Front-End ASICs for CZT and Si

Multi-Element Detectors

Gianluigi De GeronimoMicroelectronics Group, Instrumentation Division, Brookhaven National Laboratory, Upton, NY

Outline

I. Circuit Solutions

II. ASICs for CdZnTe Sensors

III. ASICs for Si Sensors

Typical front-end channel

pixel

reset

high-orderfilter

baseline stabilizer

to external ADC

amplitude and timing extractor

chargepreamplifier

shaper back-end processing & data concentration

high reliability ease of use spectroscopic quality data concentration optimization

Input MOSFET optimization

2ip

2ip2 CC

CCENC A3PA2 Af Cg

A1

P

Cg

gm

Ip Irst

0.0 0.5 1.0 1.5 2.0 2.5 3.0

0.0

0.2

0.4

0.6

0.8

1.0

1.2

Q

P

Am

plitu

de [V

]

Time [µs]

Cp Ci

IpQ

gm,Cg,Af P,A1,A2,A3

reset

gm,Cg ,Af , are functions of input MOSFET width W and power P

output

IM

10µ 100µ 1m100µ

1m

10m

100m

strong-

moderate- weak-inversion

power P = 100µW

1mW

10mW

g m [S

]

Width W [m]

Input MOSFET optimization

1µ 10µ 100µ 1m 10m 100m10µ

100µ

1m

10m

100m

strong-inversion

moderate-

weak-

width W = 10µm

100µm

1000µm

g m [S

]

Power P [W]

Cg ( CoxL+Cov )·W

Af Kf / ( CoxL·W )

gm vs P gm vs W

10µ 100µ 1m 10m0

100

200

300

400 Technology

0.50µm 0.35µm 0.25µm 0.18µm

n-channel MOSFET, P=1µs, C

p+C

i=3pF

EN

C [r

ms

e- ]

Power P [W]

0.0

0.2

0.4

0.6

0.8

1.0

Cg

/ (

Cp+

Ci )

Input MOSFET optimization

Input MOSFET optimization

100f 1p 10p 100p1

10

100

1k

10k

n-channel MOSFET, 0.5µm technology, P=1µs

Power P 100µW 1mW 10mW

FW

HM

CZ

T [e

V]

Cp+C

i [F]

0.01

0.1

1

10

Cg

/ ( C

p+C

i )

Input MOSFET optimization

Vdd

Vgc

Vgl

in

out

current source load

cascode

Vgs

input MOSFET

gm and ro are functions of Vds

Vds

Continuous reset of the preamplifier

charge preamplifier

VgrL/W>>1, strong inversion, saturation

pixel

Mf

CfIp

Q

current gain equal to N fully linear self-adapts to leakage current minimum noise contribution

1st stage of shaper

NIp

NQ

NMf

NCf

Rs

Cs

CR

Continuous reset of the preamplifier

Vgr1

24

Rs

Cs

6

Vgr2

Ip

Q

144Ip

144Q

eq2Iq

N

1

Rs

2kT An1I100kΩRs eq

Ap25I100kΩRs eq

Continuous reset of the preamplifier

0 3 6 9 12 15-0.2

-0.1

0.0

0.1

0.2

P 1µsGain 200mV/fCC

load 200pF

Cp+Ci 1.5pFIp 1nA

Cha

nnel

inte

gral

line

arity

err

or [%

]

Injected charge [fC]

0 2 4 6 8

0.0

0.5

1.0

1.5

2.0

2.5

Cp+C

i 3pF

Q 11fCGain 200mV/fCIp 250pA 70nA

Cha

nnel

out

put v

olta

ge [V

]Time [µs]

linearity output vs pixel leakage current

High order shaping

0 1µ 2µ 3µ 4µ

0.0

0.5

1.0 5th order complex

5th order non-complex

2nd order

equal 1% width

Nor

mal

ized

Am

plitu

de

Time [s]

A1/P

5th cpx 1

5th 1.24

2nd 2.64

....

CCENC ip

2

2 Cg

gm

A1

P

Output baseline stabilizer

high-ordershaper

-

+

low-freq.low-passfilter

x 1

00

+

-diff.

Vref

BS

Output baseline stabilizer

102 103 104 105 106 107104

105

106

107

108

Cha

nnel

Gai

n []

Frequency [Hz]

0.0 500.0µ 1.0m 1.5m 2.0m 2.5m-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

peaking time = 400ns, rate = 20kHz - 500kHz

BLH AC coupling

Cha

nnel

Out

put [

V]

Time [s]

transfer function performance at high rate

First generation of front-end ASICs

other features

• plug & play

• per-channel test capacitor

• programmable gain

• programmable peaking time

• high output drive capability

• high stability vs temperature

0 1 2 3 40.0

0.5

1.0

1.5

2.0

2.5

3.0

Cp+C

i 1.5pF

Q 12fCGain 200mV/fCT -30C to +50C

Ch

ann

el o

utp

ut v

olta

ge [V

]

Time [µs]

OF

Generation of front-end ASICs for CZT

Technology : 0.5µm CMOS SP3M

CZT – ASIC spectra measurements

0 200 400 600 800 10000

250

500

750

1000241

AmFWHM 4.5% at 59.5keV

CZT 3x3x7 mm3

Peaking Time P 1.2µs

Cou

nts

Channel

0 200 400 600 800 1000 12000

200

400

60057

CoFWHM 3.8% at 122keV

CZT 3x3x7 mm3

Peaking Time P 1.2µs

Cou

nts

Channel

241Am spectrum 57Co spectrum

CZT – ASIC spectra measurements

241Am spectrum 57Co spectrum

• detector thickness 3mm• detector bias -600V• resolution 4.3% at 59keV• gain 200mV/fC• peaking time 1.2µs

• detector thickness 3mm• detector bias -600V• resolution 3.5% at 122keV, 21.8% at 14keV• gain 200mV/fC• peaking time 1.2µs

CZT – ASIC applications

Solstice Gamma camera eZ-SCOPE hand held Gamma camera

• 96 CZT crystals• 3072 pixels• 192 front-end ASICs• 1.3M events/second• average FWHM 3.8% at 122keV

• 1 CZT crystal• 256 pixels• 16 front-end ASICs• 4.8M events/second• average FWHM 4.0% at 122keV

CZT – ASIC applications

Bone Densitometry – GE Lunar Detector

• 16 CZT crystals• 16 pixels 3 x 7 x 3 mm3

• 2 front-end ASICs• DEXA (Dual Energy X-ray Absorptiometry)

• ASICs replaced 17 circuit boards (over 500 components) and improved performances

Highly segmented detectors

Benefits:• Position Resolution

– pixel pitch ~ 1/N• Energy Resolution:

– CDET ~ 1/N

– IDARK ~ 1/N

– Pulse Shaping time ~ N

• Rate capability– pileup ~ 1/N

Benefits:• Position Resolution

– pixel pitch ~ 1/N• Energy Resolution:

– CDET ~ 1/N

– IDARK ~ 1/N

– Pulse Shaping time ~ N

• Rate capability– pileup ~ 1/N

N=1 N=9 N=25 N=49

Drawbacks:• Interconnect density

– density ~ N• Electronics channel count

– cost ~ N– power ~ N

Drawbacks:• Interconnect density

– density ~ N• Electronics channel count

– cost ~ N– power ~ N

DC

Data concentration optimization

ADCP/S DAQAnalog Memory+ Analog Multiplex

• can be deadtimeless

• complex control

• long readout time

• needs trigger + multiple samples

ADC

P/S

CELL ADDR

CK

...

ANLGM UX

ADC

P/S

CELL ADDR

CK

...

ANLGM UX

Both:

• slow

• inaccurate

• inefficient

• can’t trigger on randoms

Both:

• slow

• inaccurate

• inefficient

• can’t trigger on randoms

ADC

P/S DAQCONCENTRATOR

Track-and-Hold+ Analog Multiplex

• unbuffered => deadtime

• long readout time

• needs accurate trigger

T/H

ADC

P/S

T/H

T/H

SAMPLE

CK

...

ANLGMUX

T/H

ADC

P/S

T/H

T/H

SAMPLE

CK

...

ANLGMUX

Pulse amplitude extraction : classical CMOS configurations

in

HOLD

Ch

out

HOLD

timing signal needed switch charge injection poor drive capability deadtime until readout

+ power dissipation

sample/hold

-+

in

Ch

out

reset

peak-found(timing signal)

+Vdd

accuracy impaired by op-amp offsets and CMRR poor drive capability deadtime until readout

+ self-triggered+ timing signal

peak detect/hold (PDH)

The two-phase PDH concept

Write phase

• behaves like classical configuration

+-in

Ch

out

voff

Read phase

• op-amp re-used as buffer

• offset and CMMR errors canceled

• enables rail-to-rail sensing

• good drive capability

• self-switching (peak found)

+-in

Ch

out

voff

0 1 2 3 40.0

0.2

0.4

0.6

0.8

1.0

out

hold

gate ( peak-found, timing )

in

Sig

nal [

V]

Time [µs]

0 1 2 3 40.0

0.2

0.4

0.6

0.8

1.0

in

out

hold

gate ( peak-found, timing )

Sig

nal [

V]

Time [µs]

Two-phase PDH : offset cancellation

chip 1 – negative offset chip 2 – positive offset

Two-phase PDH : performance

Parameter: Value: PDDv1 (PDDv2)

Technology 0.35 um CMOS DP4M

Supply voltage 3.3V

Input voltage range 0.3 - 3.0 V

Minimum peaking time 500 (50) ns

Absolute accuracy < 0.20%

Linearity < 0.05%

Droop rate 250 mV/s

Timing accuracy 5 ns

Power dissipation 3.5 (2.0) mW/ch

PDDv1 : absolute accuracy

0.5 1.0 1.5 2.0 2.5 3.0-20

-15

-10

-5

0

5

10

15

20Peaking time

200ns 500ns 2.5µs 5.0µs

Abs

olut

e ac

cura

cy [m

V]

Pulse amplitude [V]

Derandomization with N two-phase PDHs (PDD)

0 20 40 60Time, us

READ

PDD OUT

PDD IN

PK FND

measured derandomization( M=16 , N = 2 )

ADC

Ntwo-phase

PDH

output MUX

Mfront-end channels

arbitration logic & crosspoint switch

PDD

Derandomization efficiency vs N

The larger is N, the lower can be the fo/fi ratio

1 2 3 4 5 6 7 81E-4

1E-3

0.01

0.1

1

fo / fi = 1.5

fo / fi = 2

fo / fi = ADC rate / average input rate

p = 50ns, fi = 3.2MHz

Blo

ckin

g pr

obab

ility

Number N of PDHs

1.E-05

1.E-03

1.E-01

1.E+02 1.E+04 1.E+06

Rate per channel, Hz

fo/fi =2

fo/fi =1.5

blocking probability

0

1000

2000

0 1000 2000 3000T, ns

TA

C o

utp

ut,

mV

-10

-5

0

5

10

Res

idu

als,

ns

TAC Output

Residuals

Linear (TACOutput)

TAC linearity

Derandomization efficiency and TAC linearity

32-channels PDD ASIC

CROSSPOINT32:8

INPUTS(32)

COMPARATORS

MUX8:1

ARBITRATION~ 5 ns

PD/TACs (8)tp > 50 ns

...

channelexclude/include

readout mode

TAC gainTAC mode

SPIINTERFACE

CONFIGURATIONMEMORY

digitalconvenienceoutputs

analog monitor

powerdown

FULL

EMPTY

ADDRESS

AMPLITUDE

TIME

• One-chip solution

• NCHAN = 32, NPD = 8

• Dual-mode TAC– risetime– time of occurrence

• Amplitude, address, timing outputs• 50 ns minimum pulsewidth

• tARB ~ 5 ns

• Rate capability ~ 10 MHz• SPI interface:

– serial configuration of TAC gain and mode– arbitration locking– channel exclusion– powerdown– analog monitor– Digital convenience outputs (used for

configuring companion amplifier chip)

• FIFO-like control and readout interface

• One-chip solution

• NCHAN = 32, NPD = 8

• Dual-mode TAC– risetime– time of occurrence

• Amplitude, address, timing outputs• 50 ns minimum pulsewidth

• tARB ~ 5 ns

• Rate capability ~ 10 MHz• SPI interface:

– serial configuration of TAC gain and mode– arbitration locking– channel exclusion– powerdown– analog monitor– Digital convenience outputs (used for

configuring companion amplifier chip)

• FIFO-like control and readout interface

32-channels PDD ASIC : layout

size : 3.2 x 3.2 mm²power : 2mW / channel

technology: 0.35µm CMOS DP4M

Typical fluorescence EXAFS measurement geometry

Sample

Detector

ResolutionRate

sensor

electronicsfront-endprocessingreadout

FL

Resolution vs rate

1k 10k 100k 1M10

100

1k

10k

1

12

118

1182

1pA

10pA

Ileak

= 100pA

Rm

s el

ectr

ons

F

WH

MS

i [eV

]

rate [Hz]

prateCC ip

1

NrateRate

rateleak

2

IA

1···5.0)(ENC 1

2p -

NP

NRate

CNC ip

Optimum pixellation

charge sharing (20µm/side) and trapping (gap/side) : empirical

Optimum pixellation

10 100 1k100

1k

10k

12

118

1182

400

P = 3W, p2 = 5mW

L = 20mm

cpa

= 400fF/mm2, c

pf = 75fF/mm

Ci = 300fF

p2 = 4mW

Rate = 10MHz

40MHz

Rm

s el

ectr

ons

F

WH

MS

i [eV

]

Pixel count N

quadrant(812=96 pixels)

96-channel front-end(3 32 channel ASICs)

Peltier

20mm

Si n-type high resistivity wafer 250µm thick,N = 384 p+ 1mm1mm pixels,

gaps 10µm, 30µm, 50µm

Beam through

samplesensor

Interconnecting pixel to front-end electronics

ASIC

sensor

+ interconnect parasitic+ bond length- fringe capacitance- charge sharing and trapping

+ bond length- interconnect parasitic- dielectric losses

ASIC

sensor

ASIC

sensor

ASIC

sensor

+ interconnect parasitic- constraint on ASIC area and layout- fluorescence from Pb (Sn/Pb/Ag)- illumination from segmented side

+ dielectric losses interconnect parasitic- bond length

6mm10µm, Si3N4 (r=6.5,tan()=0.001), 3µm, Ci1.2pF

IC

quadrant

Sensor – ASIC photo

Front-end channel overview

pixel

charge preamplifier discriminators & counters

low-noise reset

high-ordersettablefilter

output baseline stabilizer

1 threshold2 window

6-bit DACs for fineadjustment

24-bit

SPI

shaper

readout

5 mW 3 mW

Technology CMOS 0.35µm 3.3V 2P4M

Layouts

3 24-bit COUNTERS - 690µm

100µm

4 6-bit DACs analog - 590µm

DACS digital - 170µm5 COMPARATORS - 130µm

100µm

100µm DAC cell

COUNTER cell

ASIC overviewCMOS 0.35µm 3.3V 2P4M

180,000 MOSFETs, size 3.6 6.3 mm2

8mW / channel

32 readout channelsself adaptable continuous reset

high order shapersettable peaking time (0.5µs, 1µs, 2µs, 4µs)

settable gain (750mV/fC, 1500mV/fC) band-gap referenced output baseline

output baseline stabilization (BLH)1 threshold and 2 window discriminators

4 6-bit DACs for fine window adjustments3 24-bit counters

test modeanalog output monitor

pixel leakage current monitor 

Serial Peripheral Interface (SPI)global settings

monitors enablingtest enabling

channels maskingDACs setting

counters readout

charge preamplifier shaper with BLH discriminators and DACs counters

32 channels, 3.6 6.3 mm2

ASIC photo

Settable gain and peaking time

0 5µ 10µ 15µ0.0

0.5

1.0

1.5

2.0

Peaking time : 0.5, 1, 2, 4 µsGain : 750, 1500 mV/fCQ

in = 1fC

A

mpl

itude

[V]

Time [s]

EX

0 4 8 12 16 20 24 28 321.65

1.70

1.75

1.80

1.85

before correction - after correction - (21eV)

Thr

esho

ld d

ispe

rsio

n [V

]

Channel

Correction of threshold dispersion

Energy resolution

100n 1µ 10µ100

200

300

400

500

12

24

35

47

59

no sensor

1pA

5pA

60pA

+25°C -15°C -35°C

Rm

s E

lect

rons

F

WH

MS

i [eV

]

Peaking time [s]

Si – ASIC spectra measurements

0 1k 2k 3k 4k 5k 6k 7k 8k0

100k

200k

300k

400k

55Fe Energy Spectrum

temperature -35°Crate 10kHz peaking time 4µs

FWHM (Mn-K) 205eV

electronic noise 167eV (20e-)

channels & discriminators enabledcounters disabled

C

ount

s

Energy [eV]

Si – ASIC spectra measurements

0 1k 2k 3k 4k 5k 6k 7k 8k0

5k

10k

15k

20k

25k55

Fe Energy Spectrum

temperature -20°Crate 10kHz peaking time 4µs

FWHM (Mn-K) 250eV

electronic noise 220eV (26e-)

channels & discriminators enabledcounters enabled

C

ount

s

Energy [eV]

Si – ASIC spectra measurements

0 1k 2k 3k 4k 5k 6k 7k 8k0

100k

200k

300k

400k55

Fe Energy Spectrum

temperature -20°Crate 100kHz peaking time 2µs

FWHM (Mn-K) 324eV

electronic noise 301eV (35e-)

channels & discriminators enabledcounters enabled

C

ount

s

Energy [eV]

Readout

RO

Readout interface

Automatic threshold equalization

before correction after correction

Current EXAFS detector

head - preamplifiers

rack – shapers … 100 channels, > 350 eV, < 1 MHz

New EXAFS detector

400 channels, < 300 eV, > 10MHz

Acknowledgment

P. O’ConnorLayout : A. Kandasamy

Technical : J. Triolo, D. Pinelli