Outcome from the VMM/sTGC Workshop at Weizmann Institute May 14-15, 2015 Gianluigi De Geronimo Brookhaven…

Outcome from the VMM/sTGC Workshop at Weizmann Institute

May 14-15, 2015Gianluigi De Geronimo

Brookhaven National Laboratory, Upton, NY

Acknowledgement Brigitte Vachon, Vladimir Smakhtin, Alex Vdovin, Nachman Lupu, Benoit Lefebvre,

George Mikenberg, Lorne Levinson, Daniel Lellouch, Venetios Polychronakos

May 22nd, 20151

Saturation Issue with TGC Sensors

from B. Lefebvre, V. Smakhtin and B. Vachon, April 2015 2







Front-End Circuit

CA1 output

CA1 CA2 CA3

BLH

SH

Shaper outputadaptive resets

with PZ cancellation

CA1, CA2, CA3 provide charge (current) amplification before shaperAmplification is required for noise, and it is programmable

6 from G. De Geronimo, December-April 2015

TGC 200pF 2pC

iin

Qin

CA1

CA2

CA3

out 500mV + tail

2pC


iin

Qin

CA1

CA2

CA3

out 900mV no tail

4pC

saturation

baseline tail (several µs)

TGC 200pF 4pC


9

Qout = Qin ·NQin

-∞

CF CF·N

N1

Ibias

-∞

N1

Ibias

sp

sp

sp

sn

sn

sn

from sensor

to virtualground

Dual-Polarity Charge Amplifier

from G. De Geronimo, December-April 2015

τF Correction for Type 1 Dead Time

500 fC @ 200ns

Output

CA1

2pC

Solution: CA time constant τF ~1/10 by modifying size of feedback MOSFETs

in saturation deadtime limited to sub-µs


Origin of Type 2 Dead Time ?


AC-Coupled Charge Amplifier

CAC = 100 pF

CDET = 100 pF

RDET = 10 MΩ

Charge signals

Ideal charge amplifier

Ideal charge amplifier with AC-coupled charge signals

12


ICAC (input current through CAC)

Charge amplifier output

Response of charge amplifier to AC-coupled charge signals

t = RFCF

200µs

13





t = RFCF

10µs

Detail

14





10µs

sRDETCAC

1 + sRDET(CDet+CAC)Transfer function =

(derivative of exponential decay)

Detail

15





10ms

t = RDET(CDet+CAC)

sRDETCAC

1 + sRDET(CDet+CAC)Transfer function =

Detail

16


Charge amplifier output: zero-area response


10ms

17


Charge amplifier output: zero-area responseNegligible dependence on rate: 10kHz and 100kH compared here


10ms

18

The front-end electronics has to be able to cope with these shifts

AC-Coupled Charge AmplifierResponse of charge amplifier to AC-coupled charge signals

10ms9.3ms

Detail

19

Charge amplifier output: zero-area responseNegligible dependence on rate: 10kHz and 100kH compared here

The planned decrease in time constant will partly reduce the positive shift

20

Qout = Qin ·NQin

-∞

CF CF·N

-∞

N1

Ibias

from sensor

to virtualground

VMM1/2 Charge Amplifier for Positive Charge

DC source to bias mirror and recharge input node ~500pA

A non-linear asymmetry exists in MOSFET-based integrated front-ends

AC-Coupled VMM1/2 Front-End

CAC = 470 pF

CDET = 100 pF

RDET = 10 MΩ

Charge signals

VMM1 FE

Actual charge amplifier with AC-coupled charge signals

Ideal Filter

amplifier

adaptive resetleakage current

Iout

CAout

SHout

21

Voltage amplifier output (CAout)


200µs


Charge amplifier current output (Iout)

Shaper output (SHout)

22



10µs


Charge amplifier current output (Iout): note pole-zero cancellation


Detail

23



30ms




10kHz, 1pC, leakage 500pA

24


Response of charge amplifier to saturating AC-coupled charge signals

30ms




10kHz/1kHz, 1pC/10pC, leakage 500pA

25


Response of charge amplifier to saturating AC-coupled charge signals

30ms




10kHz/1kHz, 1pC/10pC, leakage 5nA

26

An increase in DC leakage current alleviates saturation



30ms





27

The increase in DC leakage current can be high, but it increases the noise na it may eventually limit the dynamic range


Response of charge amplifier: higher charge and rate

30ms





28


Response of charge amplifier: higher charge and rate

30ms





Detail

29

29.3ms

Solutions Being Integrated• Decrease discharge time constant for fast recovery from

saturation and high-rate operation• Double size of feedback capacitance to reduce voltage swing• (Implement switchable DC current)• Modify feedback for dynamic compensating current

Qout = Qin ·NQin

-∞

CF CF·N

N1

-∞

N1

Ibias

from sensor

to virtualground

compensating current Replica to preserve

pole-zero cancellation

30

Note: work in progress

Description of experimental setup and observations made at the Weizmann Institute on 15 May 2015.

1) Readout of small sTGC prototype strips

2) Readout of Module-1 sTGC pad

31 from Brigitte Vachon and Vladimir Smakhtin, May 2015

1) Readout of small sTGC prototype strips Small 10x20 cm2 prototype sTGC with strips on both sides. Chamber operated at nominal operational HV of 2.9kV Look at signals from Sr-90 radioactive source (rate ~ 10 kHz)

+HV

G10

G10

wiresgraphite

graphite

strips

strips


Observed change in efficiency as function of current injected into the VMM1

Efficiency observed to reach maximum for current of approximately 60 nA.

1) Readout of small sTGC prototype strips Use VMM1 readout

Look at VMM1 analogue pulse Gain = 0.5 mV/fC, Peak Time = 25 ns, Neighbour channel = off

Use pull-up resistor (20 MΩ) on sTGC adaptor board to inject small variable current into VMM1.

VMM1

+ 2 V

20 MΩ


1) Readout of small sTGC prototype strips Recorded raw signals from strips on opposite side of the detector Raw signals used as input to Gianluigi's simulation

Raw signalChannel 4

50 Ω

+ 2 V

20 MΩ

Strip on top cathode

Strip onbottom cathode

OscilloscopeAgilent, MSO-X 4054A

VMM1 analog output, Channel 2


35

1) Readout of small sTGC prototype strips

Raw stripsignal from small 10x20 cm2

prototype

VMM1 analogueoutput


2) Readout of sTGC Module-1 pad Chamber operated at nominal operational HV of 2.9kV

Look at signals from Sr-90 radioactive source (rate ~ 1-3kHz) Readout pad with VMM1

Look at VMM1 analogue pulse Gain = 0.5 mV/fC, Peak Time = 25 ns, Neighbour channel = off

Use pull-up resistor (20 MΩ) on adaptor board to inject small variable current into VMM1.

Observed change in efficiency as function of current injected into the VMM1 (optimal value observed to be approximately +60nA)

Record VMM1 analogue pad readout using +2 V DC on 20 MΩ pull-up resistor (from ~1V input equals to ~60nA).


2) Readout of sTGC Module-1 padSr-90 source

VMM1

+2 V DC on 20 MΩ pull-upresistor


38

VMM1 analogueoutput

2) Readout of sTGC Module-1 pad


Note from Vladimir Smakhtin

39

"During the meeting we have measured signals from strip 10x20 cm2 sTGC.

- after optimization Voffset from 1.2V to 2V value by eye we achieved 100% efficiency at operation HV=2.9kV and rate per channel ~ 3kHz,- for this test we are using original method for strip efficiency using two identical up and down strips- we have protocol and raw files( full set which needed for modeling and simulation)

After mini meeting we started tests with Module-1 and pad.

- alignment of Co-60 and optimization of Voffset using scope have been completed- developing method for measure rate and efficiency- we have some very preliminary results- the results of this activity will be reported in a next meeting"

40

Pad capacitance

Amplifier-Shaper-Discriminator Ics and ASD boards, October 1999 (and re-calculated for sTGC)

[Note: Largest pad: Area = 470 cm2]

C PG=710 pF (measured )

C PW=(0.30 pF/cm 2)× A pad=50 pF

C PP=0 pF (measured )

C PH=(0.15 pF/cm 2)×Apad=25 pF

C PC=k ϵ0 Apad

d∼3500 pF

k∼4.7ϵ0=8.854×10−12 F/md=0.1 mm

ϯ

ϯ

ϯϯ

ϯϯ

Example: Area = 164 cm2 (pad 7)

Taken from: https://indico.cern.ch/event/371991/contribution/1/material/slides/0.pdf

0.2

mm

+HV

1.5

mm

G10

G10

CPW

CPGCPP

CPH

pad-to-padvia honeycomb

CPC

from Brigitte Vachon and Vladimir Smakhtin, May 2015

41

sTGC cross-section

J. Oliver, “ATLAS Muon New Small Wheel Grounding, Power and Interconnect - Guidelines and Policies”,

https://edms.cern.ch/file/1428856/1/NSW_Grounding_Architecture_v2_20150202_PDR.pdf

from Brigitte Vachon and Vladimir Smakhtin, May 2015

Additional Discussions 1/2

from Nachman Lupu, May 2015 42

Average rate as high as 1MHz

Capacitance as high as 2nF

Additional Discussions 2/2• Acquisition reset (soft reset)

• Done at falling edge of ENA• Configuration from SCA (CS,CK,DI,DO)

• SPI in chunks of 96 bits• Use one of 96 bits to generate global reset (hard reset)• CS active low (to be confirmed)

• SEU mitigation• Use DICE or similar for registers• Use TMR for state machines

• Direct 6-bit output dead time• Same as high-resolution in simultaneous mode

• Need for L0 buffers and selection logic in VMM• May be moved off-chip and replaced with double, higher

bandwidth data lines (4 x 320MHz, DDR)

43

Issue Circuit Solution Status Complexity

VMM3 Priority

Schematics

Layout

TGC saturation: high-charge, high-rate

Front-end Fbk time const., fbk capac., dynamic current

in prog. mid high in prog. in prog.

MSB accumulations in 10-bit and 8-bit ADCs

ADC decision nodes, PSR

TBD queued mid high

Data repetition Token/FIFO logic Token-reset, FIFO alignment in prog. mid high in prog. in prog.

High-rate efficiency (discrim.) Shaping amplifier Bipolar resp. (SLF bypass) in prog. low high in prog. queued

BCID consistency Gray-code counter Clock inversion done low high done done

Direct timing enable Control logic Logic inversion done low high done done

Event loss from ADC reset Channel logic Logic fix and routing in rpog. low high done in prog.

Threshold bit error Channel logic Logic fix done low mid done done

DAC compression FET compression MOSFET size and biasing done low mid done done

Pulser rise-time, noise Injection switch Size optimization done low mid done done

Counter turnaround Counter cells Re-routing done low mid done done

Front-end disabled in negative mode with SFM low

Front-end TBD queued low mid in prog. in prog.

High baseline channels Baseline stabilizer Increase BLH current meas. low low queued

Buffer float at bypass Buffer input stage Add switch simul low low done done

Decay time in peak detector in analog readout mode

Leakage hold node Dual front-end circuit for voltage and current-mode

simul mid low queued

Fixes (May 2015)

44

Function Circuit Notes Status Complexity

VMM3 Priority

Schematics

Layout

TGC pads 2nF Front-end See also recovery from saturation in prog. mid high in prog. in prog.

Simultaneous high-res. & direct-out

Channel and control logic

Channel reset defined queued mid high

Single-ended config. IOs Interface 1.2V logic queued low high

Double data-out lines/rate Interface 4 SLVS diff. output lines, 320 Mb/s DDR queued low mid

SLVS IOs Digital IOs Standard 200mV +/- 200mV in prog. low mid in prog. queued

Latency reduction in analog path

Shaping amplifier

Optional order reduction queued mid mid

Latency reduction in digital paths

Readout logic

Concerns latencies for direct and slow outputs (ck-to-data)

queued mid mid

Timing ramp optimization Analog TAC Reduce from 125ns to 65ns done low mid done done

Configuration interface Interface SPI 96-bit w/reset bit queued mid mid

Synchronous ART flag ART logic Flag synchronous with ART clock hold low mid

SEU-tolerant logic Registers & control

Configuration and state, DICE static + TRM state

queued mid mid

Timeout circuit Analog TAC Timeout if no ramp-stop within 1µs queued low low

L0 handling logic Readout See Lorne's document hold

Improvements (May 2015)

45

Conclusions• Saturation in VMM1/2 has been observed with TGC

prototypes• component due to amplitude saturation and long discharge time

constant in charge amplifier - will be addressed with decrease in time constant, increase in feedback capacitance and, if required, fast recovery feedback

• component due to shift in charge amplifier output baseline from ac-coupling - will be addressed with increase in feedback capacitance, dynamic compensation current and, if required, programmable dc leakage current

• workaround with injected dc current alleviates saturation, being tested at Weizmann

• saturation type 2 indicates existence of ac-coupling in detector signal path

• VMM3 design revision in progress, target July 2015• we will integrate high and medium-priority items; low-priority items as

time allows• very limited time to compete the tasks, which increases risks46

Backup Slides

47

Q

Rs

Cs

xN QxN

xN

charge amplifier

shaper

Charge Amplifier Detail

· simplified schematics· positive charge circuit

pole-zero cancellation(charge gain = N)

CF ≈ 2.3 pF

amplitude ~ Q/CF

time constant τF from size of MF and amplitude

MF

F

P

F

PFeargdisch e600CkT

21ENC

from non-stationary noise

48

Documents

Outcome from the VMM/sTGC Workshop at Weizmann Institute May 14-15, 2015 Gianluigi De Geronimo Brookhaven…