Trends in Front-End ASICs for Particle Physics

Gianluigi De Geronimo Brookhaven National Laboratory

degeronimo@bnl.gov , +1(631)344-5336

TIPP - Amsterdam - June 2014

Outline

• CMOS Technologies

• ASICs for Particle Physics

• Challenges and Paradigm

Microelectronics

Art of combining micrometer-scale components into a single monolithic device: Integrated Circuit (IC)

The most widely adopted IC technologies use the MOSFETMetal-Oxide-Semiconductor Field-Effect Transistor

~ 20,000 µm ~ 20 µm

L

D G S

The Rapid Evolution of Microelectronics

1960 1970 1980 1990 2000 2010 2020 2030 2040

1n

10n

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1µ

10µ

1MHz

first MOSFET

first IC

Intel 4004Tra

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ie

1960 1970 1980 1990 2000 2010 2020 2030 2040

1n

10n

100n

1µ

10µ

> 3GHzXbox One 28nm

6-core I7 45nm

Intel 80286

first MOSFET

first IC

Intel 80486

10-core XEON 32nm

Tra

ns

isto

r ch

an

ne

l le

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1MHz

Intel 4004

100

1k

10k

100k

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10M

100M

1G

10G

100G

Nu

mb

er

of

tra

ns

isto

rs / d

ie~ 20 -1 every 20 years

~ 202 eve

ry 20 ye

ars

From Planar FET to FinFET (3D FET)

Conducting channels on three sides of a vertical "fin" structure, providing "fully depleted" operation - introduced in late '90s

• Combine 20nm-Planar FETs and sub-20nm FinFETs

• 55% drop in power dissipation or 35% boost in speed compared to 28nm-Planar

Planar FET FinFET (3D FET)

The Rapid Evolution of Microelectronics

1960 1970 1980 1990 2000 2010 2020 2030 2040

1n

10n

100n

1µ

10µ ~ 20 -1 every 20 years

~ 202 eve

ry 20 ye

ars

Exotic Transistors• single-electron• carbon-nanotube• ...

Introduced in the ’90s, exotic transistors made considerable progress, but are still far from achieving reproducibility and reliability required by microelectronics

High-Density Interconnects - 2.5D and 3D

2.5D TSVactive dies

passive Si interposer with planar and vertical (TSV) interconnects

micro-bumps

active die

active dies with TSVsflip-chip bumpsstack many dies with different functionalities

micro-bumps

3D TSV

· Through-Silicon Via (TSV) vertical interconnects through active or passive die - µm diameter· Micro-Bump / Metal-Metal Bonds2D interconnects - µm size

1960 1970 1980 1990 2000 2010 2020 2030 2040

1n

10n

100n

1µ

10µ

The Rapid Evolution of Microelectronics

Progress heavily driven by consumer electronics

~ 20 -1 every 20 years

~ 202 eve

ry 20 ye

ars ?!

TSVExotic Transistors• single-electron• carbon-nanotube• ...

Semiconductor Market

PP has little chance to make an impact on evolution

Bil

lio

n D

oll

ars

YearPP

50M?

computing

communications

storage

controlmedical industrial

entertainment

toys

Microelectronics and Particle Physics

Radiation Detectors ?

data processing and computing,communication,...

Require custom-designed front-end electronics frequentlyin the form of Application-Specific Integrated Circuits

• optimized front-end circuit• small physical size• low power dissipation• radiation tolerance• cost (in context of whole detector)• ...

Front-end ASIC

AMPLEX (1988) - First Large Scale

16 channels, ~800 MOSFETs (~50/ch)3µm CMOS, 5V, 1.1 mW/ch, 16 mm²amplifier/filter/track & hold/muxfor Silicon micro-strips at UA2

Institute WG1Radiation

WG2Top level

WG3Sim./ Ver

WG4I/ O

WG5Analog

WG6IPs

Bari C A A

Bergamo-Pavia A C A B

Bonn C A A B B A

CERN B(*) (*) A C(*) A B(*)

CPPM A B C C B A

Fermilab A B A

LBNL B A B B A A

LPNHEParis A B A A

NIKHEF A A A

New Mexico A

Padova A A

Perugia B A B

Pisa B A A A

PSI B A C A A

RAL B B A C

Torino C B C B A A

UCSC C B C A

FE-I5 (2016-17?)

260k pixels, 1G MOSFETs (~4,000/px)65nm, 1.2V, 0.5-1 W/cm², >400mm²high complexity/functionality, DSPfor ATLAS vertex hybrid pixels

19 institutionsspecialized working groups

100 collaborators(~50 ASIC designers)

ARCHITECTURE 2X2 pixel unit

Compare to Evolution of Microelectronics

Delay from characterization, prototyping prices, resources

1960 1970 1980 1990 2000 2010 2020 2030 2040

1n

10n

100n

1µ

10µ

VMM

Xbox One

6-core I7 FE-I5

FE-I4

FILASAMPLEX

first MOSFET

first IC

Tra

ns

isto

r ch

an

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1k

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VMM (2015-16?)

64 channels, >6M MOSFETs (>80k/ch)130nm, 1.2V, 0.4 W/cm², >110mm²high complexity/functionality w/DSPfor ATLAS muon spectrometer/tracker V. Polychronakos

New Small WheelssTGC , MicroMegas, 2.3M channels

analog1

data1data2

analog2

CA shaper

logic

orneighbor

addr.

6-b ADC

ART (flag + serial address)ART clock

12-b BC

Gray count

10-b ADC

8-b ADC

BC clocklogic

time

peak

4XFIFO

data/TGC clock

mux

tk clockpulser

trim

bias registerstp clock

TGC out (ToT, TtP, PtT, PtP, 6bADC)

tempDAC reset

test

64 channels

analog mon.

prompt

DSP

Impact on ATLAS New Small Wheels

• 60x sensing elements (32k→2M), 10x element density (5→0.5 mm)• 3x power dissipation (300→15 mW/element)• comparable data-transfer bandwidth, fully data-driven, discrimination• trigger primitives, timing measurements, programmable polarity

2005 - ASM 2015 - VMM

(1) FE ASICs will become very-high-complexity systems-on-chip (SOC) and will require high-density interconnects

1980 1990 2000 2010 20200

20

40

60

80

N

umbe

r of

des

igns

Year

Number of front-end ASICs for PPrunning and in design

(2) The demand for FE ASICs is increasing

Front-end ASICs vs Year

2013~ 60 FE (out of ~140)~ 35 FE in design

sources: HEPIC 2014 White Paper et al.

0

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30

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50

Num

be

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IC D

esig

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running in design

Estimate 2013

allfront-end

Front-End ASICs vs Technology

(3) PP ASICs are keeping pace with technology

complexityavailability

pricesresources

The PP-ASIC Paradigm

Advances in Particle Physics detectors are tightly coupled to advances in

ASICs and associated interconnects

Complexity

Demand

Technology

PP ?ASIC ?

design groups ≈ 30-40

Design Groups – Current Status

active designs ≈ 30-40

Average one design per group• institutions leading collaborative efforts• institutions performing R&D on technologies

One FE-ASIC design currently requires2-4 full-time designers and 2-4 years

average, from concept to ready-for-production

...

...

...

...

CLIC

FE-I5

ABCLAPAS

VMMFSSR2

APV25

KPIXBEAN

nEXO

ASDQNOvA MAPS3D

ISR3BTARGET

ASDCDCSAO3

POM

SALT

PACIFICCLARO MAROC3

ICECAL

VELOPIX

LBNE

...

......

SAMPA

...

QIE

CBC

In order to be efficient and maintain state-of-the-art ASIC groups must:• develop 1-2 new designs and 2-4 revisions per year• work with 2 technologies (re-usage & next)• perform R&D on circuits and technologies

PP currently supports/uses up to 25-30 %

The critical minimum is currently 5-6 designers

Design Groups – Current Status

Need to diversify while contributing to PP with an average of 25-30 % of resources

The PP-ASIC Paradigm

The number of ASIC designers has to increase !

Complexity

Demand

Technology

PP ?ASIC ?

involve non-PP ASIC groups

increase size of PP ASIC groups

Collaborations ?• only part of the solution• communication• overhead• lead of large group

In order to contribute to future PP detectors FE ASIC groups need to:

• grow (30-40%)• increase collaborations (know-how exchange)• develop/acquire "system-level FE ASIC designer"• develop/acquire "high-density interconnects“• align technologies• evolve and coordinate R&D

Evolution of Front-End ASIC Design Groups

PP community needs to contribute with 25-30%

Alternative? Pay companies (hundreds M$)

Aligning Technologies

Long-lasting choice (re-usage)

Collaborations (know-how)

skip technologies ... ~ jointly

• Specialized groups must perform characterization• Initial phase of pioneering projects (large groups)• Some exceptions for specialized technologies

Coordinating R&D

R&D on enabling circuits/technologies• low-power ADCs• low-power DSP (auto-calib., data red., program., ...)• low-power high-speed communication (standards)• low-power low-voltage analogs• high dynamic range, waveform sampling• high-density interconnects (2.5D, 3D - incl. sensors)• cryogenic• MAPS• ...

When to exit/enter a technology ?• exit too late may result in limited collaborations• enter too early may result in waste of resources

keep

< 1

W/c

m²

Conclusions

G. C. Smith, V. Radeka, BNL Microelectronics, CERN, PP FE ASIC Community

Acknowledgment

Advances in PP detectors are tightly coupled to advances in front-end ASICs and associated interconnects

Front-end ASICs:• dramatic increase in complexity/functionality (SOC)• increase in demand• need to keep pace with the technologies

ASIC groups:• increase size and collaborations (know-how)• perform R&D towards SOC and interconnects• align technologies and coordinate R&D

IC Designer in a “Collaboration”

Prototyping Prices

Prototyping costs are increasing (price, size)

0

50k

100k

150k

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250k

2019?

2014

2024?2004

2014 average MPW pricefor a 16mm² prototype

Ave

rage M

PW

Pri

ce

Technology

prices 1/2 every ~5 years