EVAL-ADIN1300FMCZ User Guide - Analog Devices · The EVAL-ADIN1300FMCZ can be used in two general modes. In standalone mode, the EVAL-ADIN1300FMCZ can be used to evaluate the ADIN1300

EVAL-ADIN1300FMCZ User Guide UG-1635

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Evaluating the ADIN1300 Robust, Industrial, Low Latency, and Low Power

10 Mbps, 100 Mbps, and 1 Gbps Ethernet PHY

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 30

FEATURES FMC connector for MII interface, MDIO signals, and status

signals Accessible, surface-mount configuration resistors and dial

switches Operates from a single, external 5 V supply

EVALUATION KIT CONTENTS EVAL-ADIN1300FMCZ evaluation board MDIO interface dongle

EQUIPMENT NEEDED Power supply (choose one of the following):

5 V power supply rail to connect to the EXT_5V connector 5 V barrel adaptor to connect to the P4 plug

Ethernet cable USB cable PC running Windows 7 and upward

SOFTWARE NEEDED Ethernet PHY software and GUI (available to download on

the ADIN1300 product page)

DOCUMENTS NEEDED ADIN1300 data sheet

GENERAL DESCRIPTION The EVAL-ADIN1300FMCZ allows simplified evaluation of the key features of the ADIN1300 robust, industrial, low latency gigabit, 10 Mbps, 100 Mbps, and 1 Gbps, Ethernet physical layer (PHY). The EVAL-ADIN1300FMCZ is powered by a single, external, 5 V supply rail that can be supplied either via the EXT_5V connector or via the P4 plug.

All chip supplies are regulated from the 5 V rail providing supply rails required for AVDD3P3, VDD0P, and VDDIO.

The P3 field programmable gate array (FPGA) mezzanine connector (FMC) connector is provided for connection to a master FPGA system for the media access control (MAC) interface and management data input/output (MDIO) control. The P5 connector provides an alternative means for MDIO control. The EVAL-ADIN1300FMCZ is fitted with a 25 MHz crystal (Y1).

For complete specifications for the ADIN1300 device, see the ADIN1300 data sheet, which must be consulted in conjunction with this user guide when using the EVAL-ADIN1300FMCZ.

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UG-1635 EVAL-ADIN1300FMCZ User Guide

Rev. 0 | Page 2 of 30

TABLE OF CONTENTS Features .............................................................................................. 1

Evaluation Kit Contents ................................................................... 1

Equipment Needed ........................................................................... 1

Software Needed ............................................................................... 1

Documents Needed .......................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

EVAL-ADIN1300FMCZ with Optional MDIO Interface Dongle Connected .......................................................................................... 3

Evaluation Board Hardware ............................................................ 4

Power Supplies .............................................................................. 4

Power Sequencing ........................................................................ 4

Evaluation Board Usage Options ............................................... 4

Jumper Options ............................................................................ 4

Clock Options ............................................................................... 4

On-Board EEPROM and LEDs .................................................. 5

ADIN1300 LED Pin ..................................................................... 5

MDIO Interface ............................................................................ 5

MDIO Interface Dongle .............................................................. 6

Configuration Pins Setup ............................................................ 6

Software Overview ........................................................................... 8

Installing the Ethernet PHY Software ....................................... 8

Initial Setup ................................................................................... 9

Using the Evaluation Software ...................................................... 10

GUI Detailed Overview ................................................................. 11

Board Display Showing Connected EVAL-ADIN1300FMCZ Hardware ..................................................................................... 11

User Buttons Section .................................................................. 11

Link Properties Tab .................................................................... 12

Register Access Tab .................................................................... 13

Clock Pin Control Tab ............................................................... 13

Loopback Tab .............................................................................. 13

Testmodes Tab ............................................................................ 13

Framechecker Tab ...................................................................... 14

Cable Diagnostics Tab ............................................................... 14

Activity Window and Linking Status ....................................... 15

Activity Log Information Section ............................................ 15

Loading a Script File .................................................................. 16

Troubleshooting .............................................................................. 17

Software Installation Tips.......................................................... 17

Software Tips .............................................................................. 17

Hardware Tips ............................................................................ 17

Layout Guidelines ........................................................................... 18

Board Stackup ............................................................................. 18

Ground Planes ............................................................................ 18

Isolation Guidelines ................................................................... 18

Power Supply Decoupling ......................................................... 18

MAC Interface ............................................................................ 18

Management Interface ............................................................... 18

Placement of the TVS Diode .................................................... 18

Thermal Considerations ............................................................ 18

Evaluation Board Schematics and Artwork ................................ 19

Ordering Information .................................................................... 27

Bill of Materials ........................................................................... 27

REVISION HISTORY 10/2019—Revision 0: Initial Version




EVAL-ADIN1300FMCZ WITH OPTIONAL MDIO INTERFACE DONGLE CONNECTED

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Figure 1.




EVALUATION BOARD HARDWARE POWER SUPPLIES The EVAL-ADIN1300FMCZ operates from a single, external, 5 V supply rail.

Apply 5 V either to the P4 plug or to the EXT_5V connector with the JP3 jumper configured for 5 V at Position A.

The rest of the EVAL-ADIN1300FMCZ power requirements are generated from the 5 V supply. Two on-board ADP223 devices generate the AVDD3P3, VDDIO, VDD0P9, and DVDD power rails. The default nominal voltages are listed in Table 1.

The VDDIO voltage rail defaults to 2.5 V with the installed components, and may be adjusted if other VDDIO voltages are required by changing the value of the R16 resistor accordingly, as shown in Table 1.

Table 1. Default Device Power Supply Configuration Supply Rail Nominal Voltage Adjustment AVDD3P3 3.3 V Not applicable VDDIO 2.5 V 1.8 V with R16 = 130 kΩ 2.5 V with R16 = 200 kΩ 3.3 V with R16 = 280 kΩ VDD0P9 0.9 V Not applicable DVDD 3.3 V Not applicable

Table 2 shows an overview of the EVAL-ADIN1300FMCZ current for various operating modes.

Table 2. EVAL-ADIN1300FMCZ Quiescent Current (EXT_5V = 5 V) Board Status Typical Quiescent Current On Power-Up 30 mA initially 6.5 mA in energy detect power

down (EDPD) mode In Hardware Power-Down

(RESET_N Held Low) 6.5 mA

10BASE-Te 50 mA 100BASE-TX 60 mA 1000BASE-T 145 mA

POWER SEQUENCING There is no particular power sequence required for the ADIN1300 device.

When using the EVAL-ADIN1300FMCZ with the MDIO interface dongle, there is a known sequence requirement for the MDIO interface dongle. The MDIO interface dongle should be powered from the USB cable prior to connection to the EVAL-ADIN1300FMCZ. Alternatively, if issues are observed, restart the GUI software to resolve any board connection issues.

EVALUATION BOARD USAGE OPTIONS The EVAL-ADIN1300FMCZ can be used in two general modes. In standalone mode, the EVAL-ADIN1300FMCZ can be used to evaluate the ADIN1300 in IEEE 802.3 test modes, establish links with a link partner, and evaluate the performance of the

chip. In standalone mode, power the EVAL-ADIN1300FMCZ with a 5 V supply at the EXT_5V connector.

Alternatively to standalone mode, the EVAL-ADIN1300FMCZ has an FMC low pin count (LPC) connector, which can be plugged into an FPGA development board. When used with an FPGA board, the media independent interfaces (MIIs), clocks, and light emitting diodes (LEDs) can be connected to the FPGA board where the MAC and upper layers can be implemented for evaluation of the ADIN1300 in a full system.

JUMPER OPTIONS A number of jumpers on the EVAL-ADIN1300FMCZ must be set for the required operating setup before using the EVAL-ADIN1300FMCZ for evaluation. The default settings and functions of these jumper options are described in Table 3.

Table 3. Default Jumper Options and Descriptions Link Position Function JP1 Not

inserted Do not install (DNI).

JP2 B (high) This jumper sets the write mode of U7. Position A (low): enable writing to the

electrically erasable programmable read only memory (EEPROM).

Position B (high): WP the EEPROM (default). JP3 A (5V) This jumper sets the 5 V supply source. Set

to Position A. Position A (5V): either P4 or EXT_5V is the 5 V

supply source (default). Position B (12V): This circuit is not installed.

JP3 should always be set to Position A.

CLOCK OPTIONS The EVAL-ADIN1300FMCZ provides the option to supply the ADIN1300 clock requirements from either an on-board crystal oscillator, or an external clock applied to the J1 connector.

The crystal oscillators on the EVAL-ADIN1300FMCZ and the MDIO interface dongle include the following:

Y1 is a 25 MHz crystal connected across the XTAL_I pin and XTAL_O pin of the ADIN1300 on the EVAL-ADIN1300FMCZ.

Y2 is a 32.768 kHz crystal used on the MDIO interface dongle for the on-board ADuCM3029.

Y3 is a 26 MHz crystal used on the MDIO interface dongle for the on-board ADuCM3029.

When a 25 MHz external clock is applied to the J1 connector, the R120 resistor must be populated and the R15 and R119 resistors must be removed to disconnect the Y1 crystal. The 25 MHz clock must be a sine or square wave signal with an input range of 1.8 V to 2.5 V. See the ADIN1300 data sheet for more information.







https://www.analog.com/ADuCM3029?doc=EVAL-ADIN1300FMCZ-UG-1635.pdf

https://www.analog.com/ADP223?doc=EVAL-ADIN1300FMCZ-UG-1635.pdf





The ADIN1300 can also be configured to provide a 25 MHz clock output on the CLK25_REF pin, which is available on the FMC connector. The source of this clock is the on-board Y1 crystal. Note that when a pin reset is applied to the ADIN1300, the clock disappears for the duration of the reset and must be reenabled via the Ethernet PHY software following the reset. This clock can be used to synchronously clock the FPGA logic. If a reset for ADIN1300 is required without CLK25_REF stopping, use a software reset instead. Alternatively, the GP_CLK pin is also available on the FMC connector and can be configured to output several different clocks from the ADIN1300. See the ADIN1300 data sheet for more information.

ON-BOARD EEPROM AND LEDS The EVAL-ADIN1300FMCZ has two FPGA controllable LEDs and one unprogrammed, I2C EEPROM, U7.

U7 can be programmed with voltage settings to allow the FPGA board to provide the correct voltages on the supply rails. The write address of the EEPROM is 0b[10100 [GA1] [GA0] 0] and the read address is 0b[10100 [GA1] [GA0] 1].

ADIN1300 LED PIN There is one LED pin (LED_0) on the ADIN1300. The LED_0 pin can be configured in various operating modes using the MDIO interface dongle (see the ADIN1300 data sheet). By default, the LED_0 pin LED illuminates when a link is established, and flashes when there is activity.

The LED_0 pin is a multifunction pin shared with the PHY_CFG0 pin configuration function. Therefore, it can be necessary for the voltage level on the LED_0 pin to be set at a certain value at power-on and reset to configure the ADIN1300 as required. See the ADIN1300 data sheet for more information on the multilevel strapping being used as part of the hardware configuration.

The LED_0 pin has a two-pole rotary switch, S1, to allow easy configuration for all modes of the PHY_CFG0 pin (as set by S4). Table 4 describes how S1 should be configured for the appropriate S4 PHY_CFG0 pin setting. The LED_0 pin is driven from the AVDD3P3 supply rail, see Figure 2.

Table 4. S1 Switch Positions Jumper S4, PHY_CFG0 S1 Position JP1 Mode 3 and Mode 4 1 JP2 Mode 1 and Mode 2 2

MODE 3 AND MODE 4

MODE 1 AND MODE 2

R192100kΩ

R1100Ω

AVDD3P3

BC817

Q2

1

23

S1LED_0

A

C

DS1

2

3

1R19310Ω

R1910Ω

R43390Ω

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Figure 2. Hardware LED_0 Pin Configuration

MDIO INTERFACE The MDIO interface of the ADIN1300 can be accessed directly through the P5 connector to connect the MDIO interface dongle to the PHY.

The MDIO interface dongle also allows interfacing with the EVAL-ADIN1300FMCZ via the Ethernet PHY software graphical user interface (GUI) running on the PC (see Figure 3).

ADIN1300

25MHzCRYSTAL

POWER

FM

CC

ON

NE

CT

OR

P3

MDIOP5

MAGNETICSRJ45CONNECTOR

EVAL-ADIN1300FMCZ

OPTIONALMDIO INTERFACE

DONGLE

BOOTSTRAP

RESISTORMODE

SELECT

LED0

P7

ADuCM3029

FTDIUART TO USB

USB

EXTERNALCLOCK

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Figure 3. Simplified Overview of EVAL-ADIN1300FMCZ with MDIO Interface

Dongle Connected















MDIO INTERFACE DONGLE The MDIO interface dongle is a separate board included in the EVAL-ADIN1300FMCZ evaluation kit. The MDIO interface dongle has an on-board, ADuCM3029 microcontroller and an FDTI Chip FT232RQ, universal asynchronous receive transmitter (UART) to USB interface. The schematic for this hardware is shown in Figure 41. When using the MDIO interface dongle, connect the USB cable to the MDIO interface dongle first, then connect the MDIO interface dongle to the EVAL-ADIN1300FMCZ with the ADuCM3029 facing up (see Figure 4).

Using the MDIO interface dongle allows interaction with the ADIN1300 device via the Ethernet PHY software GUI running on the PC.

P5

USB

HEADER

MDIOINTERFACE

DONGLE

EVAL-ADIN1300FMCZ

ADuCM302921

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Figure 4. MDIO Interface Dongle Connection to the

USB Cable and EVAL-ADIN1300FMCZ

There are two LEDs on the MDIO interface dongle, DS7 and DS8. When the powered USB cable is initially connected to the MDIO interface dongle, DS8 illuminates. When the Ethernet PHY software GUI establishes communication with the EVAL-ADIN1300FMCZ, DS7 and DS8 flash. The LEDs continue to flash while the GUI is active and the EVAL-ADIN1300FMCZ is selected as the local board within the GUI.

The MDIO interface dongle has two push-button switches on the underside of the board, S5 and S6, as shown in Figure 5. S5 is for download and reboot purposes. S6 is used to reset the on-board ADuCM3029.

BOTTOM

TOP

S5 S6

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USB

ADuCM3029 Figure 5. Overview of MDIO Interface Dongle

CONFIGURATION PINS SETUP The EVAL-ADIN1300FMCZ default configuration and configuration options are detailed in Table 5. The ADIN1300 configuration settings can be changed by manipulating the resistors listed in the right column. See the ADIN1300 data sheet for more details on all available configuration options. Figure 6 shows the location of the resistors on the underside of the printed circuit board (PCB) of the EVAL-ADIN1300FMCZ. The speed configuration is configured via two rotary switches, S3 and S4, and the media defined interface configuration is controlled using the S9 switch. Table 5 lists the different switch configurations available.

Table 5. EVAL-ADIN1300FMCZ Configuration Settings Configuration Option Relevant Pins Resistor and Switch Settings PHY Address = 0b00000 RXD_3/PHYAD_3 R22, R29, R31, R37 = DNI. RXD_2/PHYAD_2 R23, R30, R32, R38 = DNI. RXD_1/PHYAD_1 Using internal pull-down resistors. RXD_0/PHYAD_0 MDIX Mode Configuration GP_CLK/RX_ER/MDIX_MODE S9 Position1, Mode 1, manual MDI. S9 Position 2, Mode 2, manual MDIX. S9 Position 3, Mode 3, prefer MDIX. S9 Position 4, Mode 4, prefer MDI (default).










Configuration Option Relevant Pins Resistor and Switch Settings PHY Configuration LINK_ST/PHY_CFG1 Controlled by S1, S3, and S4 switches to provide the various

configuration options (see the ADIN1300 data sheet). Downspeed, EDPD, Energy Efficient Ethernet (EEE), Software Power-Down, Forced Speed

LED_0/COL/TX_ER/PHY_CFG0 Default configuration: PHY_CFG1/S3 = 1 or 2. Note that the EVAL-ADIN1300FMCZ

boards are shipped in pairs with one board set to 1 and the other set to 2.

PHY_CFG0 and S4 = 4, and LED_0 and S1 = 1. MAC Interface Selection RX_CTL/RX_DV/CRS_DV/MACIF_SEL1 R8, R9 = DNI. RXC/RX_CLK/MACIF_SEL0 R27, R28 = DNI. Using internal pull-down resistors results in MAC interface

default selection being the reduced gigabit media independent interface (RGMII) MAC interface with 2 ns internal delay on the RXC pin and TXC pin.

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Figure 6. Configuration Resistor Placement, Underside of PCB





SOFTWARE OVERVIEW INSTALLING THE ETHERNET PHY SOFTWARE The Ethernet PHY software GUI requires the installation of the Ethernet PHY software and the installation of the USB communications drivers. Both installations must be complete before connecting the EVAL-ADIN1300FMCZ to the USB port of the PC to ensure that the evaluation system is properly recognized when connected to the PC.

First, install the Ethernet PHY software and the associated documentation (the ADIN1300 data sheet). The installation steps are listed in the following section. The default location for the Ethernet PHY software GUI installation is the C:\Analog Devices folder.

When the Ethernet PHY software installation is complete, install the USB communications drivers. The MDIO interface dongle uses the FT232RQ for UART to USB communication. The MDIO interface dongle requires the installation of drivers for the FTDI chip. Locate and install this driver separately. These drivers are available at: www.ftdichip.com/Drivers/CDM/CDM21228_Setup.zip.

Ethernet PHY Software GUI Installation

To install the Ethernet PHY software GUI, take the following steps:

1. Launch the installer file to begin the Ethernet PHY software installation.

2. If a window appears asking for permission to allow the program to make changes to the PC, click Yes.

3. The welcome window appears (see Figure 7). Click Next.

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Figure 7. Welcome Window

4. The Ethernet PHY software launches. An overview of what is being installed and recommendations in terms of hardware power-up appears. Read the overview and click Next (see Figure 8).

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Figure 8. Installation Process Overview

5. A license agreement appears. Read the agreement and click I Agree to allow the installation to proceed (see Figure 9).

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Figure 9. Accepting the License Agreement





6. Select a location to install the Ethernet PHY software and then click Install (see Figure 10).

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Figure 10. Installation Location

7. A window appears stating that the installation is complete. Click Finish to continue (see Figure 11).

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Figure 11. Installation Complete

8. The Ethernet PHY software is automatically installed in the Analog Devices folder on the PC. Access the Ethernet PHY software via Windows® explorer at C:\Analog Devices\ADIN1300 or from the Start menu.

INITIAL SETUP To set up the EVAL-ADIN1300FMCZ and use it with the Ethernet PHY software GUI, take the following steps:

1. Connect a 5 V power supply to the EVAL-ADIN1300FMCZ via the EXT_5V connector or the 5 V barrel connector.

2. Connect the USB cable to the MDIO interface dongle. 3. Connect the USB cable to the PC. When connecting the

EVAL-ADIN1300FMCZ to the PC for the first time, the drivers are automatically installed. Wait until the driver installation is complete before proceeding to the next step.

4. Ensure that the ADuCM3029 microcontroller faces up (see Figure 4) and connect the MDIO interface dongle to the EVAL-ADIN1300FMCZ. The MDIO interface dongle is not keyed.

5. Launch the Ethernet PHY software from the Analog Devices folder in the Start menu.





USING THE EVALUATION SOFTWARE When the Ethernet PHY software is launched, the GUI window shown in Figure 12 appears. Figure 12 shows the GUI features with labels, and Table 6 lists the GUI labels and the corresponding descriptions.

Table 6. GUI Label Descriptions Label Description 1 Select Local section. Shows connected evaluation hardware. The board name shown corresponds to the MDIO interface dongle

that is connected to the EVAL-ADIN1300FMCZ. 2 User buttons. 3 Link Properties tab. Use this tab to change the PHY configuration. 4 Register Access tab. Allows the user read or write device registers. 5 Clock Pin Control tab. Controls which clock is applied to the GP_CLK pin and enables the CLK25_REF pin. 6 Loopback tab. Controls the various loopback modes. 7 Test Modes tab. Provides access to the various test modes on the device. 8 Framechecker tab. Configures and enables the frame generator and frame checker. 9 Cable Diagnostics tab. Provides easy access to the cable diagnostics features on the device. 10 Activity information window. This window provides an overview of the PHY activity, reads, and writes issued to the device. 11 Activity Log section. Section shows read, write, and status activity for the selected PHY. 12 Dropdown menus to load a script file. These two dropdown menus allow the user to load a script file with a sequence of write

commands to load to the device.

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Figure 12. Main GUI Window




GUI DETAILED OVERVIEW BOARD DISPLAY SHOWING CONNECTED EVAL-ADIN1300FMCZ HARDWARE In the Select Local section (see Figure 12), a unique hardware identifier is shown for each MDIO interface dongle connected to the PC. In the example shown in Figure 13, there are two MDIO interface dongles connected to the same PC (the A62UK21O and AL2YSWGN).

The Ethernet PHY software GUI can only communicate with one MDIO interface dongle at a time. To choose which MDIO interface dongle is addressed as the local board in this section, click the appropriate device identifier to select and highlight it. All register controls, displayed link properties, and local board information in other sections of the GUI apply to the selected ADIN1300 device connected to the MDIO interface dongle.

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Figure 13. MDIO Interface Dongle Selection

USER BUTTONS SECTION Use the buttons in this section to control the basic operation of the GUI and the ADIN1300 device.

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Figure 14. Basic User Buttons

Software Power-Down and Power-Up

Click Software Power Down to place the selected device into software power-down mode where the analog and digital circuits are placed into a low power state. Most clocks are gated off and no link is brought up. Click Software Power Down to enable a software power-down. The button color changes to orange and the button label changes to Software Power Up. Click Software Power Up to exit from the software power-down and restart linking. When the software power-down is asserted, the other buttons for the selected device are grey and disabled.

Disable or Enable Linking

Click Disable Linking to disable linking when a link is up. The button label changes from Disable Linking to Enable Linking. Click Enable Linking to enable linking.

Restart Linking

If the software configuration has been changed, click Restart Linking to restart the linking process with the new configuration. If the link has already been established, the link is first brought down and then restarted.

Export Registers

Click Export Registers to perform a data dump to the Activity Log section. The register dump can be saved to text format for offline review. Right click and click Save as to save the data to a log file.

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Figure 15. Activity Log with Export Registers Displayed






Reset

Click Reset to use the dropdown menu to initiate different resets. The reset options include the following:

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Figure 16. Reset Options

Subsystem Software Reset with Pin Configuration: click Reset: SubSys (Pin) to perform a reset of the subsystem with the subsystem requesting a new set of hardware configuration pin settings from the chip during the software reset sequence. The GeSftRst bit and the GESftRstCfgEn bit are set to 1.

Subsystem Software Reset: click Reset: SubSys to perform a reset of the subsystem with the subsystem requesting previously stored hardware configuration pin settings to be reloaded during the software reset sequence. The GeSftRst bit and the GESftRstCfgEn bit are set to 0.

PHY Core Software Reset: click Reset: PHY to perform a reset where the SftRst bit resets the PHY core registers.

LINK PROPERTIES TAB The Link Properties tab provides user access to the main linking configurations within the device. This tab has a slider to access all controls. When a control is selected, the GUI provides a prompt describing the function at the bottom of the linking control box (see Figure 17).

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Figure 17. Link Properties Tab

Speed Mode

For the selected device, advertised speed or forced speed can be chosen. The speed selection prepopulates the remaining user controls for the Link Properties tab with the following:

Advertised: subset of controls available in advertised mode. The controls include the following: Auto-Negotiated Advertised Speeds: shows the

checkbox availability of all autonegotiated advertised speeds available. Select and clear the checkboxes as required. All speed options are available in this section. The default advertised reflects the hardware configuration pins.

EEE Advertisement: use the checkboxes to advertise the EEE as a speed option for 1000BASE-T and 100BASE-TX.

Downspeed: use the checkbox to enable downspeed, which allows the PHY to change down to a lower speed after a number of attempts to bring up a link at the highest advertised speed.

Downspeed Retries: sets the number of times the PHY attempts to bring up a link. The default is four attempts.

MDIX: use dropdown menu to choose between Auto MDIX, FixedMDI, or FixedMDIX.

Energy Detect PowerDown Mode: use the dropdown menu to choose between Disabled, Enabled, or EnabledWithPeriodicPulseTx.

Master/Slave: use the dropdown menu to choose between Master and Slave. The default is Slave.

Forced: subset of controls available in forced mode. The controls include the following: Forced Speeds: use the dropdown menu to choose the

required speed. MDIX: use the dropdown menu to choose between

Auto, FixedMDI, or FixedMDIX. Energy Detect Powerdown Mode: use the dropdown

menu to choose between Disabled, Enabled, or EnabledWithPeriodicPulseTx.

Master/Slave: use the dropdown menu to choose between Master and Slave. The default is Slave.




REGISTER ACCESS TAB The Browse tab within the Register Access tab allows the user to review the bank of registers and edit the register fields or bit fields as required (see Figure 18).

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Figure 18. Register Access Tab Full Register Map

The Manual tab within the Register Access tab allows the user to perform basic reads from and writes to individual ADIN1300 registers (see Figure 19).

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Figure 19. Register Access Tab

Access the direct register read/write function on the right side of the Activity Log section. To access this function, slide the arrow to the left to expose it (see Figure 20).

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Figure 20. Activity Log Section Register Access

CLOCK PIN CONTROL TAB Use this tab to control which clock is applied to the GP_CLK pin, and to enable the CLK25_REF pin (see Figure 21).

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Figure 21. Clock Pin Control Tab

LOOPBACK TAB The various loopback modes are available in this tab (see Figure 22). Consult the ADIN1300 data sheet for a full description of each loopback mode.

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Figure 22. Loopback Tab

TESTMODES TAB Use this tab to initiate the various test mode functions in the device. Select the appropriate test mode and click Execute Test (see Figure 23).

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Figure 23. Test Modes Tab






FRAMECHECKER TAB This tab provides access to the frame generator and frame checker features of the ADIN1300 (see Figure 24).

Control the number of frames generated by the generator, the frame length, and the content of the frame within this tab. Choose to have the frame generator to either run in burst mode or run continuously. To halt the frame generator when the frame generator is running continuously, use the Terminate button.

Use the Loopback button to enable the remote device to loop back the data to the local device. To ensure that the appropriate device is selected, choose which connected board is the local, configure that board to generate frames, then configure the other board in remote loopback.

The frame checker information displayed on the screen accumulates the number of frames sent and shows the number of errors observed (see Figure 25).

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Figure 24. Overview of Frame Generator and Frame Checker

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Figure 25. Frame Generator Status and Frame Checker Result

CABLE DIAGNOSTICS TAB The cable diagnostic feature allows the user to diagnose issues with the link. Various features within the device are available when the link is up, which quantify the quality of the link by measuring features such as the mean squared error (MSE) level and estimated cable length. These measurements are displayed in the main Link Properties tab.

The features in the Cable Diagnostics tab (see Figure 26) are the features available to run when the link is disabled, such as checking for shorts, checking for opens, and identifying the distance to the first fault (see Figure 28). The LinkEn bit must be clear to run these checks.

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Figure 26. Cable Diagnostics Configuration with Link Up

Click the Disable Linking button to set the LinkEn bit to 0 to allow diagnostics to be run (see Figure 27 through Figure 29).

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Figure 27. Cable Diagnostics Configuration when Link is Disabled with Cable

Connected to Remote PHY

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Figure 28. Cable Diagnostics Configuration with Cable Open





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Figure 29. Cable Diagnostics Configuration with Cable Crossed

ACTIVITY WINDOW AND LINKING STATUS This window displays the current status of the selected PHY chip (as determined in the Select Local section), including whether a link is established, the speed of the link, and the speed mode. The local and remote fields show the advertised speeds available in the local PHY device and also what the remote PHY is returning (see Figure 30).

If the user switches between two EVAL-ADIN1300FMCZ boards in the Select Local section, the information shown in these fields will be updated to reflect the information provided from the board defined as local.

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Figure 30. Board Status Information

The GUI displays a color code to show the status of the link depending on how the user has configured the device (see Figure 31).

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19-0

32

Figure 31. GUI Link Status

ACTIVITY LOG INFORMATION SECTION The activity log reports status information and register write issues to the selected EVAL-ADIN1300FMCZ board (see Figure 32). The activity log captures the activity in the GUI corresponding to the activity on the local PHY, which indicates the various reads, writes, and information on whether a link is established. When the frame generator is enabled, this window shows the frame generator activity. The board identification is recorded with each bit field change to clarify which device is being addressed.

2141

9-03

3

Figure 32. Activity Log Showing Device Status

To clear the activity log, right click and then click Clear. To export the contents of the activity log for offline review, right click and then click Save as. The file saved is a text file with a default location in the Analog Devices > ADIN1300 folder.




LOADING A SCRIPT FILE The GUI allows the user to load a sequence of register commands from a file. Within the GUI window, there are two dropdown menus under the Activity Log section where the user can select the script file and which section of the script to run. Click a dropdown menu, choose the script by name, and then click the dropdown menu again to load the selected script. The Activity log displays the register writes issued from the script.

214

19-0

34

Figure 33. Script File Loading Dropdown Menus

The script file is located in the ADIN1300 folder and is named registers_scripts.json (see Figure 34).

214

19-0

35

Figure 34. Script File Location

The register commands can be loaded with either the register name or the register address, as shown in the simple examples in the file. The commands are loaded sequentially. Create the sequence of write commands using a text editor. Ensure that the exact syntax is copied and match the register names with those in the data sheet to prevent errors reported in the activity log. Give the script a unique name. For when the SftPd Down&Up routine is selected, see the following example:

Name: SftPd Down&Up,

RegisterAccesses: [

MemoryMap : GEPhy,

RegisterName: SftPd,

Value: 1

,

MemoryMap : GEPhy,

RegisterName: SftPd,

Value: 0

,

]

,




TROUBLESHOOTING SOFTWARE INSTALLATION TIPS Ethernet PHY software installation tips follow:

Always allow the software installation to be completed, and keep in mind that the Ethernet PHY software is a two-part installation including the ADI package installer (GUI and documentation) and the FTDI drivers which can be found at www.ftdichip.com/Drivers/CDM/CDM21228_Setup.zip. The installation may require a restart of the PC.

When the MDIO interface dongle is first plugged in via the USB cable, allow the new found hardware wizard to run completely. This step is required prior to starting the Ethernet PHY software.

If the EVAL-ADIN1300FMCZ does not appear in the GUI window, ensure that the following steps have been competed:

Power is applied to the EVAL-ADIN1300FMCZ. The powered USB connector is connected to the MDIO

interface dongle. Both the EVAL-ADIN1300FMCZ and the MDIO

interface dongle are connected together. The Ethernet cable is connected. The Ethernet PHY software is launched.

SOFTWARE TIPS If the Ethernet PHY software does not read any data back, check for any messages in the Activity Log section. There is one known communication bug in the connection of the MDIO interface dongle and EVAL-ADIN1300FMCZ, as discussed in the following section.

MDIO Interface Dongle Communications, Known Issue

A known behavior when using the MDIO interface dongle with the EVAL-ADIN1300FMCZ is related to the sequence of how the boards are powered and connected together. If the GUI is open, and the user connects the MDIO interface dongle to the EVAL-ADIN1300FMCZ before connecting the USB power to the MDIO interface dongle, the GUI may not properly establish communications with the MDIO interface dongle.

The GUI polls for the MDIO interface dongle regularly, and if an error in the MDIO interface dongle communications is found, it is flagged in the Activity Log section and highlighted in red font, as shown in Figure 35. The message also includes a prompt explaining how to resolve the issue.

In the example shown in Figure 35, the user is advised to reset the MDIO interface dongle through Button S6. There are two buttons on the underside of the MDIO interface dongle. In this case, the user identifies S6 and reset. This action restarts the MDIO interface dongle. If the S6 restart does not resolve communications, exit the GUI and relaunch the Ethernet PHY software.

21

419-

036

Figure 35. Example Activity Log when MDIO Interface Dongle is Not

Responding

HARDWARE TIPS Ensure that power is applied to the MDIO interface dongle and EVAL-ADIN1300FMCZ as previously discussed. Measure the voltage at various points on the EVAL-ADIN1300FMCZ using the DVDD, VDD0P9, 5V, AVDD3P3, and VDDIO test points. Crosscheck the voltages against the information in Table 1.

No Link Established

If no link is established, take the following steps to assist debug:

Ensure that the Ethernet cable is connected properly to the RJ45 connector and between the EVAL-ADIN1300FMCZ boards or PHY pairs.

When using two EVAL-ADIN1300FMCZ boards, ensure that both boards are powered.

Ensure that the hardware configuration is appropriate for the required linking arrangement.

LED Not Illuminated, but Link Established Reported in GUI

By default, LED_0 illuminates when a link is established, and flashes when there is activity. The EVAL-ADIN1300FMCZ is configured for Mode 3 and Mode 4 by default, with S1 in Position 1. If PHY_CFG0 is to be used in Mode 1 or Model 2, change the position of S1 to Position 2, as described in Table 4.




LAYOUT GUIDELINES BOARD STACKUP The EVAL-ADIN1300FMCZ consists of a 4-layer PCB: the top layer, Layer 2, Layer 3, and the bottom layer. All layers have a copper pour, with an exception around sensitive traces for the MAC and MDI interfaces.

GROUND PLANES The top and bottom layers of the EVAL-ADIN1300FMCZ mainly carry signal and routing signals from the ADIN1300. The two inner layers are used for ground planes. Layer 2 is a full ground plane. Layer 3 contains primarily of ground with area dedicated to the DVDD and VDDIO power planes. Although the ADIN1300 is a mixed signal device, it only has one type of ground return, GND.

ISOLATION GUIDELINES Transformer Layout

No metal layers can be directly underneath the transformer to minimize any noise coupling across the transformer.

RJ45 Layout

For optimal electromagnetic computability (EMC) performance, use a metal shielded RJ45 connector with the shield connected to chassis ground. There must be an isolation gap between the chassis ground and the IC GND with consistent isolation across all layers.

POWER SUPPLY DECOUPLING From a PCB layout point of view, it is important to locate the decoupling capacitors as close as possible to the power supply and GND pins to minimize the inductance.

MAC INTERFACE When routing the MAC interface traces, ensure that the lengths of the pairs are matched. Avoid crossover of the signals where possible. Stubs should be avoided on all signal traces. It is recommended to route traces on the same layer.

MANAGEMENT INTERFACE MDI interface

Traces running from the MDI_[x]_P/N pins of the ADIN1300 to the magnetics must be on the same side of the EVAL-ADIN1300FMCZ (no vias), kept as short as possible (less than 1 inch in length), and individual trace impedance of these tracks must be kept below 50 Ω with a differential impedance of 100 Ω for each pair. The same recommendations apply for traces running from the magnetics to the RJ45 connector. Impedance must be kept constant throughout. Any discontinuities can impact signal integrity.

Each pair must be routed together with trace widths the same throughout. Trace lengths must be kept equal where possible and any right angles on these traces must be avoided (use curves or 45° angles in the traces). Stubs must be avoided on all signal traces. It is recommended to route traces on the same layer.

PLACEMENT OF THE TVS DIODE It is recommended to place the TVS diode close to the ADIN1300 device to ensure minimal track inductance between the external protection and internal protection within the device.

THERMAL CONSIDERATIONS The ADIN1300 is packaged in an LFCSP package. This package is designed with an exposed paddle which must be soldered to the PCB for mechanical and thermal reasons. The exposed paddle acts to conduct heat away from the package and into the PCB. By incorporating an array of thermal vias in the PCB thermal paddle, heat is dissipated more effectively into the inner metal layers of the PCB. When designing the PCB layout for optimum thermal performance, use a 4 mm × 4 mm array of vias under the paddle.

This LFCSP device includes two exposed power bars adjacent to the exposed pad at the top and bottom, highlighted in red in Figure 36. These bars are connected to internal power rails and the area around them is a keep out zone. Keep these areas clear of traces or vias.

1

0.50BSC

BOTTOM VIEW

40

1120

21

30

31

10

0.025 REF

0.15REF

0.300.250.20

0.240.140.04

0.4750.3750.275

0.7850.6850.585

2.872.772.67

0.500.400.30

2.902.80 SQ2.70

EXPOSEDPAD

PIN 1

21

419-

03

7

Figure 36. LFCSP Simplified Package Drawing with Keep Out Area for Power

Bars Highlighted (Underside)









EVALUATION BOARD SCHEMATICS AND ARTWORK

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21419-038

Figure 37. PHY Schematic




PAIR D

PAIR B

100Ω DIFFERENTIAL;5 MIL TRACES, 10 MIL SPACING ( 5 / 10 / 5 );MATCH AND MINIMIZE TRACE LENGTH

PAIR A

100Ω DIFFERENTIAL;5 MIL TRACES, 10 MIL SPACING ( 5 / 10 / 5 );MATCH AND MINIMIZE TRACE LENGTH

PAIR C

5406299-1

DNI

20054

0.1µ

F

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H5007NL

H5007NL

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75Ω

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75Ω

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CON-MDI_3_P

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214

19-0

39

Figure 38. Magnetics




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2.5

V =

0.5

(1

+ 2

00kΩ

/50kΩ

) (D

EF

AU

LT)

AD

P22

3: P

LAC

E V

IN A

ND

VO

UT

CA

PA

CIT

OR

S A

S C

LOS

E A

S P

OS

SIB

LE T

O T

HE

PIN

S

AD

P22

3AC

PZ

AD

P22

3AC

PZ

4.7µ

F

DN

I

4.7µ

F

4.7µ

F

50kΩ

DN

I 0Ω

40kΩ

4.7µ

FD

NI

180

3277

1803

277

1kΩ

AD

P71

05A

CP

Z-5

.0

100kΩ

4.7µ

F

0.01

µF

DN

I

4.7µ

F4.

7µF

DN

I DN

ID

NI

DN

I

DN

I

1kΩ

DN

ID

NI

10nH

DN

I

0Ω

DN

ID

NI 0Ω

DN

I

280kΩ

50kΩ

200kΩ

50kΩ

10nH

DN

I

0Ω

DN

ID

NI

DN

I0.

01µ

F0.

01µ

F

4.7µ

F4.

7µF

10nH 10

nH

280kΩ

50kΩ

4.7µ

F

GND4

C50

C40

P4

C51

R62

C49

R64

L4

DV

DD

_P

R68

DV

DD

_N

E1

C46

U5

C48

U4

R52

VD

D0P

9_P

AV

DD

3P3_

N

R67

AV

DD

3P3_

P

L3

VD

DIO

_N

VD

D0P

9_N

VD

DIO

_P

R65

L1

R11

R12

R16

R58

L11

R57

R54

C44

C47

E2

SU

PP

LY

C43

C31

EX

T_5

V

JP3

C14

JP1

EX

T_1

2V

5V

R10

U2

DN

I

C13

C99

C45

C33

DV

DD

EX

T_5

V

SU

PP

LY

EX

T_1

2V

12V

_FP

GA

VD

D0P

9

AV

DD

3P3

VD

DIO

SU

PP

LY

1

3 21B1A

1

1

21

576

3D

AP

21 48

576

3P

AD

21 48

1

1

1

11

1

21

1

21

32

1

1 2

21

1

18

42 7

36

PA

D

5

AD

J1A

DJ2

PA

D

VO

UT

1V

INV

OU

T2

GN

D

EN

2E

N1

PA

D

VIN

PG

EN

/UV

LO

SS

GN

DSE

NS

E/A

DJ

VO

UT

AD

J1A

DJ2

PA

D

VO

UT

1V

INV

OU

T2

GN

D

EN

2E

N1

BA

21419-040

Figure 39. Power Supplies




R7

2, R

74,

RE

SIS

TO

RS

TO

BE

CO

NN

EC

TE

D

CL

OS

E T

O C

ON

NE

CT

OR

TO

MIN

IMIZ

E

ST

UB

WH

EN

MD

IO IS

US

ED

WIT

H T

HE

FM

C C

ON

NE

CT

OR

3. K

EE

P R

OU

TIN

G L

EN

GT

H T

O M

INIM

UM

2. A

LL T

RA

CK

S N

EE

D T

O B

E L

EN

GT

H

RX

SIG

NA

LS

, 0Ω

FO

R T

X S

IGN

AL

S

MA

TC

HE

D A

ND

SH

OU

LD

BE

DR

AW

N

1. 1

0Ω

SE

RIE

S T

ER

MIN

AT

ION

FO

R

RX

AN

D G

RO

UP

OF

TX

LIN

ES

ST

ICK

GN

D V

IA A

RO

UN

D G

RO

UP

OF

WIT

H G

RO

UN

D A

BO

VE

AN

D B

ELO

W

PL

AC

E S

IGN

AL

S O

N A

N IN

NE

R L

AY

ER

AS

50Ω

TR

AN

SM

ISS

ION

LIN

ES

SS

W-1

04

-02

-T-D

-RA DN

I

DN

I

PT

S8

30 G

M1

40

SM

TR

LF

S

10Ω

PT

S8

30

GM

140

SM

TR

LF

S

0.1

µF

0.1

µF

1kΩ D

NI

10Ω

0Ω

0Ω

0Ω

0Ω

10Ω

DN

I

DN

I DN

I

0Ω

0Ω

0Ω

0Ω 0Ω

0Ω

0Ω 1

0Ω

0.1

µF

AS

P-1

3460

4-01

4.7

µF

AT

24C

02D

-SS

HM

-T

0.1

µF

0.1

µF DN

I

0.1

µF DN

I

0.1

µF DN

I

DN

I

10

kΩ

0.1

µF

1kΩ

0.1

µF

AS

P-1

3460

4-01

0.1 µ

F

10

kΩ

DN

I

0.0

1µF

AS

P-1

3460

4-01

DN

I

AS

P-1

3460

4-01

0.1

µF

DN

I0Ω

0Ω

DN

I

10Ω

10Ω

0Ω

0.1

µF

1kΩ

M2

0-9

990

345

470Ω

0Ω 0Ω

0Ω

0Ω

0.0

1µF

10n

H

DNI

DNI

SS

W-1

04-0

2-T

-D-R

A

0.1

µF

0Ω 0Ω

0Ω 10Ω

470Ω

R15

0

C9

2

C5

5C

18

R7

C3

C4

C5

C6

P3

P3

P3

P3

R9

7R

89

R86R

63

R6

GND5

C5

2C

53

R2

13

R2

11R21

0

R1

44

R1

13

S8

S7

R14

3

R14

2

C8

9

C9

0

L5

R8

4

R9

2

R8

8R

90

R49

R8

0

R8

7

R9

5

R1

01

R8

1R

85

R99

R9

3R

50

R46

DS

5

R47

DS

4

MD

IOM

DC

C5

4

C5

9

R6

9R

70

JP2

R7

5

U7

C5

6

C58

C57

C61

C62

C60

R7

4

R7

2P

5

P5

MD

IO_

FM

C

12V

_F

PG

A

RE

SE

T

LE

D_

0

INT

_N/C

RS

TX

C/T

X_C

LK

RX

C/R

X_

CL

K EX

T_

CLK

_F

MC

EX

T_C

LK

RX

C/R

X_C

LKR

X_C

TL

/RX

_DV

TX

_C

TL

/TX

_E

N

GP

CL

K

RX

D_

3

SC

L

RX

CT

L/R

XD

V

RX

D_

0

LED

_B

TX

D_

0

VIO

SW

_6

GP

_C

LK

/RX

_ER

TX

ER

TX

D_

3

TX

D_

1

SW

_5

TX

D1

TX

D3R

XC

TX

_CT

L/T

X_E

N

LE

D_0

LIN

K_S

T

SD

A

SC

L

GA

1

3P3

_F

PG

AG

A1

LIN

KS

T

GA

0

GA

0

SD

A

3P

3 A

UX

VIO

TX

D_

0

RX

D_

2

RX

D_0

TX

C/T

X_

CLK

LE

D_

0

TX

D_

3

LED_B

LED_A

SW

_3

RE

SE

T

GP

_CLK

/RX

_E

R

LE

D_

0

INT

_N

/CR

S

CO

N-C

OL

RX

_CT

L/R

X_D

V

LED

_F

MC

INT

_N

TX

C

RX

D1

RX

D_

1

SW

_1

TX

C/T

X_C

LK

VIO

TX

D0

VIO

CO

N-C

RS

RX

ER

IO_

SC

L

RX

D0

TX

D_

1

TX

D_

2

RX

D_1

RX

D_2

3P

3 A

UX

3P

3 A

UX

3P

3_F

PG

A

VD

DIO

MD

C

MD

IO

MD

C_

FM

C

RX

D_3

RX

D3

TX

CL

K

TX

D2

RX

D2

TX

CT

L

SW

_6

SW

_5

IO_

SD

A

SW

_4

LED

_A

MD

C_

FM

C

MD

IO_F

MC

SW

_2

TX

D_

2

H1

H4

0

H2

H3

7

H3

8

H3

4

H3

5

H3

1

H3

2

H2

8

H2

9

H2

5

H2

6

H2

2

H2

3

H1

9

H2

0

H1

6

H1

7

H1

3

H1

4

H1

0

H1

1

H7

H8

H3

9

H3

6

H3

3

H3

0

H2

7

H2

4

H2

1

H1

8

H1

5

H1

2

H9

H6

H3

H4

H5

D3

4

D3

3

D3

1

D3

0

D2

9

D1

D2

6

D2

7

D2

3

D2

4

D2

0

D2

1

D1

7

D1

8

D1

4

D1

5

D1

1

D1

2

D8

D9

D3

9

D3

7

D2

8

D2

5

D2

2

D1

9

D1

6

D1

3

D1

0

D7

D6

D3

D2

D4

D5

D3

5

D3

2

D4

0

D3

8

D3

6

G3

9

G3

6

G3

7

G3

3

G3

4

G3

0

G3

1

G2

7

G2

8

G2

4

G2

5

G2

1

G2

2

G1

8

G1

9

G1

5

G1

6

G1

2

G1

3

G9

G1

0

G6

G7

G4

0

G3

8

G3

5

G3

2

G2

9

G2

6

G2

3

G2

0

G1

7

G1

4

G1

1

G8

G5

G4

G1

G2

G3

C31

C30

C26

C27

C22

C23

C18

C19

C14

C15

C10

C11

C40

C38

C36

C33

C32

C29

C28

C25

C24

C21

C20

C17

C16

C13

C12C9

C8

C5

C4

C1

C34C6

C7

C2

C3

C37

C35

C39

1

43

21

43

21

A

A

C

C

1

1

32

1

78 56

4321

7531

8642

BA

VC

C

WP

SC

L

SD

AG

ND

A2

A1

A0

VA

DJ

GN

D

LA3

2_N

LA3

2_P

GN

D

LA3

0_N

LA3

0_P

GN

D

LA2

8_N

LA2

8_P

GN

D

LA2

4_N

LA2

4_P

GN

D

LA2

1_N

LA2

1_P

GN

D

LA1

9_N

LA1

9_P

GN

D

LA1

5_N

LA1

5_P

GN

D

LA1

1_N

LA1

1_P

GN

D

LA0

7_N

LA0

7_P

GN

D

LA0

4_N

LA0

4_P

GN

D

LA0

2_N

LA0

2_P

GN

D

CL

K0_

M2

C_

N

CL

K0_

M2

C_

P

GN

D

PR

SN

T_

M2

C_

L

VR

EF

_A_

M2

C

3P

3V

GN

D

3P

3V

GN

D

3P

3V

GA

1

TR

ST

_L

TM

S

3P

3VA

UX

TD

O

TD

I

TC

K

GN

D

LA

26_

N

LA

26_

P

GN

D

LA

23_

N

LA

23_

P

GN

D

LA

17_

N_

CC

LA

17_

P_C

C

GN

D

LA

13_

N

LA

13_

P

GN

D

LA

09_

N

LA

09_

P

GN

D

LA

05_

N

LA

05_

P

GN

D

LA

01_

N_

CC

LA

01_

P_C

C

GN

D

GN

D

GB

TC

LK

0_M

2C_N

GB

TC

LK

0_M

2C_P

GN

D

GN

D

PG

_C

2M

GN

D

VA

DJ

GN

D

LA

33_

N

LA

33_

P

GN

D

LA

31_

N

LA

31_

P

GN

D

LA

29_

N

LA

29_

P

GN

D

LA

25_

N

LA

25_

P

GN

D

LA

22_

N

LA

22_

P

GN

D

LA

20_

N

LA

20_

P

GN

D

LA

16_

N

LA

16_

P

GN

D

LA

12_

N

LA

12_

P

GN

D

LA

08_

N

LA

08_

P

GN

D

LA

03_

N

LA

03_

P

GN

D

LA

00_

N_C

C

LA

00_

P_C

C

GN

D

GN

D

CL

K1_

M2

C_

N

CL

K1_

M2

C_

P

GN

D

GN

D

3P3

V

GN

D

12P

0V

GN

D

12P

0V

GA

0

GN

D

GN

D

SD

A

SC

L

GN

D

GN

D

LA2

7_N

LA2

7_P

GN

D

GN

D

LA1

8_N

_C

C

LA1

8_P

_C

C

GN

D

GN

D

LA1

4_N

LA1

4_P

GN

D

GN

D

LA1

0_N

LA1

0_P

GN

D

GN

D

LA0

6_N

LA0

6_P

GN

D

GN

D

DP

0_M

2C

_N

DP

0_M

2C

_P

GN

D

GN

D

DP

0_C

2M

_N

DP

0_C

2M

_P

GN

D

ININ

OU

T

OU

T

OU

T

OU

T

OU

T

OU

T

OU

T

ININININ

21419-041

Figure 40. FMC Connector




RE

D

GR

EE

N

ALS

O, P

HY

RE

SE

T P

IN IS

5V

TO

LE

RA

NT

OP

TIO

N T

O H

OL

D IN

RE

SE

TM

DIO

CO

NN

EC

TO

R I

F A

DU

CM

MD

IOC

ON

TR

OL

ON

SE

PA

RA

TE

BO

AR

D

EN

AB

LE M

DC

IN

ON

E D

IRE

CT

ION

(U

C T

O P

HY

)

RE

SE

T IS

ON

LY

EV

ER

DR

IVE

N L

OW

NO

N-I

SO

LAT

ED

US

B C

ON

NE

CT

ION

"0 =

DO

WN

LOA

D M

OD

E"

"RE

SE

T"

CONNECTIONS TO MAIN PCB

"1 =

BO

OT

FR

OM

INT

. FLA

SH

"

AD

UC

M3

029

SW

D

QF

N6

4_9

X9_

PA

D4

_5X

4_5

APHHS1005ZGC

100

kΩ

0.1

µF

0.1

µF

UX

60S

C-M

B-5

S8

1kΩ

DN

I

10µ

F10

µF

0.1

µF

0.4

7µ

F

0.4

7µF

20p

F

TS

W-1

04

-08

-T-D

-RA

AD

uCM

3029

BC

PZ

0Ω

120

nH

10

0Ω

10

0Ω

10

0Ω

10

0kΩ

0.1

µF

26M

EG

HZ

0.1

µF

0.1

µF

PT

S8

30 G

M1

40

SM

TR

LF

S

0.0

1µ

F

0.1

µF

PT

S8

30 G

M1

40

SM

TR

LF

S1

00kΩ

100

kΩ1kΩ

DN

I

1MΩ 4.7

kΩ

120

nH

4.7

µF

120

nH

0.1

µF20p

F

8pF

8pF

33Ω

10

0kΩ

0.1

µF

33Ω

100

kΩ

32.7

68

KH

Z

SN

74

LVC

1G

08D

CK

R

33Ω

691

57-1

02

HL

F

FT

232R

Q

0.1

µF

DN

ID

NI

0.1

µF

2.2

µF

120

nH

2.2

µF

74A

VC

1T4

5GW

,125

74A

VC

1T

45G

W,1

25

74A

VC

1T

45G

W,1

25

82kΩ

0Ω

0Ω

0ΩA

DP

124

AR

HZ

-3.3

-R7

0.1

µF

0.1

µF

APHHS1005SURCK

R11

1

R1

12

U3

R1

48

R14

9

U14

U13

P1

2

P7

P9

P1

1P

10

C87

C8

5

R13

0

C80

U11

R12

9

C7

8C

76

R12

8

R1

27U

10

C66

C6

5

L7

L6 R

121

C6

4

P8

C8

8

U12

C8

6

L9

R1

36

R13

7

DS8

R13

5

C82

C8

3

C8

4

C81

C7

9

R1

33 R

134

R1

31

R13

2

C7

7

Y3

C7

5

Y2

C71

L8

C7

4

C7

2

C7

3

C7

0

C6

9

C67

C68

R12

3

R1

22

S5 S6

TP

1

TP

3T

P2

TP

4T

P5

U9

R1

26

R12

5 DS7

R1

24

+3.

3V

V_S

EN

SE

+3.3

V

+3.3

V

AD

UC

M_

MO

SI

US

B_U

AR

T_

DM

AD

UC

M_

MO

SI

AD

UC

M_

MD

CA

DU

CM

_M

DIO A

DU

CM

_M

DIO

_E

N

AD

UC

M_

RE

SE

T

AD

UC

M_

RE

SE

T

LV

L_S

HIF

T_

MD

CL

VL

_SH

IFT

_M

DIO

+3.

3V

+3.

3V

AD

UC

M_

TX

D

+3

.3V

+3.

3V

US

B_U

AR

T_D

P

PW

RG

D

+3.3

V

US

B_5

V

+3.3

V

+3

.3V

+3.3

V

+3.3

V

+3.

3V

US

B_5

V

AD

UC

M_

RX

D

+3

.3V

V_

SE

NS

E

V_S

EN

SE

V_S

EN

SE

+3

.3V

AD

UC

M_M

DIO

_EN

AD

UC

M_

MD

IOLV

L_

SH

IFT

_M

DIO

AD

UC

M_M

DC

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21419-042

Figure 41. MDIO Interface Dongle




2141

9-0

43

Figure 42. Schematic Silkscreen, Top

2141

9-0

44

Figure 43. Schematic Silkscreen, Bottom




214

19-0

45

Figure 44. Top Layer

21

419

-04

6

Figure 45. Layer 2, Ground Layer




21

419-

04

7

Figure 46. Layer 3, Power and Ground Layer

21

419-

04

8

Figure 47. Bottom Layer




ORDERING INFORMATION BILL OF MATERIALS

Table 7. Qty Reference Designator Description Manufacturer Part Number 16 C1, C10, C11, C15, C19, C21,

C23, C26, C54, C55, C57 to C62 Ceramic capacitors, 0.1 μF, 16 V, 10%, 0402, X7R

American Technical Ceramics

530L104KT16T

16 C2, C9, C12, C16, C20, C22, C25, C28, C40, C50, C52, C53, C63, C87, C89, C90

Ceramic capacitors, 0.01 μF, 25 V, 10%, 0402, X7R

TDK C1005X7R1E103K050EB

5 C13, C14, C30, C31, C36, C38, C56


KEMET C1206C475K3RACTU

4 C24, C29, C32, C35 Ceramic capacitors, 0.1 μF, 50 V, 10%, 0402, X7R

TDK C1005X7R1H104K050BE

3 C27, C34, C37 Ceramic capacitors, 1 μF, 100 V, 10%, 0805, X7S

TDK C2012X7S2A105K

1 C39 Ceramic capacitor, 0.001 μF, 3000 V, 10%, 1812, X7R

KEMET C1812C102KHRACTU

2 C41, C42 Ceramic capacitors, 12 pF, 50 V, 1%, 0402, NP0(C0G)

Murata GJM1555C1H120FB01D

6 C44, C46 to C49, C51 Ceramic capacitors, 4.7 μF, 10 V, 10%, 0603, X6S

Murata GRM185C81A475KE11D

13 C64, C66 to C69, C73, C74, C76, C78 to C81, C85


TDK CGA2B3X7R1H104K050BB

1 C65 Ceramic capacitor, 4.7 μF, 50 V, 10%, 0805, X7R

Murata GRM21BZ71H475KE15L

2 C70, C72 Ceramic capacitors, 10 μF, 25 V, 10%, 0805, X5R

TDK C2012X5R1E106K085AC

2 C71, C77 Ceramic capacitors, 8 pF, 16 V, 0.5 pF, 0402, C0G

AVX Corporation 0402YA8R0DAT2A

2 C75, C82 Ceramic capacitors, 20 pF, 16 V, 5%, 0402, C0G

AVX Corporation 0402YA200JAT2A

2 C83, C84 Ceramic capacitors, 0.47 μF, 35 V, 10%, 0603, X7R

Taiyo Yuden GMK107B7474KAHT

2 C86, C88 Ceramic capacitors,2.2 μF, 50 V, 10%, 0805, X7R

Taiyo Yuden UMK212BB7225KG-T

2 D3, D4 6 V, SOT23_6, TVS diode arrays, low capacitor ESD protection

Littelfuse, Inc. SP0504SHTG

3 DS1, DS4, DS5 1.7 V, 0805, LEDs, red, clear, 660 nm Lumex Inc. SML-LX0805SRC-TR 1 DS7 2.1 V, 0402, LED, orange, 610 nm Kingbright

Electronic APHHS1005SECK

1 DS8 0402, LED, red Kingbright Electronic

APHHS1005SURCK

2 E1, E2 1 kΩ at 100MHz, L0805, ferrite bead, 0805 Taiyo Yuden BK2125HS102-T 1 EXT_5V PCB connector header,

CNHDRRA1X2H285, 3.81 mm Phoenix Contact 1803277

2 JP2, JP3 PCB connectors, 3-position, male, header, unshrouded, single-row, 2.54 mm pitch

Harwin M20-9990345

5 L1, L3, L4, L5, L11 10 nH, 2%, 0603, inductors, high frequency wirewound

Murata Manufacturing

LQW18AN10NG10D

4 L6 to L9 120 nH, 25%, 0805, inductors Murata Manufacturing

BLM21BB750SN1B

1 P1 PCB connector, modular jack assembly, single-port, shielded, RJ45

TE Connectivity 5406299-1




Qty Reference Designator Description Manufacturer Part Number 1 P12 PCB connector, straight, male, 2-pin

header Amphenol FCI 69157-102HLF

1 P3 PCB connector, single-ended array, male, 160-position, FMC

Samtec ASP-134604-01

1 P4 PCB connector, CNCUI-PJ-002A_A, power jack

CUI PJ-002AH-SMT-TR

1 P5 PCB connector, 8-position, socket strip, double-row, right angled, 2.54 mm pitch

Samtec SSW-104-02-T-D-RA

1 P7 PCB connector, right angled, male header Samtec TSW-104-08-T-D-RA 1 P8 PCB connector, female, mini USB 2.0 Hirose Electric UX60SC-MB-5S8 1 Q2 45 V, SOT23-M3, NPN transistor NXP

Semiconductors BC817

1 R1 Resistor, 3.01 kΩ, 1%, R0402 Panasonic ERJ-2RKF3011X 1 R10 Resistor, 100 kΩ, 1%, 0603, Bourns CR0603-FX-1003ELF 6 R39, R103, 115, R117, R207,

R209 Resistors, 56 kΩ, 1%, 0603 Multicomp (SPC) MC 0.063W 0603 1% 56K.

16 R24, R33, R34, R40, R51, R69, R70, R71, R73, R104, R114, R116, R118, R197, R206, R208

Resistors, 10 kΩ, 1%, 0603 Multicomp (SPC) MC0063W0603110K

8 R75 to R79, R106, R142, R143 Resistors, 1 kΩ, 1%, 0603 Multicomp (SPC) MC0063W060311K 2 R107, R145 Resistors, 1.5 kΩ, 50 V, 1%, 0603, Multicomp (SPC) MC 0.063W 0603 1% 1K5 2 R11, R62 Resistors, 280 kΩ, 0.1%, 0603 Panasonic ERA-3AEB2803V 27 R6, R15, R26, R53, R58, R63,

R65, R67, R68, R80, R84, R87, R88, R90, R92, R112, R119, R148, R150, R191, R194, R195, R196, R210 to R213

Resistors, 0 Ω, 50 V, 1%, 0402 Multicomp (SPC) MC00625W040210R

4 R72, R74, R113, R144 Resistors, 0 Ω, 1%, 0603 Multicomp (SPC) MC0603WG00000T5E-TC 4 R12, R52, R54, R64 Resistors, 50 kΩ, 0.1%, 0603 Vishay PNM0603E5002BST5 1 R121 Resistor, 1 MΩ, 1%, 0201 Panasonic ERJ-1GNF1004C 1 R122 Resistor, 4.7 kΩ, 25 V, 1%, 0201 Multicomp (SPC) MC0201L6F4701SE 6 R123, R124, R130, R131, R135,

R136 Resistors, 100 kΩ, 1%, 0201 Panasonic ERJ-1GNF1003C

2 R125, R137 Resistors, 1 kΩ, 1%, 0201 Panasonic ERJ-1GNF1001C 3 R126, R128, R129 Resistors, 33 Ω, 1%, 0201 Panasonic ERJ-1GNF33R0C 1 R127 Resistor, 0 Ω, 5%, 0201 Bourns CR0201-J/-000GLF 3 R132 to R134 Resistors, 100 Ω, 1%, 0201 Panasonic ERJ-1GNF1000C 1 R149 Resistor, 82 kΩ, 1%, 0603, Multicomp (SPC) MC 0.063W 0603 1% 82K. 1 R16 Resistor, 200 kΩ, 1%, 0603 Panasonic ERJ-3EKF2003V 1 R192 Resistor, 100 kΩ, 1%, 0603 Yageo RC0603JR-07100KL 1 R193 Resistor, 10 kΩ, 1%, 0402 Panasonic ERJ-2RKF1002X 4 R2 to R5 Resistors, 75 Ω, 1%, 0603 Panasonic ERJ-3EKF75R0V 1 R43 Resistor, 390 Ω, 5%, 0402 Panasonic ERJ-2GEJ391X 2 R46, R47 Resistors, 470 Ω, 1%, 0402 Yageo RC0402FR-07470RL 1 R48 Resistor, 0 Ω, 500 V, 2512 Vishay CRCW25120000Z0EG 6 R50, R81, R86, R89, R93, R99 Resistors, 10 Ω, 1%, 0402 Multicomp (SPC) MC00625W0402110R 1 R57 Resistor, 40 K, 0.1%, 0603 Vishay PAT0603E4002BST1 1 S1 Switch, 4-position, surface mount,

SM_DIP8-2 CTS 219-4MST

5 S2, S5 to S8 Switches, tactile, microminiature top actuated, single-pole, single throw, normally open (SPST-NO)

C&K PTS830 GM140 SMTR LFS




Qty Reference Designator Description Manufacturer Part Number 3 S3, S4, S9 16 V, single-pole, 4 throw, rotary

switches, SP4T NIDEC COPAL Electronics

CS-4-14NA

1 T1 Transformer 1000BASE-T magnetic modules

Pulse Electronics H5007NL

1 U1 IC robust, low latency gigabit Ethernet PHY

Analog Devices ADIN1300

1 U10 IC USB serial UART FTDI CHIP FT232RQ 1 U11 IC-TTL single-positive and gate, SC70-5 Texas Instruments SN74LVC1G08DCKR 1 U12 3.3 V complementary metal-oxide

semiconductor (CMOS) linear regulator with low quiescent current

Analog Devices ADP124ARHZ-3.3-R7

3 U3, U13, U14 IC-TTL dual supply transceivers, 3-state NXP Semiconductors

74AVC1T45GW,125

2 U4, U5 Dual 300mA adjustable output, low noise, high power supply rejection ratio (PSRR) voltage regulators

Analog Devices ADP223ACPZ-R7

1 U7 I2C compatible serial EEPROM 2-kBit ATMEL AT24C02D-SSHM-T 1 U8 CMOS I2C serial EEPROM, 32-kBit. ONSEMI CAT24C32WI-GT3 1 U9 Ultralow power ARM® Cortex®-M3

Micro-controller with integrated power management and 256 kB of embedded flash memory

Analog Devices ADUCM3029BCPZ

1 Y1 25 MHz, 10 ppm, crystal, 10 pF load capacitor

Seiko Epson FA-128_25.000000MHZ_10.0_+10-10

1 Y2 32.768 kHz, 20 ppm, crystal, 6 pF load capacitor

Abracon Corp. ABS07-120-32.768KHZ-T

1 Y3 26 MHz, 30 ppm, crystal, 10 pF load capacitor

ECS, INC. ECS-260-10-36Q-ES-TR

Table 8. Not Populated Qty Reference Designator Description Supplier Part Number 26 5V, AVDD3P3_N, AVDD3P3_P,

CLK25, DVDD_N, DVDD_P, GND1, GND2, GND3, GND4, GND5, GPCLK, INT_N, LED_0, LINK_ST, MDC, MDIO, P9, P10, P11, SUPPLY, VDD0P9_N, VDD0P9_P, VDDIO_N, VDDIO_P, XTAL_I

Test point, DNI Keystone Electronics 1405-2

3 C33, C45, C99 Ceramic capacitors, 0.01 μF, 25 V, 10%, 0402, X7R

TDK C1005X7R1E103K050EB

1 EXT_12V PCB connector header, 3.81 mm Phoenix Contact 1803277 1 J1 PCB connector, straight SMA TE Connectivity LTD 5-1814832-1 7 R49, R95, R97, R101, R110,

R111, R120 Resistors, 0 Ω, 50 V, 1%, 0402 Multicomp (SPC) MC00625W040210R

4 R138 to R141 Resistors, 0 Ω, R0805 Multicomp (SPC) MC 0.1W 0805 0R 1 R19 Resistor, 1 MΩ, 1%, 0402 Panasonic ERJ-2RKF1004X 12 R8, R9, R22, R23, R27 to R32,

R37, R38 Resistors, 10 kΩ, 1%, 0603 Multicomp (SPC) MC0063W0603110K

1 R85 Resistor 10 Ω, 1%, R0402 Multicomp (SPC) MC00625W0402110R








Qty Reference Designator Description Supplier Part Number 1 U2 500 mA, low noise low dropout (LDO)

regulator with soft start Analog Devices ADP7105ACPZ-5.0-R7

1 C43 Ceramic capacitors, 4.7 μF, 10 V, 10%, 0603, X6S

Murata GRM185C81A475KE11D

2 C13, C14 Ceramic capacitors, 4.7 μF, 25 V, 10 %, 1206, X7R

KEMET C1206C475K3RACTU

1 JP1 PCB connector, jumper, straight, male, 2-pin, 2.54 mm pitch

Amphenol FCI 69157-102HLF

1 SHIELD PCB connector, 4 mm socket Rapid 20054

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed.

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