First International Symposium on Nano-manufacturing, April 24-26, 2003

Future Challenges and Needs for Nano-Electronics from Manufacturing View Point

Yoshio NishiStanford Nanofabrication Facility

Department of Electrical EngineeringStanford University

Stanford, California 94305-4070nishiy@stanford

“Manufacturing”

• To make by hand or esp., by machinery, often on a large scale

• To work (wool, steel, etc.) into usable form• To produce (something) in a way regarded

as mechanical• To make up (excuse, evidence, etc)

Webster's New World Dictionary of the American Language

1958: 1st Integrated Circuit Jack S. Kilby

1960: First MOSFET by D. Kahng and M. Atalla

1959: 1st Planar Integrated Circuit

Robert N. Noyce

magnification

6 ? m NMOS LSI in 1974

Layers

Source/Drain diffusion

Gate oxide

Si substrate

Field oxide

Poly Si gate electrode

Interlayer dielectrics

Aluminum interconnects

Passivation

MaterialsSi, SiO2

BPSGPSGAl

AtomsSi, O, Al,P, B

(H, N, Cl)

Si substrate

Field SiO2

ILD (InterlayerDielectrics)

Al interconnects

Passivation (PSG)

(SiO2 + BPSG)Si substrate

Field SiO2

ILD (InterlayerDielectrics)

Al interconnects

Passivation (PSG)

(SiO2 + BPSG)

Poly Si gate electrode

Gate SiO2

Source / Drain

Poly Si gate electrode

Gate SiO2

Source / Drain

Year of introduction Transistors

4004 1971 2,250

8008 1972 2,500

8080 1974 5,000

8086 1978 29,000

286 1982 120,000

386™ processor 1985 275,000

486™ DX processor 1989 1,180,000

Pentium® processor 1993 3,100,000

Pentium II processor 1997 7,500,000

Pentium III processor 1999 24,000,000

Pentium 4 processor 2000 42,000,000

1900 1950 1960 1970 2000VacuumTube

Transistor IC LSI ULSI

10 cm cm mm 10 ?m 100 nm

In 100 years, the feature size reduced by one million times

10-1m 10-2m 10-3m 10-5m 10-7m

What conditions made sequential growth of IC manufacturing?

• Planar technology for precise control of positions in two dimensional plane

• Ion implantation for vertical control of impurity profiles• Film deposition and etching enabling vertical scaling• CD control within 10% of minimum geometry• Clean technology resulting in defect density control for

over 85% yield for 109devices on chip.• Every new technology node enabled 30-50% cost

reduction per bit or gate over previous node• Highly controlled environment for credible statistical data

acquisitions

196019601960

DSP SystemsDSP Systems

HandheldHandheldHandheld

LaptopLaptopLaptop

PCPCPC

WorkstationWorkstationWorkstation

MinicomputerMinicomputerMinicomputer

MainframeMainframeMainframe

197019701970 198019801980 199019901990 200020002000

1 MIP 10 MIPS 100 MIPS 1000 MIPS1 MIP 10 MIPS 100 MIPS 1000 MIPS1 MIP 10 MIPS 100 MIPS 1000 MIPS

BipolarTTLCompilers

BipolarBipolarTTLTTLCompilersCompilers

NMOSCISC MPUSC MemoryNetworksDatabases

NMOSNMOSCISC MPUCISC MPUSC MemorySC MemoryNetworksNetworksDatabasesDatabases

CMOSRISC MPUDSPLANGraphicsSymbolic

Computing

CMOSCMOSRISC MPURISC MPUDSPDSPLANLANGraphicsGraphicsSymbolicSymbolic

ComputingComputing

Submicron CMOSSpeech I/OImaging I/OGlobal & Mobile

ConnectivityVisualizationMegabit MemoriesLow-cost DSP

Submicron CMOSSubmicron CMOSSpeech I/OSpeech I/OImaging I/OImaging I/OGlobal & MobileGlobal & Mobile

ConnectivityConnectivityVisualizationVisualizationMegabit MemoriesMegabit MemoriesLowLow--cost DSPcost DSP

EnablingTechnologyEnablingTechnology

Moving Power to the PersonMoving Power to the PersonMoving Power to the Person

Decanano CMOSUbiquitous

CommunicationsAccess

Mobile Digital VideoVirtual RealityGigabit MemoriesSuper DSP VLIW

Decanano CMOSDecanano CMOSUbiquitousUbiquitous

CommunicationsCommunicationsAccessAccess

Mobile Digital VideoMobile Digital VideoVirtual RealityVirtual RealityGigabit MemoriesGigabit MemoriesSuper DSP VLIWSuper DSP VLIW

P. P. Gelsinger, “Microprocessor for the New Millennium: Challenges, Opportunities, and New Frontiers,” Dig. Tech. 2001 ISSCC, San Francisco, pp.22-23, February, 2001

Microprocessors Trend

Today: 2002 (Intel)

Lg sub-70 nm

Tox 1.4 nm

f 2.53 GHz

P several 10 W

2008 (Intel)

Lg sub-25 nm

Tox 0.7 nm

f 30 GHz

P 10 kW

N 1.8B

Heat Generation

2002? 10W/cm2 Hot Plate2006? 100W/cm2 Nuclear Reactor2010? 1000W/cm2 Rocket Nozzle2016? 10000W/cm2 Sun Surface

Past: 1972 (Intel)

Lg 10,000 nm

Tox 1200 nm

f 0.00075 GHz

(75 kHz)

In 2000, for the first time, semiconductor revenues in communication exceeded revenues in PC sector.

Source: Dataquest

15%

20%

25%

30%

35%

1996 1997 1998 1999 2000 2001Estimate

PC

Communications

% of Semiconductor Revenue

Personal Internet Products

I-VideoPhone

IP Phone

DigitalCamcorder

Digital Still Camera

PDACamera

Network Still Camera

DSL Modem

Bluetooth Enabled Products

Home Networking

Cable Modem

iSTBInternet

Audio PlayerDigital Video

Recorder/ServerDigital

TVDAB

Radio

PDAsPDAs

PDA

3G Cellular Phone

2G/2.5GCellular Phone

InternetDSP &Analog

InternetDSP &Analog

MainframeTransistorsMainframeTransistors

MinicomputerTTL/Logic

MinicomputerTTL/Logic

PCMicro-

processor

PCMicro-

processor

1 perCompany

1 perDepartment

1 perPerson

MANY perPerson!

Technology has made systems more personal

1960s 1970s 1980s 1990s 2000s 2010s

DigitalCMOSDigitalCMOS

AnalogCMOSAnalogCMOS

PowerMgmt

PowerMgmt

RadioBiCMOS

RadioBiCMOS

MemoryMemory

PassivesPassives

Technology in the Internet AgeSOC Integration Strategy for Cell Phones

Analog/Digital

Analog/Digital

PassivesPassives

RadioRadio

PowerMgmt

PowerMgmt

MemoryMemory

MemoryMemory

MixedSignal Radio

MixedSignal Radio

AnalogDigital Power

AnalogDigital Power

SingleChip CellPhone

SingleSingleChip CellChip CellPhone Phone

Today 200?

Digital RadioDigital Radio

BasebandProcessorBasebandProcessor

EmbeddedNon-Volatile

Memory

EmbeddedNon-Volatile

Memory

Technology Innovations for Analog and implications to manufacturing

Dennis Buss, 2001 ISSCC

? Poly resistors: +1 mask

? Isolation: +1 mask

? Dual-gate CMOS: +3 masks

? High-density capacitors: +1 mask

? Characterization/modeling:– Matching– Temperature dependence– Non-linearity– Noise

? Poly resistors: +1 mask

? Isolation: +1 mask

? Dual-gate CMOS: +3 masks

? High-density capacitors: +1 mask

? Characterization/modeling:– Matching– Temperature dependence– Non-linearity– Noise

Technology In The Internet EraAnalog SOC Integration: #1 Problem

• Reduced dynamic range: KT/C noise

• Reduced head room

• High current required for fixed power functions

• Low drive current in switches

0.35 0.25 0.18 0.13 0.110.6 0.091.0 0.8

1

2

3

4

5

Vol

tage

Gate Length (? m)

5V 5V 5V

3.3V

2.5V

1.8V1.5V

1.2V1.0V

What does “Internet Age”imply for silicon-based ICs

and Beyond?

Moore’s LawScaling principleLaw of Economics

19

Moore’s Law and Scaling

• The basic MOSFET structure has not changed, but the structural details and materials have changed for transistor, isolation, and interconnect.

• Scaling uncovers problems that could be ignored previously.

• For each generation, available materials and equipment generally set the practical limits (litho is just one example).

• Improvements in materials and equipment as well as circuit cleverness may permit successful implementation of designs that were previously rejected.

Challenge(Unknown )

Ultimatelimit

Development(for production)

Research(Tr confirmed)

Production

20 nm30 nm

Lg

High performance

Low power

Mobile, low cost

6 nm3 nm

1 nm

0.6 nm

2 nm

Technology Driverswhich contributed technology and

Manufacturing with Large production volumeStrong pull for technology ROI for R&D investment

22

?DRAM for• most of front-end processings• lithography• packaging for low cost/small form factor• fab engineering

?High Performance Logic / MPU for• transistor performance• multi-level interconnect• design tools• high pin count packaging

23

Mobile communication and computing in the Internet Age provide ever increasing challenges, i.e.

– ultra-low power consumption– digital and analog integration including RF– cost sensitivity

As a new technology driver– conflicting requirement for digital and analog

for supply voltage– on-chip noise management issue

How far can we go with scaled CMOS for IC manufacturing,i.e. with

top down manufacturing methodology?

Simplified Cross-Section of MOSFET Transistor Structure

Upper interfacial region

Bulk high-k film

Lower interfacial region

Gate electrode, poly

Si Substrate (or SOI with Si

thickness ?1/3 Lg)

Source Drain

Spacer

High-k Gate Dielectric Stack

P.M. Zeitzoff, R.W. Murto and H.R. Huff, Solid State Technology, July 2002

Lg

On going efforts to extend the life of silicon based CMOS

• High K gate stack with metal gate• Channel mobility improvement• SOI• Ultra shallow source and drain junction• Low K/Cu for interconnect• Continuous shrink with lithography

evolutions

Ultimate limits?

10-5

10-4

10-3

10-2

10-1

100

101

102

1970 1990 2010 2030 2050Year

MPU LgJunction depthGate oxide thickness

Direct-tunneling limit in SiO2

ITRS Roadmap(at introduction)

Wave length of electron

Distance between Si atomsSize

(?m

), V

olta

ge(V

)

Min. V supply

10 nm

3 nm

0.3 nm

ULTIMATELIMIT

0.001

0.010

0.100

1.000

10.000

1960 1970 1980 1990 2000 2010Year of Publication (or First Production)

Sta

ted

Gat

e L

eng

th (m

icro

ns)

IEDM Titles

IEDM Average

94 SIA & Fit

2001 ITRS MPU

Single Electron DevicesNanotubesResonant Tunneling

Super Scaled CMOS

CMOS

NanoElectronics

DecaNanoElectronics

SubMicron CMOS

NMOS

Gate Lengths from IEDM Paper Titles

High Resolution TEM showing 0.03 ? m Channel Length

30 nm Channel Length78 columns of Si atoms

Source Drain

4 layers of Si atomsconsumedto create

1.1nm SiO2

4 nm

1.1nm SiO2

electronmean free path

two decadesin 10 nm

donor atom

acceptor atom

inversion charge

Polysilicon Gate

Needs for Metal Gate Electrodes

• Elimination of poly silicon depletion for smaller EOT• Work function engineering for elimination of channel

implant in order to minimize impurity scattering in the channel as well as avoid stochastic fluctuation of the threshold voltage of MOSFET.

• Needs atomic/molecular level of understandings of “interface structure” relevant to “work function” in multi-layer structure

Needs for high K dielectrics

• Larger K without frequency dispersion• Minimum channel carrier mobility

degradation • Allow metal electrode for work function

engineering• Stable during process integration

environment• Thickness controllability, Manufacturability

• Yan et al. (APL 79 [11] 2001) used micro-contact printing of alkylhalosilane self-assembled mono-layers on SiO2 to define ALD-deactivated pattern

• ZnO ALD of circular dots (Tsubs = 125?C)

•Reported near-complete deactivation of SAM-coatedoxide surface

Needs for smaller geometries

• 248nm• 193nm• 157nm• Charged beams• EUV• Nanoimprint/soft imprintWithout manufacturing cost increase per

gate or bit

Amortization of Mask Cost (130-nm)

1

10

100

1000

1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08

Chips Produced

Co

st p

er C

hip

[$]

A real opportunity for a nano-manufacturing paradigmwhich is “small-lot friendly” !

Robert Doering, May 12,2002

Subset of 2001 ITRS

1099987Number of wiring levels

2883.0

2513.0

2183.0

1903.5

1603.2

1302.4

(W)Power:High perfLow power

0.40.6

0.50.7

0.60.8

0.70.9

11.1

1.11.2

(V)VDD::High perfLow power

3092154677338619397(106)Transistor/chip

2.42.63.75.76.911(ps)Gate delay

0.60.81.21.51.92.5(nm)Equivalent oxide tox

9/1313/1818/2525/3537/5365/90(nm)Gate length, physical/printed

MPU

23823918118393127(mm2)Chip size

6432841.512(Gb)Memory size

DRAM

2232456590130(nm)General lithography

201620132010200720042001YEAR

In fact silicon based CMOS is already in the world of

“nanoelectronics”

What’s beyond scaling, the world of “nanoelectronics”?

• Electrostatic improvement of MOSFETFINFET, Vertical MOS, FDSOI

• Improvement through materials for MOSFEThigh K gate, low-K ILD, gate metal work function, higher mobility channel, Ge channel, Schottky S/D

• New functional materialsferroelectric memory, MRAM, Ovonic/polymer memory, single electron/quantum dots memory

• Non-silicon 3D solution, nanowire, nanotube• MEMS/NEMS integration• Optical interconnect/on-chip receiver

Will Future Nanoelectronics Technologies Complement or Replace CMOS ?

Source: 2001 ITRS

Double-Gate Transistor Structures

Simplified view ofFinFET

(one type of double-gate

MOSFET)

S G DS G D

Source Drain

Poly Gate

Fin

Source Drain

Poly Gate

Fin

Top View

SiO2

BOXBOX

GateGate

DrainDrainSourceSourceSiOSiO22 SiOSiO22

Schematic Cross-Section

Simplified view ofFinFET

(one type of double-gate

MOSFET)

S G DS G D

Source Drain

Poly Gate

Fin

Source Drain

Poly Gate

Fin

Top View

Simplified view ofFinFET

(one type of double--gate MOSFET)

S G DS G D

Source Drain

Poly Gate

Fin

Source Drain

Poly Gate

Fin

Top View

SiO2

BOXBOX

GateGate

DrainDrainSourceSourceSiOSiO22 SiOSiO22

Schematic Cross-Section

SiO2

BOXBOX

GateGate

DrainDrainSourceSourceSiOSiO22 SiOSiO22

Schematic Cross-Section

SiO2

BOXBOX

GateGate

DrainDrainSourceSourceSiOSiO22 SiOSiO22

Schematic Cross-Section

SiO2

BOXBOX

GateGate

DrainDrainSourceSourceSiOSiO22 SiOSiO22

SiO2

BOXBOX

GateGate

DrainDrainSourceSourceSiOSiO22 SiOSiO22

Schematic Cross-Section

S DG

source

top gate

bottom gate drain

100 nm

IBM ‘97Double Gate

SOI

FinFET

T-J. King and C. Hu, UC/Berkeley and Mark Bohr, ECS Meeting PV 2001-2, Spring, 2001Key advantage: relatively

conventional processing, largely compatible with current techniques

Mask Adder to High Perf Logic Process

Standby Power

Random Access

Area (mm2) for 1Mbit @ 90 nm node

Embedded Memory Technology

Technology in the Internet Age

0 - 2

High

Yes

1.35

6 - 8

NV

No

0.35

6 - 8

High

Yes

0.4

SRAM FLASH DRAM FRAM MRAM OUM

2

NV

Yes

0.6

3 - 4

NV

Yes

0.6

3 - 4

NV

Yes

0.4

The Ideal MOS Transistor

Challenges Facing a Pervasive Replacement of “Ultimate Scaled CMOS”

• Cost of less than 0.5 micro-cents per logic gate

• Greater than 4x108 logic gates per cm2

• Greater than 1010 “minimum-size switches” per cm2 (e.g., SRAM transistors)

• Cost of less than 50 nano-cents per bit of memory

• Greater than 30 Gbits of memory per cm2

• Intrinsic switching speed greater than 5 THz

• Power consumption of less than 6 µW per MOP/sec

• Reliability of greater than 105 hours (~ 10 years) operating lifetime

• SER of less than a few thousand FITs per Mbit in terrestrial environment

• Capable of “mass production” (e.g., > 1 million units /day)

• Ability to integrate logic, analog, RF, memory (high-speed, high-density, nonvolatile, etc.)

Robert Doering, May 12, 2002

Opportunity for nano-scale devices

• Proof of concept • Manufacturability demonstrations

reproducibility under controlled environmentcontrollability of every parameters, positioning capability with accuracy,

• ReliabilityAcceleration mechanism for possible failures based upon thorough understanding of physics and chemistry behind

• Cost of ownership (COO) competitiveness

What conditions made sequential growth of IC manufacturing?

• Planar technology for precise control of positions in two dimensional plane

• Ion implantation for vertical control of impurity profiles• Film deposition and etching enabling vertical scaling• CD control within 10% of minimum geometry• Clean technology resulting in defect density control for

over 85% yield for 109devices on chip.• Every new technology node enabled 30-50% cost

reduction per bit or gate over previous node with right technology driver

• Highly controlled environment for credible statistical dataacquisitions

New era beyond microelectronics

• Aggressive introduction of new materials• New device structures based upon new

materials, as well as new phenomena• Research under controlled environment

with capability integration• New characterization capability coupled

with adequate modeling and simulation capability

Needs for Paradigm Changes

• System/architecture level consideration from early stage of device research, Connection between top-down and bottom up approaches

• Horizontal geometry control, CD and overlay: Limited and costly

Should it be horizontal?• Vertical geometry control: more precise, e.g.

atomic layer deposition Can we build devices vertically?Careful introduction of bottom-up approach?

47

Summary

• Internet Era drives much more variety of nanoelectronics technology than the previous eras which will serve as “system level driver”.

• Silicon-based CMOS technology will remain as the basic platform in the foreseeable future with nanoelectronics devices with new materials and new electrostatic improvements as far as manufacturing cost per function decreases.

• Top down manufacturing methodology faces tough challenges in terms of further manufacturability improvement

• New functionality/new devices introduced via nanotechnology/ nanoelectronics will have opportunity if they can be embedded to silicon platform coupled with design paradigm changes.

• Environment with a variety of materials and processes handling capability coupled with strong characterization capability is a key enabling infrastructure.