Effects of Underfill Delamination and Chip Size on the

Effects of Underfill Delamination and Chip Size on the Reliability of Solder Bumped Flip Chip on Board

The International Journal of Microcircuits and Electronic Packaging, Volume 23, Number1, First Quarter 2000 (ISSN 1063-1674)

© International Microelectronics And Packaging Society 33

Effects of Underfill Delamination and Chip Sizeon the Reliability of Solder Bumped Flip Chip onBoard

John H. Lau and S.-W. Ricky Lee*Express Packaging Systems, Inc.1137 San Antonio RoadPalo Alto, California 94303Phone: 650-919-0300Fax: 650-919-0303e-mail: [email protected]

*On sabbatical leave from Department of Mechanical Engineering, Hong Kong University ofScience& Technology

Abstract

An investigation on the solder bumped Flip Chip on Printed Circuit Board (FCOB) is presented in this paper. The emphasis is placedon the effects of delamination crack between the underfill encapsulant and the solder mask on the solder joint reliability of FCOB. Inthe present study, a fracture mechanics approach is employed. The strain energy release rate at the crack tip between the underfill andthe solder mask is presented. The maximum inelastic stress and strain in the corner solder joint for all the investigated cases arecalculated for comparison. The effects of chip size on the solder joint reliability of FCOB with perfect and imperfect underfills(including without underfill) are evaluated. The finding of this study should contribute to a better understanding in the thermal-mechanical behavior of solder bumped Flip Chip assemblies.

Key words:

Imperfect Underfill, Flip Chip on Board, Delamination, Frac-ture Mechanics, and Solder Joint Reliability.

1. Introduction

Solder joint thermal-fatigue reliability of a solder bumped FlipChip on low cost substrate with a perfect underfill encapsulanthas been demonstrated by many researchers through thermalcycling tests and mathematical modeling1-5. However, due to ofmanufacturing defects such as fluxing, dispensing, and curing,and the out-gassing of PCB, imperfections such as voids and

cracks, and missing fillets are not uncommon. In Reference6, theeffects of missing fillets have been studied. In this paper, theeffects of imperfect underfill (in term of delamination) on thereliability of solder bumped Flip Chip on low cost substrates arestudied. In addition, the effects of chip size on the imperfect un-derfill Flip Chip assemblies are investigated.

Figure 1 shows a solder bumped Flip Chip on low cost sub-strate assembly. As mentioned earlier, if the underfill is perfect,then, there is no solder joint reliability problem. However, solderjoint reliability becomes an issue if either (1) there is delamina-tion between the underfill and the passivation of the silicon chip,or (2) there is delamination between the underfill and the soldermask on the organic substrate, or (3) both effects.

For case (1), the crack may be initiated at the upper right orleft hand corners of the solder joint. These initial cracks maypropagate either in the horizontal direction near the under bumpmetallurgy or downward the diagonal of the solder joint. On theother hand, for case (2), the crack may be initiated on the lower

© International Microelectronics And Packaging Society


Intl. Journal of Microcircuits and Electronic Packaging

34

right or left hand corners of the solder joint. These initial cracksmay propagate either in the horizontal direction near the copperpad or upward the diagonal of the solder joint. Finally, for case(3), the solder joint could fail much earlier and the cracks wouldlook like those in Figure 1. In this study, only case (2) will beconsidered.

Underfill

Solder Mask

Passivation

12.7mm (or 6.35mm)

1.57mm

0.73mm

Al

Cu0.63mm

Chip

L=12.5mm (or 6.15mm)

PCB

SYMM.

Chip Al Pad

Passivation

Solder Mask

Delaminations

PCB

UnderfillCracks

Figure 1. Failure modes for solder bumped Flip Chip onPCB with imperfect underfill.

2. Problem Definition

In this study, before one would investigate the problem ofdelamination (crack) between the underfill and the solder maskon the PCB, a study of the effects of chip size on the solder jointreliability of Flip Chip on board with a perfect underfill and with-out underfill has to be undertaken. It is well-known that, withoutunderfill, the larger the chip the higher the stresses and strains atthe corner solder joints due to the thermal expansion mismatchbetween the silicon chip and the epoxy glass substrate. However,the objective of this paper is to show that, with a perfect under-fill, the chip size does not affect the solder joint reliability.

For Flip Chip assemblies with imperfect underfill, the objec-tives are to show that: (1) for the same delamination (crack length),the chip size does not affect the solder joint reliability, (2) thedelamination will not become unstable under the present ther-mal loading, and (3) the stresses and strains at the corner solderjoint increase as the crack length increases. It should be noted

that the scope of this study is not to determine the thermal-fa-tigue life, but to investigate the effects of chip size on solder jointreliability with perfect underfills and imperfect underfills.

The loading condition in this study is a temperature drop from110 oC to 25 oC. The material properties used in the analyses aregiven in Table 1. It can be seen that the eutectic solder (63Sn-37Pb) is considered a temperature-dependent elasto-plastic ma-terial (Figures 2 and 3) and all other constituents are consideredlinear elastic materials. The chip sizes under consideration are:2.12 mm x 1.4 mm, 6.36 mm x 4.2 mm, 10.6 mm x 7 mm, and21.2 mm x 14 mm. All the chips have solder bumps on the twoshort edges only. Detailed dimensions of the Al pads and passi-vation on the chip, the copper pad and the solder mask on thePCB, the solder joint, and the PCB are shown in Figures 1 and 4.

Table 1. Material properties of the solder bumped Flip Chipassembly.

MaterialProperties

Young’sModulus

(Gpa)

Poisson’sRatio

(v)

ThermalExpansionCoefficient(α) ppm/

FR4 22 0.28 18.5Copper 76 0.35 17

63 Sn-37 Pb r See note 0.4 21Solder Mask 6.9 0.35 19Silicon Chip 131 0.3 2.8Solder Mask 6.9 0.35 19

AL 69 0.33 22.8Si3N4 314 0.33 3

Underfill 6 0.35 30

Note: Young’s modulus as well as stress-strain relations ofsolder are temperature-dependent.

0

10

20

30

40

50

60

70

0 0.002 0.004 0.006 0.008 0.01 0.012

Strain (%)

Str

ess

(MP

a)

0oC

20oC

40oC

60oC

80oC

100oC

63Sn-37Pb Solder

Figure 2. Non-linear temperature-dependent stress-strainrelations of solder.




22

24

26

28

30

32

34

0 10 20 30 40 50 60 70 80 90 100 110

Temperature (oC)

Yo

un

g's

Mo

du

lus

(GP

a) 63Sn-37Pb Solder

Figure 3. Non-linear temperature-dependent Young’smodulus of solder.

Underfill

Solder Mask

Passivation

12.7mm (or 6.35mm)

1.57mm

0.73mm

Al

CuCrack Tip0.63mm

Chip

a

L=12.5mm (or 6.15mm)

PCB

SYMM.

0.1mm

Crack

Chip

63Sn-37PbSolder Joint

1µmAl Pad (1µm)

0.05mm

20µm

Underfill

Figure 4. Solder bumped Flip Chip with cracks betweenunderfill and solder mask.

To study the present problems, a commercial Finite Elementcode called ANSYS is employed. A two-dimensional model isestablished using 8-node plane strain elements. Due to symme-try in the assembly structure, only half of the diagonal cross-section is modeled.

3. Effects of Chip Size on Solder JointReliability with and without PerfectUnderfill

3.1. Without Underfill

The second through fourth columns of Table 2 show the vonMises stress, accumulated equivalent plastic strain, and shearplastic strain in a corner solder joint for different chip sizes onPCB without underfill. It can be seen that: (1) all the stress andplastic strains are very large due to the thermal expansion mis-match between the silicon chip and the FR-4 PCB, (2) the shearplastic strain is larger than the accumulated equivalent plasticstrain, since it is dominated by shear deformation, and (3) thestress and strains increase as the chip size increases.

Table 2. Stress and strains in the corner solder joint withdifferent chip sizes with and without perfect underfill.

Chip Size (mm×mm) 2.12x1.4 6.36×4.2 10.6×7.0 21.2×14

Von MisesStress(MPa)

138 210 248 292

EquivalentPlastic

Strain (%)

3.34 5.53 6.68 8.00WithoutUnderfill

ShearPlastic

Strain (%)

5.56 9.12 11.0 13.1

Von MisesStress(MPa)

44.6 44.8 44.8 44.8

EquivalentPlastic

Strain (%)

0.537 0.544 0.544 0.544WithUnderfill

ShearPlastic

Strain (%)

0.851 0.862 0.862 0.862

It is interesting to note that the maximum shear stress at theinterface between the underfill and the passivation is 23 MPaand at the interface between the underfill and the solder mask is11.5 MPa. These values are lower than those measured in Refer-ence6 where the former is >50 MPa and the latter is >30 MPa.Thus, the crack at these locations will not be initiated under thepresent thermal loading.

3.2. With Perfect Underfill

The last three columns of Table 2 show the von Mises stress,accumulated equivalent plastic strain, and shear plastic strain inthe corner solder joint for different chip sizes on PCB with aperfect underfill. It can be seen that: (1) the stress and plasticstrains are almost the same for all the chip sizes, since the chipand the PCB are tightly adhered by the perfect underfill and,thus, the relative deformation of the solder joint is very small,and (2) the stress and plastic strains are much smaller than thosewithout underfill.




36

4. Effects of Chip Size on Solder JointReliability with Imperfect Underfill

4.1. Implementation of Fracture Mechanics inFinite Element Analysis

In the present study, eight-node plane strain elements are usedto model the Flip Chip package assembly. The crack along theinterface between the solder mask and the underfill encapsulantis simulated by an array of double nodes (see Figure 5). A uni-form temperature drop from 110oC to 25oC is applied to the model.

(a) Before Loading

(b) After Loading

Crack Surface

Crack Tip

r y

x

x

y

(a) Before Loading

(b) After Loading

δδδδy

δδδδx

Figure 5. Schematic diagram for the crack tip openingdisplacement (CTOD).

The calculation of fracture parameters is based on the cracktip opening displacement (CTOD). According to Hutchinson andSuo7, the relationship between stress intensity factors (KI andKII) and CTOD (δx and δy, see Figure 5) can be expressed in acomplex variable form as follows,

( ) ε

ππεεδ iIII

xy rrE

KiKi

i2/1

* 2)cosh()21(8 �

��

�++

=+δ (1)

where i is the imaginary unity, r is the distance from the crack tip; xand y are the direction parallel and the direction perpendicular tothe crack, respectively. In addition, E* and ε denote the effectiveproperties of materials adjacent to the crack. For a bi-material inter-face crack (in the present paper assuming underfill as material 1and solder mask as material 2), these effective material propertiesare defined by Rice8 as follows,

( )21

21* 2EEEEE

+=

(2)

�

��

�

+−=

ββ

πε

11ln

21

(3)

and, for the plane strain case,

)1()1()21()21(

21

1221

1221

νµνµνµνµβ

−+−−−−= (4)

where µ and ν denote shear modulus and Poisson’s ratio, respec-tively, and the subscripts (1 and 2) indicate the correspondingmaterials. After certain mathematical operations, the stress inten-sity factors of opening mode (KI) and shearing mode (KII) can beobtained from Equation (1) as follows,

KI = [Acos(εlnr) + Bsin(εlnr)]/D (5)

KII = [Bcos(εlnr) – Asin(εlnr)]/D (6)

where,A = δy - 2εδx (7)

B = δx + 2 εδy (8)

(9)

Subsequently, by the formula of Malyshev and Salganik9, thestrain energy release rate can be obtained as follows,

(10)

It should be noted that,

(11)

and,




22IIIeff KKK += (12)

where Keff

is the effective stress intensity factor at the crack tip.Furthermore, a phase angle is defined by Hutchinson and Suo7 asfollows,

(13)

This quantity is considered an index for measuring the domi-nance of Mode I (opening) or Mode II (shearing) fracture.

4.2. Stress and Strains at the Corner SolderJoint

Figure 6 shows the deformed shape of the 10.6 mm x 7 mmFlip Chip assembly with an imperfect underfill (crack length =0.615 mm). The von Mises stress, accumulated equivalent plas-tic strain, and shear plastic strain in the corner solder joint areshown in Figure 7. It can be seen that the maximum values ofthese parameters are at the lower left-hand corner of the solderjoint, where is the crack initiation between the underfill and thesolder mask.

Underfill

Solder MaskCrack Tip

PCB

ChipSolder Joint

Figure 6. Deformed shape of a solder bumped Flip Chipwith imperfect underfill (crack length = 0.615 mm).

von MisesStressDistribution(MPa)

Max.

EquivalentPlasticStrain

Max.

Shear PlasticStrain

Max.

Figure 7. Typical stress and strain contours in the cornersolder joint.

For other crack lengths and chip sizes the simulation resultsare shown in Table 3. It can be seen that: (1) for a given cracklength, the von Mises stress, accumulated equivalent plastic strain,and shear plastic strain in the corner solder joint are the same fordifferent chip sizes, (again, this is because the chip, underfill,and PCB are deformed as a unit and thus the relative displace-ment of the solder joint is very small), and (2) as the crack lengthsincrease, all the von Mises stress, accumulated equivalent plasticstrain, and shear strain at the corner solder joint increase. Fig-ures 8, 9, and 10 show, respectively, the von Mises stress, accu-mulated equivalent plastic strain, and shear plastic strain in thecorner solder joint with different crack lengths.




38

Table 3. Stress and strains in the corner joint with differentchip sizes and crack lengths.

Chip Size (mmxmm)Quantities Crack Length (mm)10.6x7 21.2x14

0 44.8 44.81.27 89.7 89.72.54 107 107

von Mises Stress(Mpa)

5.14 120 1200 0.544 0.5441.27 1.90 1.902.54 2.42 2.42

Equivalent PlasticStrain (%)

5.14 2.82 2.820 0.862 0.8621.27 3.27 3.272.54 4.16 4.16

Shear PlasticStrain (%)

5.14 4.84 4.84

0

20

40

60

80

100

120

140

0 0.2 0.4 0.6 0.8 1Normalized Crack Length (a/L, L = 12.7 mm)

Max

imu

m v

on M

ises

Str

ess

(MP

a)

Figure 8. Maximum von Mises stress in the corner solderjoint with different crack lengths.

0

1

2

3

4

0 0.2 0.4 0.6 0.8 1

Normalized Crack Length (a/L, L = 12.7 mm)

Max

imu

m E

qu

ival

ent

Pla

stic

Str

ain

(%

)

Figure 9. Maximum equivalent plastic strain in the cornersolder joint with different crack lengths.

0

1

2

3

4

5

6


Max

imu

m S

hea

r P

last

ic S

trai

n (

%)

Figure 10. Maximum shear plastic strain in the cornersolder joint with different crack lengths.

4.3. Stain Energy Release Rate at the CrackTip

The strain energy release rate at the crack tip for differentcrack lengths is shown in Figure 11. It can be seen that the strainenergy release rate is decreasing as the crack length increases.This indicates that, for a given crack length and with the currenttemperature change, the crack will not become unstable. Figure12 shows the phase angle with different crack lengths. It can beseen that the crack between the underfill and the solder mask isdominated by the shearing mode of fracture.

0

0.05

0.1

0.15

0.2

0.25

0.3


Str

ain

En

ergy

Rel

ease

Rat

e (J

/m2 )

Figure 11. Strain energy release rate at the crack tip of theunderfill with different crack.




0

15

30

45

60

75

90


Ph

ase

An

gle

(deg

ree)

Figure 12. Phase angle at the crack tip of the underfillwith different crack lengths.

5. Summary

The effects of chip size on the solder joint thermal-fatiguereliability of solder bumped Flip Chip on PCB with perfect andimperfect underfills and without underfill have been investigated.The von Mises stress, accumulated equivalent plastic strain, andshear plastic strain in the corner solder joint, and the strain en-ergy release rate at the crack tip with different crack lengths arealso provided for understanding the thermal-mechanical behav-ior of Flip Chip assemblies. Some important results are summa-rized as follows.· For solder bumped Flip chip assembly without underfill, the

stress and strain increase as the chip size increases.· For solder bumped Flip Chip assembly with perfect underfill,

the chip size does not affect the solder joint reliability. Also,the stress and strains are much smaller than those withoutunderfill.

· For solder bumped Flip Chip assembly with imperfect under-fill and for a given crack length, the chip size does not affectthe solder joint reliability.

· For solder bumped Flip Chip assembly with imperfect under-fill, the stress and strains in the corner solder joint increase asthe crack length increases.

· For solder bumped Flip Chip assembly with imperfect under-fill, the strain energy release rate at the crack tip between theunderfill and the solder mask decreases as the crack lengthincreases. Thus, the crack along the interface will be arrestedunder the present thermal loading.

· For solder bumped Flip Chip assembly with imperfect under-fill, the crack between the underfill and the solder mask isdominated by the shearing mode of fracture.

References

1. A. Rai, H. Dotta, T. Tsukamoto, H. Fujiwara, T. Ishii, and H.Matsui, “COB (Chip On Board) Technology: Flip Chip Bond-ing Onto Ceramic Substrates and PWB (Printed WiringBoards)”, Proceedings of the International Symposium ofMicroelectronics, ISHM ‘1996, pp. 474-481, 1990.

2. A. Rai, Y. Dotta, T. Nukii, and T. Ohnishi, “Flip Chip COBTechnology on PWB”, Proceedings of International Micro-electronics Conference, IMC ‘92, June 1992, pp. 144-149.

3. Y. Tsukada, Y. Mashimoto, T. Nishio, and N. Mii, “Reliabil-ity and Stress Analysis of Encapsulated Flip Chip Joint onEpoxy Base Printed Circuit Board”, Proceedings of the FirstASME/JSME Advances in Electronic Packaging Conference,Milpitas, California, pp. 827-835, April 1992.

4. Y. Guo, W. T. Chen, and K. C. Lim, “Experimental Determi-nations of Thermal Strains in Semicondutor Packaging Us-ing Moire Interferometry”, Proceedings of the First ASME/JSME Advances in Electronic Packaging Conference,Milpitas, California, pp. 779-784, April 1992.

5. Y. Tsukada, S. Tsuchida, and Y. Mashimoto, “Surface Lami-nar Circuit Packaging”, Proceedings of IEEE Electronic Com-ponents and Technology Conference, ECTC ‘92, San Diego,California, pp. 22-27, May 1992.

6. J. H. Lau, S.-W. R. Lee, C. Chang, and O. Chien, “Effects ofUnderfill Material Properties on the Reliability of SolderBumped Flip Chip on Board with Imperfect UnderfillEncapsulants”, Proceedings of IEEE Electronic Componentsand Technology Conference, ECTC ‘99, pp. 571-582, June1999.

7. J. W. Hutchinson, and Z. Suo, “Mixed Mode Cracking inLayered Materials,” Advances in Applied Mechanics, Vol. 29,pp. 64-187, 1992.

8. J. R. Rice, “Elastic Fracture Mechanics Concepts for Interfa-cial Cracks,” Journal of Applied Mechanics, ASME Trans-actions, Vol. 55, pp. 98-103, 1988.

9. B. M. Malyshev and R.L. Salganik, “The Strength of Adhe-sive Joints Using the Theory of Cracks,” Int. J. Fract. Mech.,Vol. 1, pp. 114-128, 1965.

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