8
The International Journal of Microcircuits and Electronic Packaging, Volume 24, Number 1, First Quarter, 2001 (ISSN 1063-1674) © International Microelectronics And Packaging Society 53 Solder Extrusions and Underfill Delaminations: a remarkable Flip Chip Qualification Experience Alfredo Genovese, Fulvio Fontana, Mario Cesana, Saverio Miliani, Ermanno Pirovano Celestica Italia, Vimercate e-mails: [email protected]; [email protected]; [email protected]; [email protected]; eapirova@celestica Abstract The last years have witnessed an explosive growing demand for all those electronic products, which can be jointly referred to as “mobile electronics”. To fulfill such a development rate in the worldwide market, the smaller, cheaper and faster philosophy in the microelectronics packaging industry needs to be pursued with ever increasing efforts. The most suitable packaging solution from this standpoint is mostly identified as the Flip Chip connection technology. In this environ- ment, the Celestica Italia Packaging and Technology Development Group performed a qualification run on Multichip Module Lami- nates (MCM-Ls). Two Flip Chip attach concepts, different in the die passivation, the under bump metallurgy and the array geometry, were evaluated on the same Sequential Build-up (SBU) substrate, with the devices reliability being the most important monitored property. It has been reported that the most detrimental effects on reliability come from the underfill delamination and from a problem related to the eutectic SnPb solder alloys after multiple reflows: the solder extrusion, otherwise called “Amoeba” phenomenon. The solution to these problems is vital for the Flip Chip technology: the successfull actions have regarded the fluxes, the reflow profiles, the surfaces cleanliness but especially the underfill. The latter represents the most influential aspect, even for the future Flip Chip evolution steps: the reworkability and the no-flow fluxing capability. 1. Introduction It is well known how the electronics manufacturers are in- creasingly incorporating Flip Chips (FC) into the design of a wide variety of electronic devices. Millions of flipped devices are now being assembled on organic laminates for a wide range of products such as cellular phones, pagers, disk drives, memory modules, and many more applications. To meet these products requirements, many underfills are cur- rently commercially available, with a wide variety of features ranging from ultra-fast curing capabilities to the extra-rapid flow- ing characteristics. Problems arise due to the conflict between the ever-rising requirements in terms of performances, sizes and costs and, on the other hand, reliability of all these devices. Ac- tually, packaging professionals recognize the difficulty to merge these features into one product. Depending on the final application, it will be typically neces- sary to decide on the level of acceptable compromise between the first three features and the latter, the reliability itself. Looking at a high cost and advanced technology Multichip module applica- tion, the Celestica Italia Packaging Development Group per- formed a massive amount of work aimed at reaching a certain level of qualification, necessary for a eutectic SnPb-based FC product implementation. Consequently, a great deal of attention has been dedicated to all the reliability aspects. In this context, the design, the materials, the process, the quali- fication tests and especially the failure analyses of the underfilled Flip Chips are presented in this work. 2. Background In the traditional Flip Chip assembly process, a solder bumped die is attached facedown onto a Printed Circuit Board (PCB) or a module using solder paste or flux only and then exposed to a soldering reflow cycle. To minimize solder joint stress-induced failures, it is necessary to dispense an underfill (UF) material along the chip edges. The capillary action, the bumps array, and some intrinsic UF characteristics determine the proper UF flow and gap filling ability. Underfill materials are essential to FC reliability since they reduce and redistribute stresses and strains in the structure, by minimizing the Coefficient of Thermal Expansion (CTE) mis-

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Solder Extrusions and Underfill Delaminations: a remarkable Flip Chip Qualification Experience

The International Journal of Microcircuits and Electronic Packaging, Volume 24, Number 1, First Quarter, 2001 (ISSN 1063-1674)

© International Microelectronics And Packaging Society 53

Solder Extrusions and Underfill Delaminations: aremarkable Flip Chip Qualification ExperienceAlfredo Genovese, Fulvio Fontana, Mario Cesana, Saverio Miliani, Ermanno PirovanoCelestica Italia, Vimercatee-mails: [email protected]; [email protected]; [email protected];[email protected]; eapirova@celestica

Abstract

The last years have witnessed an explosive growing demand for all those electronic products, which can be jointly referred to as“mobile electronics”. To fulfill such a development rate in the worldwide market, the smaller, cheaper and faster philosophy in themicroelectronics packaging industry needs to be pursued with ever increasing efforts.The most suitable packaging solution from this standpoint is mostly identified as the Flip Chip connection technology. In this environ-ment, the Celestica Italia Packaging and Technology Development Group performed a qualification run on Multichip Module Lami-nates (MCM-Ls). Two Flip Chip attach concepts, different in the die passivation, the under bump metallurgy and the array geometry,were evaluated on the same Sequential Build-up (SBU) substrate, with the devices reliability being the most important monitoredproperty. It has been reported that the most detrimental effects on reliability come from the underfill delamination and from a problemrelated to the eutectic SnPb solder alloys after multiple reflows: the solder extrusion, otherwise called “Amoeba” phenomenon.The solution to these problems is vital for the Flip Chip technology: the successfull actions have regarded the fluxes, the reflowprofiles, the surfaces cleanliness but especially the underfill. The latter represents the most influential aspect, even for the future FlipChip evolution steps: the reworkability and the no-flow fluxing capability.

1. Introduction

It is well known how the electronics manufacturers are in-creasingly incorporating Flip Chips (FC) into the design of awide variety of electronic devices. Millions of flipped devices arenow being assembled on organic laminates for a wide range ofproducts such as cellular phones, pagers, disk drives, memorymodules, and many more applications.

To meet these products requirements, many underfills are cur-rently commercially available, with a wide variety of featuresranging from ultra-fast curing capabilities to the extra-rapid flow-ing characteristics. Problems arise due to the conflict betweenthe ever-rising requirements in terms of performances, sizes andcosts and, on the other hand, reliability of all these devices. Ac-tually, packaging professionals recognize the difficulty to mergethese features into one product.

Depending on the final application, it will be typically neces-sary to decide on the level of acceptable compromise between thefirst three features and the latter, the reliability itself. Looking ata high cost and advanced technology Multichip module applica-tion, the Celestica Italia Packaging Development Group per-

formed a massive amount of work aimed at reaching a certainlevel of qualification, necessary for a eutectic SnPb-based FCproduct implementation. Consequently, a great deal of attentionhas been dedicated to all the reliability aspects.

In this context, the design, the materials, the process, the quali-fication tests and especially the failure analyses of the underfilledFlip Chips are presented in this work.

2. Background

In the traditional Flip Chip assembly process, a solder bumpeddie is attached facedown onto a Printed Circuit Board (PCB) or amodule using solder paste or flux only and then exposed to asoldering reflow cycle. To minimize solder joint stress-inducedfailures, it is necessary to dispense an underfill (UF) materialalong the chip edges. The capillary action, the bumps array, andsome intrinsic UF characteristics determine the proper UF flowand gap filling ability.

Underfill materials are essential to FC reliability since theyreduce and redistribute stresses and strains in the structure, byminimizing the Coefficient of Thermal Expansion (CTE) mis-

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match among the Silicon (Si), the organic substrate and the SnPbsolder joints. In addition, UF materials improve the thermal dis-sipation, the mechanical and moisture resistance, and provide ageneral protection from the external environment.

In the early stages of this project, a theoretical study into all ofthe above-mentioned problems was performed and the mainchemical, physical, and mechanical underfill properties were iden-tified 1-6. Taking these properties into consideration, a group ofcommercially available epoxy-based resin underfills were selectedfor evaluation. In order to select the best underfill-candidate, atest matrix was created and selection criteria established, inde-pendent of the ultimate package application. To make this selec-tion, the extensive analytical equipment set and especially theexpertise of the Vimercate Celestica Materials Laboratory wasused.

In a next phase, a number of experiments on the actual testvehicles (TVs) were defined and executed (process flow simula-tion, Highly Accelerated Stress Test (at 110°C, 60% R.H., 264hrs), to evaluate the influence of the chosen UF on the FC perfor-mance and reliability. After completing these tests and evalua-tion activities, the final process manufacturability would be faced.

3. About the Test Vehicle

The test vehicle’s name is Takumi (a Japanese word meaningCraftmanship), and it is shown in Figure 1. It is a multilayercomposite structure of Cu clad laminated epoxy woven glasssheets, to which a number of sequential built-up layers are added(2 plus 2, in this case). This provides a high-density wire-abilityfactor allowing for the fan out the dense interconnect pitch of thebumped Si devices. The carrier measures 37.5 mm x 37.5 mmand uses a de-populated staggered array of 360 eutectic SnPballoy balls (0.8 mm diameter, 1.27 mm pitch) for second levelassembly to the PCB.

For this purpose, a test board has been designed to allow forelectrical characterization of the first level interconnections be-fore and after the qualification stress tests. The devices, whichwere assembled on the carrier, are listed below and also shown inFigure 1.

Figure 1. Test board.

• Device A is 11.3 mm x 11.3 mm x 0.4 mm, has a 250-µmpitch, a 85-µm standoff, a Polyimide- based die passivation, aperipheral area array, and is daisy chained for continuity test-ing after mounting.

• Devices B & C are 12 mm x 12 mm x 0.6 mm and 6 mm x 12mm x 0.6 mm, respectively. They both have a 460-µm pitch,a 90-µm standoff, a Silicon Nitride-based die passivation, afull area array, and are daisy chained, too.

• Package D is a CSP, which is 9 mm x 8 mm, has 46 I/O, fullarray; and is daisy chained.The two die concepts have a different under bump metallurgy

(UBM). The supplier of Device A provides a UBM based on 5-µm E’less Nickel Phosphorus layer with a 50-nm immersion Goldprotection layer. The technology used on Devices B and C uses asputtering deposition of Aluminum (400 nm), Nickel-Vanadium(300 nm) and Copper (400 nm). The solder joint diameter is 145µm for both types of devices.

Through this project qualification, the intention has been thatof evaluating all these kinds of different Flip Chip features.

4. Underfill Choices

A total of 5 underfills were chosen for evaluation and all theproperties considered vital for the FC reliability were measured.Basing on the evaluations listed below, the 5 underfills wereranked in order of performance providing the best underfill forthe next phase of testing with the real test vehicle (Takumi).• The thermo-mechanical analyzer (TMA) measures the CTE,

which is considered the most important UF property: the SnPbsolder joint, connecting the two differentially expanded orshrunken components, is likely to be the most sensitive tomismatches in CTE. This is the reason why the CTE valueshould be as close as possible to that of eutectic SnPb (24.7ppm/°C).

• The underfill wetting rate is expressed by the formula !*(cos")/2#, where ! is the surface tension air/liquid resin, " is theunderfill contact angle and # is the resin viscosity (measuredby DTMA). It is then deduced that the lower the viscosity andthe contact angle, the higher the surface tension, and the shorterthe filling time (apart from the chip stand off and the edgesize). The low " is also required for the best underfill adhe-sion.

• The Glass Transition Temperature (Tg), above which the ma-terial has a transition from a cured and vitreous behavior toan elasto-plastic one, is an intrinsic material property that isalso dependant on the applied curing profile. Since the tem-peratures during the reflows that follow underfill curing (ball-ing, balling rework, various SMT operations) will surely ex-ceed the Tg, causing softening of the material, it is clear that ahigher Tg minimizes the amount of resin re-softening. A Tg of150° C is considered an optimum value.

A

B

D

C

Solder Extrusions and Underfill Delaminations: a remarkable Flip Chip Qualification Experience

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© International Microelectronics And Packaging Society 55

• To minimize any electro-migration or corrosion failures, theunderfill moisture resistance must be very high. Water ab-sorption also depends on the fillet thickness. The maximumallowed value, reported in the literature (3rd class of JEDEC J-STD-020), is 0.3% weight gain.

• Young’s Modulus (E) represents the stress-strain ratio. It isan intrinsic material property, indicating the capability to bearan applied stress without an exaggerated strain in the elasticfield. For a given stress, the higher the value of E, the stron-ger the mechanical resistance to elastic stresses and the lowerthe induced deformation. The absorption and redistributioncapability of thermal stresses (high Young’s Modulus value)is also strongly desired to minimize the phenomenon of ther-mal mismatches in expansion or shrinkage.

• On the other hand, pushing the E values too high can stiffenthe structure of the entire FC too much. In the literature sev-eral references indicate 4-10 GigaPascal as the best value4-5.

• Apart from the DRAMs soft error problem, the $ emissioncould damage the chip structure. Some radionuclides containedas impurities in the Pb bulk and generated from the 238U decaychain (Pb being its stable final product), are $ particle emit-ters. Underfill must act to stop the ionizing radiation. Such acapability is related to the material’s density. In Nuclear Phys-ics, it is well known that the mass stopping power of a 0.8 - 8MeV particles is found between 0.5 and 5 mg/cm2. Thus, atypical epoxy resin with a density of 1.2 g/cm3 needs a thick-ness ranging from 4.1 up to 41-µm to block each particle.Therefore, it can be deduced that the underfill density % shouldbe as high as possible.

The material properties of the 5 underfills are listed in Table1. The Elastic Modulus was not measured in absolute value, butit was detected by the E drop at high temperature.

Table 1. Underfills properties.

CTE Tg θ η Moisture ρ Rwk

1 35,9 129,6 35 35 0,27 1,21 No

2 47,7 147,3 47 6,5 0,35 1,43 No

3 18,2 148,8 39 16 0,22 1,79 No 4 42,3 86,5 27 5,5 0,25 1,75 No

5 25,4 74,4 21 6,5 0,12 1,65 Yes

Underfill 1 was the underfill selected for the final evaluationphase. Underfills 4 and 5 failed due to a very low Tg. This condi-tion resulted in their exclusion despite very promising resultsrelated to the wetting rate. Underfill 5, which had the best CTEvalue, also showed very poor results during HAST, probably dueto its reworkability.

Underfill 3 has long been considered the best underfill in thematrix. This is evident by looking at the values in Table 1. Thisunderfill was removed from further evaluation since it showedan intolerable difficulty in flowing (Figure 2 SAM image). The

root cause of the problem was identified as filler separation, andcould not be overcome even by changing the dispense condi-tions. Underfill 2 had a very similar behavior to 1 but was notselected due to a slightly higher tendency to suffer from voids(probably due to the higher "), a fillet granular aspect, and a 35%higher price.

Figure 2. SAM image evaluation of sample.

The fact that underfill 1 was selected for the final trial ap-pears to definitely be a compromise since not all of the values,namely CTE and contact angle, were considered to be very ap-pealing.

5. Testing and Evaluation Phase

Test vehicles underfilled with product 1 were subjected to aprocess flow simulation, summarized in Table 2. After a ther-mal treatment (24 hrs at 120°) to bake out the moisture from thecarriers, a UNIVERSAL GSM™ tool was used to place the 4devices, by applying 2 different no-clean fluxes: the first flux(F1) was dispensed on the site, whereas the second flux (F2), anew epoxy-based flux, required die dipping and would be laterutilized in the project. An Electrovert™ Omniflo 10 was usedfor the reflow soldering operations and great attention was dedi-cated to the thermal profile parameters. A number of sampleswere examined using X-Ray and a GPD™ tool was used to dis-pense all the underfill materials. As in the previous phase, theapplied curing conditions were those recommended from the sup-plier (20 minutes at 150° C). Underfill 1 was dispensed on thetest vehicle, which had been pre-heated to 75-80°C, thereby de-creasing the viscosity and improving the wetting rate7. All thesamples were electrically tested after the UF curing step and in-spected by the C-Scanning Acoustic Microscope. The ballingoperation and the ball rework was performed on each sample.The samples were then subjected to the JEDEC Level 3 precon-

35.947.718.242.3

25.4

129.6147.3148.886.5

74.4

356.5165.5

6.5

0.270.350.220.25

0.12

1.211.431.791.75

1.65

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ditioning (30°C, 60% R.H., 192 hours) and to an additional 5reflows, according to the MCM-L specifications. Again, thesamples were electrically tested and inspected by C-SAM imag-ing, before and after the multiple reflows. HAST tests were ap-plied to several samples. After a confirmation run to verify boththe final process flow and the definitive material choices, thequalification stress tests were started. But, the early results onthe samples immediately showed two types of problems, whichwould detrimentally affect the FC structure reliability. They wereunderfill delamination and the solder extrusions. These effectsare linked to one another and a regression demonstrated thatthey are present in each of the starting 5 underfills.

Table 2. Process flow simulation of test vehicles.

Laminate carrier bake-out Laminate UV Cleaning and chip site flux dispensing

(F1) or Dip chip fluxing (F2) Chip placement and rework (if required)

Chip reflow soldering Pre-encapsulation bake-out Underfill dispense & cure

BGA site flux screening and balls placement BGA balls 1st reflow soldering

BGA Cleaning BGA balls Rework (if required) BGA Balling Attach 2nd reflow

5.1. UF Delaminations: PhenomenonComprehension

After processing the samples, a general delamination trendappeared. All of the following figures show various levels ofdelaminations detected using the C-SAM or by performing elec-trical test, and were confirmed by cross-sectioning the samples.The first hypothesis for the failures was that these underfill de-fects were triggered by the multiple reflows. This is clear fromFigures 3a and 3b, where the same die “A” (F1 flux, 1 underfill)is depicted before and after 7 reflows. Figure 4 shows the crosssection of the area labelled in Figure 3b where it can be seen thata macro-void is under the UF-die passivation delamination.

Figures 3a and 3b. Examination of sample before and after

reflow.Since the bumps are melted during each reflow, their volume

increases and exerts a pressure on the cured underfill. If the ad-hesion between the UF and the die passivation or the solder maskis not excellent, the resulting thermal stresses will find preferredcrack nucleation and propagation points in all the weakly linkedsurfaces such as in the voids and in the contaminated sites. TheUF type (a regression was performed on the other UFs) and theparticular die did not appear to be influential.

Figure 4. Cross section of certain area for furtherexamination.

The same delamination growth has been observed after stressessuch as Pressure Cooking or HAST. If the heat is the energywhich gives rise to the phenomena, the following root causeshave been identified:• Voids in the bulk underfill• No-clean flux residues• Interfaces adhesion

Considering the first option, it is possible to see, in Figure 3a,a number of voids (small black points) already present at the UF-die passivation interface before the multiple reflows propagatethe onset of delamination. The same phenomenon appeared inless defective samples at time zero, containing only micro voidswhich are difficult to see.

Considering the second option, F1 flux contamination wasdetected, even after the pre-underfill bake. This explains manydelamination cases where no defects were previously seen. Actu-ally, Figure 5 presents a B device C-SAM photo before and afterthe 7 reflows. It is evident that at time zero, no defects werepresent.

Figure 5. C-SAM photo of sample before and aftermultiple reflows.

BGA Cleaning

Solder Extrusions and Underfill Delaminations: a remarkable Flip Chip Qualification Experience

The International Journal of Microcircuits and Electronic Packaging, Volume 24, Number 1, First Quarter, 2001 (ISSN 1063-1674)

© International Microelectronics And Packaging Society 57

In this case, the cause of delamination was identified as fluxresidue, although the residue was invisible on the SAM image.Figure 6 shows a die from the same lot as the die in Figure 5 afterpull test. Pimelic Acid crystal residues were found on the die andthe Cu carrier traces were visibly lifted off.

Related to the no-clean flux residues, experiments were con-ducted to evaluate the UF flow speed as a function of the fluxquantity dispensed on the site. For example, doubling the fluxvolume from 5 to 10 µl decreased the average UF speed by 14%in the case of UF 1 and 26% in the case of UF2. This resultdemonstrates that the flux residues play a heavy role in the un-derfill dispense quality and consequently in the reliability.

Figure 6. Illustration of a die after pull test.

Related to the third point, the interfacial adhesion problem isalso evident. Furthermore, a drop in the underfill’s elastic modu-lus (54 times lower) was recorded by the DTMA (see Figure 7) inthe temperature range of 160°-220°C. This is a common behav-ior for all the epoxies, which were studied, and it demonstratesthat while in the reflow profile melting zone, each UF becomestremendously ductile and not as mechanically resistant to anydeformation.

Figure 7. DTMA measurements.

It can be deduced that, in this condition, the delaminationnucleation is easier. Nevertheless, the results of a regression analy-sis indicated that underfill 1 maintained the highest E value at220°C compared to the other investigated UFs.

5.2. Amoeba: Phenomenon ComprehensionThe second severe problem is characterized by solder extru-

sion or solder flow-out, called in this context, “Amoeba” (since itresembles the protozoan in shape).

Amoeba can be considered a sort of delamination sub-set, inthe sense that having underfill delamination is a condition suffi-cient but not necessary to have Amoeba8. Actually, a number ofcases with big voids and delamination without Amoeba have beenidentified (see Figure 8, where the void connects two joints with-out any solder escape). The intrinsic causes, evident through fail-ure analysis, are the same as for the delamination phenomenon.

Figure 8. Void connecting two joints without solder escape.

In addition, a phenomenon dependency on the balling ther-mal profile parameters has been noted. The shorter the meltingdwell time, the fewer the number of Amoeba cases are. It hasalso been demonstrated, that only one reflow is enough to pro-mote Amoeba. When the temperature approaches 200°C, themelted SnPb solder exercises a significant pressure on the curedUF interfaces. In some cases, the stress intensity factor that re-sults is so high during the melt dwell time that the solder alloy isable to flow out from the original site. The higher the defectiverate at a point, the higher the probability of seeing the phenom-enon. The Amoeba appears between either the die passivation-UF interface (Figure 9) or the solder mask-UF interface (Figure10).

Figure 9. Amoeba between die passivation and UFinterface.

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Figure 10. Amoeba between solder mask and UF interface.

The Amoeba danger shown in Figure 11 is quite clear. Anelectrical short can be potentially formed between twoneighbouring joints. Furthermore, it has been demonstrated thatthe presence of “partial” Amoeba typically decreases the electri-cal resistance values (the conductor section increasing).

Figure 11. Illustration of potential electrical short.

There have been registered cases in which the underfill closesitself after the SnPb escape, thereby creating Sn-Pb islands in theUF matrix (Figure 12).

Figure 12. SnPb islands formation in UF matrix.

The Amoeba phenomenon has mainly shown repeatability withthe Polyimide passivated device. This appears to be due to thehigher thermal stress concentration in the Ni-based UBM/Polyimide corner, where many cracks have been recorded (Fig-ure 13).

Figure 13. Cracks recorded.

5.3. Corrective Actions

A massive design of experiment activity supported the resolu-tion of these problems. It was immediately clear that the rootcauses of both the delamination and Amoeba are common. Fromthis point onward, all the effort was focused in the direction ofimproving the mechanical strength of the interfaces, and reduc-ing the flux residue.

Firstly, an investigation into general site cleanliness demon-strated that, by inserting a chip site ultraviolet-ozone cleaningstep before the placement operation, the UF contact angle can bedecreased. This, thereby, improves the UF wettability and conse-quently the adhesion, even in the presence of no-clean flux resi-dues. In order to minimize the no-clean flux residues, the correc-tive action initially involved modifications to the reflow profile.A dedicated D.O.E. showed that larger dwell times and lower O2content minimized the residues.

Furthermore, at the last moment it was decided that a newlydeveloped and already mentioned epoxy-based flux, F2, shouldbe added to the matrix. The reason for doing this is that the F2residues, left behind after soldering operations, are designed tochemically cross-link with the standard UF residues. The resultsshowed a definite, overall adhesion increase, confirming that thiswas an appropriate choice. Both of the fluxes were then carriedon in the qualification run.

For the underfill, different curing profiles were investi-gated 9,10, with the one selected as best being 3 hours at 150°C.Figure 14 shows the kinetics of curing performed at 150°C byDTMA. It is evident from the Young’s Modulus curve (the blackone) that the 20 minutes suggested by the vendor is definitely notenough time to adequately cure the underfill, with the resultingcure percentage being below 70%. Actually, by using a cure pro-file of 3 hours at 150°C, the cure percentage was increased toover 99%.

Solder Extrusions and Underfill Delaminations: a remarkable Flip Chip Qualification Experience

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Figure 14. Curing kinetics performed at 150°C.

These results refer to the mechanical cure of the underfill(Modulus curve). Of course, a Differential Scanning Calorim-eter confirmed that the chemical cure, identified by the simpleepoxy chain chemical reaction, is 20 minutes at 150°C. Further-more, the Tg of the new cured samples was demonstrated to ex-ceed the 150°C, showing a favorable 30°C increase.

It is also well known that the longer the time to fully cure UFmaterials, the lower the thermal stress and the better the physicaland mechanical properties6.

It appeared, on a statistically significant number of samples,that these findings solved the delaminations and the Amoebaproblem, due to an increase in the mechanical adhesion in theUF interfaces.

The supplier of UF 1agreed with this data after performingseveral additional internal tests on their product. They confirmedthat, by simply increasing the curing time from 20 minutes to 2hours at 150°C, the UF adhesion strength increased by an aver-age of 15%, and in certain conditions increased by as much aseven of 30%.

5.4. QualificationThe tests applied to 230 samples with each flux were: High

Thermal Shock (120°C, 1000 hrs), Deep Thermal Cycle (-40/115°C 1000 cycles), Deep Thermal Cycle (-25/115°C 1000 cycles),Thermal Cycle (0/100°C 1000 cycles), Pressure Cooking Test(121°C, 100%RH, 2atm 96hrs) and HAST.

The qualification stress tests have confirmed that the correc-tive actions that were implemented to eliminate delaminationand Amoeba phenomena were successful.

6. Conclusions

The most detrimental defects encountered during this mas-sive flip chip qualification project have been presented.

Underfill delaminations and Amoeba manifest themselves aftermultiple reflows and have the same causes. UF delamination andAmoeba affected bumps are the weak point in flip chip technol-ogy and induce the early failures of the assembly.

In this specific case, the problem was solved with the follow-ing actions:• The best die site cleanliness was pursued.• Underfill was studied to understand the properties related to

improving its adhesion to the FC interfaces. The best choiceswere selected.

• The optimal curing conditions were obtained.• The optimal multiple reflow thermal profile was defined.• The no-clean flux residues were minimized.• New high performance dedicated flux material was used.

The same methodology is being used in new projects that theCelestica Italia Development Group is currently working on, suchas reworkable underfills and no-flow fluxing underfills.

Acknowledgments

The authors would like to thank the entire team, which per-formed the trials and developed the process.

References

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3. K. Gilleo, “The Chemistry & Physics of Underfill”, NEPCONWest 1998, No. 1, pp. 280-292, 1998.

4. S.F. Popelar, “A Parametric Study of Flip Chip ReliabilityBased on Solder Fatigue Modeling: Part II – Flip Chip onOrganic”, Proceedings of the 1998 International Symposiumon Microelectronics, IMAPS ‘98 pp. 497-504, 1998.

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6. J.H. Lau, and C. Chang, “How to Select Underfill Materialsfor Solder Bumped Flip Chips on Low Cost Substrates”, TheInternational Journal of Microcircuits and Electronic Pack-aging, Vol. 22, No. 1, 1st Quarter, 1999.

7. C.Y. Huang, K. Srihari and P. Borgesen “Optimization of theSubstrate Preheat Temperature for the Encapsulation of FlipChip Devices”, The International Journal of Advanced Manu-facturing Technology, 2000.

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