EDN Design Ideas 1999

Y ou can use a simple mC to continu-ously program an audio DAC so thatit operates in a 20-bit resolution

mode (Figure 1). After power-on, thePCM1710 DS DAC (Burr-BrownCorp, www.burr-brown.com) op-erates in its default 16-bit resolu-tion mode. Switching to its 20-bit resolu-tion mode requires supplying the converterwith a control word using its three-wire se-rial digital interface (SDI). A risk exists forusing this converter at a resolution of 20bits in a transmission system that shouldwork 24 hours a day, seven days a week withno, or only occasional, supervision. A dis-turbance can cause reprogramming of theconverter and cause it to revert to its defaultsettings. The circuit in Figure 1 eliminatesthis possibility by repeatedly reprogram-ming the DAC. The circuit uses the SDI tocontinuously supply three programmingwords, which define the converter’s state ofoperation, to the DAC.

The reprogramming circuitry, whichuses a popular AT89C2051 mC (Atmel,www.atmel.com), has few components and

mmC reprograms audio DAC via serial interfaceLukasz Sliwczynski, University of Mining and Metallurgy, Institute of Electronics, Cracow, Poland

A simple mmC-based circuit (a) continuously reprograms the PCM1710 audio DAC for a resolution of20 bits. The mmC sends 1 byte of code after each RST pulse (b).

ideasdesign

mC reprograms audio DAC via serial interface..........................................................107

Calibrated trim tool tweaks multiturn pots ..............................................108

Off-the-shelf watchdog serves in a pinch ......................................................110

Novel circuit controls ac power ................112

Two AA cells powerstep-down regulator ..................................114

Temperature controller keeps IR detector at 88K ........................................114

Flyback circuit provides isolated power conversion ........................................118

CLK(12 MHz)

LRCIN(46.875 kHz)

XTAL1

AT89C2051

RST

P1.7

P1.0 TO 6

RxD

TxD

P3.2

MD

MC

ML

26

27

28

2

3

6

RC COMPONENTSGENERATE

~2-mSEC RST PULSE

LRCIN

XTI

PCM1710

22k5V

IC1B

IC1A

74HCT02

5

1

19MUTE

1 nF

ATTENUATIONVALUE

12 TO 18

1

5

F igure 1

Edited by Bill Travis and Anne Watson Swager

January 7, 1999 | edn 107www.ednmag.com

(a)

(b)

2 mSEC/DIV

ideasdesign

M any analog circuits contain mul-titurn trimming potentiometerswhose settings you may need to

change during maintenance or calibration.Also, some instruments have panel-

mounted potentiometers that may needperiodic adjustments. After disturbing asetting by more than one or two turns, itbecomes difficult or impossible to restorethe original setting. The usual method is to

measure the resistance between the wiperand one of the ends of the potentiometerbefore disturbing the setting and then toreadjust to the same setting if and whennecessary. However, this method is incon-

Calibrated trim tool tweaks multiturn potsSanjay Chendvankar, Tata Institute, Mumbai, India

is power-efficient (Figure 1a). Because anymC system is also vulnerable to externaldisturbances, it’s best to reset the mC repet-itively. The circuit uses the LRCIN signal toreset the mC and invoke the programmingprocedure. The LRCIN signal also switch-es digital-audio words between the left andright channels of the converter. Thus, themC takes less time to execute the programthan the period of the LRCIN signal. Thesampling rate is 46.875 kHz, so the periodof the LRCIN signal is approximately 21msec. The circuit must devote some of thistime to properly resetting the mC.

The SDI of the PCM1710 comprises data(MD), clock (MC), and latch (ML) lines.To drive this SDI, the serial port of the mCoperates in the default mode, Mode 0. Al-though this mode of operation is rare inmany applications, it is convenient in thiscase because, apart from sending serial datavia its RxD pin (P3.0), the serial clock isavailable on the TxD pin (P3.1). Thus, theRxD line directly serves as the MD signal,and the inverted TxD line serves as the MCsignal. The program generates the thirdSDI line (ML). Sending 3 bytes of data tothe DAC requires at least 36 msec, assum-ing a 12-MHz clock from the DAC clockand omitting the time that the internal re-set procedure of the mC consumes. Thus,you can transmit 1 byte for one programexecution, which occupies about 17 msec.Assuming that 2 msec is enough time forthe mC to properly reset, the entire pro-gram should easily fit into the allowable 21-msec frame. The low time of RST is ap-proximately 19 msec (Figure 1b).

This interface circuit relies on the factthat after you apply the RST signal to themC, some internal registers do not changetheir values, and others reset to 00H. List-ing 1 is the corresponding assembler code.(You can download this listing from EDN’s

web site, www.ednmag.com. At the regis-tered-user area, go into the Software Cen-ter to download the file from DI-SIG,#2312.) After each RST pulse, the mC sends1 byte of code; the mC sends the same byteevery third RST pulse. The circuit uses reg-ister R

Oto temporarily save the value of the

next word to send because the mC resetdoes not affect this register. The circuit alsouses one bit-addressable memory location,designated FLAG (20H), to switch between

bytes to send. Port P1 supplies the programwith the attenuation value on pins P1.0 toP1.6 (from MSB to LSB) and supplies theMUTE signal on pin P1.7. The circuitstores the proper value of the Mode 1 con-trol word in the program-memory area ofthe mC at locations 60H (MUTE deassert-ed) and E0H (MUTE asserted). (DI #2312)

LISTING 1—PCM1710 DAC ASSEMBLER CODE

108 edn | January 7, 1999 www.ednmag.com

To Vote For This Design,Circle No. 427

ideasdesign

The performance of the watchdogcircuit in Figure 1 may not matchthat of a dedicated watchdog circuit,

but this circuit is helpful when the onlywatchdog in the lab doesn’t meet your de-sign’s temperature requirement and when

you are in a hurry to finish a prototype.The circuit operates on a simple princi-

ple. When digital activity occurs on the in-

Off-the-shelf watchdog serves in a pinchGiovanni Romeo, Istituto Nazionale di Geofisica, Roma, Italy

A charge pump comprising D1, D2, C1, and C2 inhibits a three-gate oscillator when input activity exists. After 40 msec without input activity, the oscilla-tor starts running and produces a reset signal.

IC1A IC1B IC1C IC1D

IC1FIC1E

C3

R3

R2 40691M

C1

1N4148

1N4148

5M D1

D2

R1C2

1N4148

1 nF

INPUT

0.1 mF

1 2 3 4 5 6 9 8

1M1 mF

1M

RESET HIGH

RESET LOW

11 10 13 12

venient and sometimes impossi-ble, such as when the trimmer ismounted on a panel, for example.The simple tool in Figure 1 comesin handy in such situations.

You construct the tool bymechanically coupling the trim-ming tool’s shaft to the shaft of ahigh-quality, multiturn, wire-wound potentiometer (P

1). The

wiper and one of the end termi-nals of this potentiometer connectto a DMM operating in resistance-measurement mode. The toggleswitch, S

1, selects one of the two

available end terminals. Beforedisturbing the setting of a multi-turn potentiometer in a circuit,you rotate the trim tool to theendpoint of P

1’s rotation span in

the opposite direction to that in which youintend to adjust the trimming poten-tiometer. Set the selector switch such thatthe DMM reads zero (or near-zero) resis-tance. Then, you rotate the trim tool by

firmly holding P1

with one hand and turnthe trimming potentiometer to the desiredsetting. The corresponding P

1resistance

value on the DMM, along with S1’s posi-

tion, tells you whether the tool rotates

clockwise or counterclockwise.You record these data for futurereference.

If you wish to restore the poten-tiometer’s original position, youadjust P

1to the recorded value with

the same position of S1

by turningthe trim tool in the opposite direc-tion until the DMM reads zero re-sistance. This position is the origi-nal setting of the potentiometer.The resistance value of P

1is not

critical. However, it’s better to se-lect low values to obtain higher res-olution on the DMM. Also, a sin-gle range of the DMM shouldcover the value. This prototypeuses 1 kV. You can improve thetool by replacing P

1with a minia-

ture bidirectional optical shaft en-coder and connecting its output to anup/down counter. (DI #2308)

This “tool with a memory” allows you to accurately restore theoriginal setting of a multiturn potentiometer.

MULTITURNWIRE-WOUND POTENTIOMETER

DMM

(IN RESISTANCE-MEASUREMENT MODE)

CW

S1MECHANICALCOUPLING

TRIM TOOL

TIP FORTURNINGTRIMMERSCREW

CCW

P1 (1k)

F igure 1

F igure 1



The simple and inexpensive power-control circuit in Figure 1 uses a read-ily available fan regulator with built-in

phase control. Such fan regula-tors are limited to ap-proximately 100W. Thecircuit in Figure 1 addstwo SCRs and a few compo-nents to turn the humble fanregulator into a mighty powercontroller. The fan regulatoroperates with a nominal load of10 to 25W through a lamp,which also gives a power-levelindication. The 1:1:1 pulsetransformer completes the cir-cuit. The transformer’s sec-

ondary windings fire the back-to-backSCRs, which then control a load of 1000 to3000W.You can house the circuit in any in-

sulated box. You should mount the SCRson heat sinks. R

1, D

1and R

2, D

2limit the

gate current and prevent the application ofreverse voltage between gateand cathode. Figure 2 showsconstruction details of the pro-totype. (DI #2310)

Novel circuit controls ac powerNarendra Paranjape, Tata Chemicals Ltd, Mithapur, India

A couple of thyristors, a pulse transformer, and two diodes transform a humble 100W fan regulator into a high-power ac controller.

An easy-to-build power con-troller works with an inexpen-sive fan regulator to control1000 to 3000W.

240V, 50 OR 60 Hz

LOAD1 TO 3 kW

LAMP10 TO 25W

FANREGULATOR

NEUTRAL

PULSETRANS-FORMER

R1

R2

1001W

1001W

D2

D1

1N4007

1N4007

SCR1

SCR2


F igure 2

put, a charge pump comprising C1, D

1, D

2,

and C2keeps C

2charged. R

1is the discharge

resistor for C2. IC

1Adetects the charge lev-

el through R2. A charged condition inhibits

the three-gate oscillator comprising IC1B

,IC

1C, and IC

1D, and the active-high reset-

high output stays low.When the voltage at the input of IC

1A

drops below the CMOS threshold, the os-cillator starts working and produces a

square wave. The high time of the reset-high output resets the mP under control,which must start the activity (and activatethe watchdog input) before the end of thelow time. R

3and C

3essentially control the

high and low times, which have almost thesame value.

Although this design monitors an RS-232C line, you can use the circuit to mon-itor a digital level.When monitoring an RS-

232C line with the values in Figure 1, thewatchdog starts resetting 40 msec after de-tecting no activity and requires less than 20msec to inhibit the oscillator after input ac-tivity resumes. (DI #2311)

ideasdesign

F igure 1



DC/DC conversion is particularlychallenging when both the input andoutput voltages are low. Step-up ICs

that operate with inputs lower than 1V areavailable, but step-down ICs that accept in-put voltages near 2V are not. Thus, pro-viding efficient power for the low-voltageCPU in a handheld product can be a prob-lem if the power source is a two-cellAA battery. The battery’s output candrop to 1.8V as the battery discharges. InFigure 1, the upper switch-mode dc/dcconverter (IC

1) generates more than 600

mA at 1.5V, from a two-AA-cell input thatvaries from 3.4 to 1.8V. The 3.3V rail thatpowers this step-down controller comesfrom a high-current, synchronous-rectifiedboost controller (IC

3), which also provides

power for external logic and the CPU’s I/Oblocks. IC

1receives 3.3V bias, but power for

the 1.5V output comes directly from thebattery.

Q2, D

2, and a SOT-23 reset IC (IC

2) force

the switching power MOSFET (Q1) off

when the 3.3V rail is too low to properlyoperate IC

1. Without those components,

the conditions at power-up (during whichbattery voltage is present but 3.3V are mo-mentarily absent, pulling Q

1’s gate low)

may cause the 1.5V output to overshoot tothe battery voltage. The 1.5V output’sbuck-conversion efficiency (approximate-ly 85%) is reasonably good for the circuit’sextra-small components: a three-pin SOT-23 power MOSFET and 5-mm-diametersurface-mount inductors. For the 3.3Voutput, IC

3’s on-chip synchronous rectifi-

cation yields a boost efficiency higher than90%. (DI #2302)

Two AA cells power step-down regulatorLen Sherman, Maxim Integrated Products, Sunnyvale, CA

Powered by the 3.3V boost controller IC3, this step-down controller (IC1) generates 1.5V from inputsas low as 1.8V.

1.5V600-mAOUTPUT

3.3V200-mAOUTPUT

L1 100 mHSUMIDA CD54-101

L2 10 mHSUMIDA CD54-100

C1 100 mF

C3 0.1 mF

C2 100 mF

C4 100 mF

R5 10

R6 101k

R7 61.9k

C5 0.1 mF

C6 0.1mF

R1 20k

R2 130k

R3 300k

C7 0.1 mF

R4 470k

Q1NDS8434A

Q2BSS84

D2MBR0520

D3MBR0520

D11N5817

IC1MAX1627

IC2MAX6311

IC3MAX1706

VCC

+ +

+

+

INPUT TWO AACELLS

7 1

EXT OUT

NC

FB2

V+

CS 6

5SHDN1.5VON

3.3VON

3

REF GND

4

RESET GND1

8

2

45

RSTIN1

RSTIN2

3

1315

ONA

2

3LBN

REF

LX 16POUT

CLK/SEL

OUT

11

14

6

ONB

7

FBPGNDGND

4 1 8 10 5 12

Temperature controller keeps IR detector at 888KJerry Penegor, Space Sciences Laboratory, University of California—Berkeley

S ensitive infrared array detec-tors must operate at a low tempera-ture to avoid thermally generated

dark current throughout the photocon-ductive elements. This requirement is

particularly true for SiAs array detectors,which need cooling to near liquid-heli-um temperatures. Furthermore, the sen-sitivity of these detectors can be temper-ature-dependent. The optimal operating

temperature for a long-wavelength IRcamera is about 88K. This temperaturemust remain constant despite changes inthe radiation level falling on the array, inthe liquid helium level as it boils away, and

F igure 1


ideasdesign


A four-wire silicon diode helps to maintain an IR camera’s temperature at approximately 88K. One pair of #38 AWG wires forward-biases the diodewith a fixed 10 mA of drive current. A second pair of wires provides for a Kelvin-connection measurement of the diode’s forward voltage drop, whichis a nonlinear function of temperature.

in the orientation of the Dewar flask.To measure and control these low tem-

peratures, the circuit in Figure 1 uses afour-wire silicon diode. One pair of #38AWG wire forward-biases the diode with afixed 10 mA of drive current. The secondpair of wires provides for Kelvin-connec-tion measurement of the forward-voltagedrop,V

F, which is a very nonlinear function

of temperature. Around 88K, the VF

is 1.5Vand changes about –35 mV/8K. To accu-rately measure the array temperature re-quires mounting the diode as close as pos-sible to the SiAs array in its ceramic chipcarrier.

The back of this carrier is spring-loadedagainst an oxygen-free, high-conductivitycopper plug onto which a 500V wire-wound resistor attaches. A heavy copperbraid also connects the plug to the liquid-helium reservoir. Good thermal contact be-tween the power resistor and the chip car-rier ensures that a simple circuit can con-trol the temperature. The simple pro-portional-integral servo circuit in Figure1 can control array temperature to ±5 m8Kover an 8 to 128K range. Slewing the array

to a new setpoint temperature takes ap-proximately 30 sec.

Special low-thermal-conductivity steelcoax cable goes through hermetic connec-tors in the vacuum Dewar flask wall. Thiscable makes all electrical connections to thecooled camera. The schematic shows nolow-leakage unity-gain buffers that isolatethe voltages at the sensor diode’s anode andcathode (+ and –T) from all the meters andcircuitry that operate at room temperature.

Op amp IC1

is a differential receiver forthe + and –T voltages and has a gain of –3.Because –3 times the coldest expected V

F

is about –4.8V, a stable 5V reference, IC3,

supplies the voltage at the potentiometerfor the temperature setpoint over the nec-essary range. The setpoint-monitor outputhas an attenuation of 3, so you can see thesetpoint voltage directly on any meter.

When the sensor and setpoint voltagesare in balance, the noninverting input toIC

2Ais 0V. IC

2Aamplifies any imbalance.

IC2B

sets the frequency response of the ser-vo with a zero at a corresponding time con-stant of 10 sec. That is, IC

2B’s gain term of

10 is constant for any ac disturbances but

is high for dc error. Mounting the resistorsand capacitors that set the servo time con-stant on a seven-position header allows youto easily add component values when thecontroller is mounted on the Dewar flask.The output diode ensures that positive-only current goes to the power resistor onthe heat sink; power off is 0V, and no neg-ative currents can flow. (Negative currentdoes not cool the power resistor.) The op-tional 500V series resistor in series with theoutput diode provides additional currentlimiting for IC

2B.

One condition to guard against is a bro-ken or disconnected sense diode that sendsthe temperature controller into full-pow-er application. IC

2Dsenses temperatures

that are too cold—excessive negative volt-age from IC—to be valid. The 50-kV po-tentiometer sets the “too-cold”threshold atapproximately –5V. If the circuit detects atoo-cold condition, IC

2Dturns on Q

1,

which shorts the output and sinks the out-put current within Q

1. (DI #2296)

TEMP

2TEMP

215V

215V

15V

+

+

2

2

+

2

500

10k

10k

30.1k

71

82

36

4

IC1

OP-O7

REF-O2A

IC2CIC3

IC2D

+

2IC2A

+

2IC2B

Q1

0.1

67

5

10

98

10k

20k

10k

50k

4

2

6SET-POINT

1 nF

"TOO-COLD"THRESHOLD

47k

4.7M

2N3904

100

100

1025V

1025V

15V

215V

RED

BLACK

YELLOW

1N4148A

500

0.1

1112

1314

1k470k

100k

1k

0.1

3

2

41

1k

0.1

15V

215V

LM324AN

22k

4.7MDIP HEADER

115V

20k

0.1

30.1k

LAB SET

VIRTUALGROUND

1N4148A

0.1

0

SETPOINTMONITOR

NOTE:ALL CAPACITORS ARE IN MICROFARADS UNLESS OTHERWISE SPECIFIED.

+

+

5V

11002

132


ideasdesign

F igure 1

116 edn | January 7, 1999www.ednmag.com

Acommon requirement in telecom-munications systems is to convert anunregulated 48V line to an isolated,

accurate dc supply voltage. The circuit inFigure 1 provides a 5V, 15W output. Thecircuit uses a UCC3809 primary-side con-troller, which can also control other sin-gle-ended converters. The topology usespeak-current-mode control with a fixed-frequency oscillator. The design is cost-ef-ficient, because it assumes that compen-sation of the voltage loop occurs on thesecondary side, where you would place theerror amplifier and reference anyway. Byeliminating a primary-side amplifier, youreduce system cost and complexity.

The feedback signal from the secondarycomes from the UC3965 precision refer-

ence. In addition to a low-offset error am-plifier, this IC also contains an optocou-pler driver for simplicity in designing iso-lated converters. An undervoltage-lockoutcircuit provides a controlled start-up tran-sient. The design in Figure 1 uses discon-tinuous-conduction mode (in which theflyback transformer undergoes completedemagnetization in every cycle), withmaximum duty cycle set to 50%. Contin-uous-mode flyback circuits (in which theflyback transformer operates in continu-ous inductor-current mode) have a right-half-plane zero that limits the controlbandwidth, as opposed to discontinuous-mode flybacks that do not restrict band-width.

Both ICs operate in either mode; the

choice of mode depends on the power-supply requirements.You can easily bufferthe primary-side oscillator with an emit-ter follower to provide slope compensa-tion for designs requiring duty cycles be-yond 50%. Note, however, that you havethe option of programming a duty-cycleclamp to 50% or less, which can save costby eliminating several slope-compensa-tion components. The maximum-duty-cycle clamp in the UCC3809 is complete-ly programmable by selecting the tworesistors connected to pins 3 and 4. (DI#2288)

Flyback circuit provides isolated power conversionPhilip Cooke, Unitrode Corp, Merrimack, NH

A discontinuous-mode flyback regulator provides an isolated, regulated supply, and saves cost by cutting compensation components.

MBR1635

7:1

PC30EI19

98 mHPRIMARY

2200 mF6.3V

15 mV120 mF100V

15V

1 mF

1 mF

+

48V

1.74k

+

1 1

5V

UCC38098 7 6 5

1 2 3 4

0.022 mF

1000 pF

1.43k

2N2222A

14.3k

0.1 mF

100 pF

1 nF

EACH7.15k

10

4

5

6

3

2

11k

4.02k

4.02k

750

1

2

3

4

8

7

6

5

MOC8102

0.1 mF

22.6k

22.6k150k

UC3965 220 pF

0.0022 mF

0.2

1N4148

1 mF++

IRF630


ideasdesign

F igure 1


When it comes to implementing afast FIR filter, current RISC mPscan compete with DSP mPs. The

FIR algorithm continuously implementsthe following equation:N=n21 Out=Sum[in(t[-]n)coeff(n)] N=0,where N is the number of taps, or thenumber of multiply-accumulate (MAC)instructions of the filter.

Using a delay line to implement thisequation is common and involves theability to manage a circular buffer. Spe-cialized DSP mPs have can manage thistask in hardware, and general-purposemPs have to implement the buffer man-agement in software. As you might ex-pect, the software implementation is sig-nificantly slower than the hardware one.However, modern RISC mPs operating athigh speeds and with features lacking inprevious generations of general-purpose mPs can compete inprice and performance at executing thesetypes of algorithms.

For example, consider the following al-gorithm, which you can implement usingthe V832 RISC processor (NEC Elec-tronics, www.el.nec.com), which runs at144 MHz. This mP features large internal

memories, the ability to execute instruc-tions from internal memory in one clockcycle, and the ability to execute one MACinstruction in one clock cycle. The algo-rithm is not new, but it takes advantageof these features.

The algorithm runs linearly with noloops and implements the circular bufferwith the addition of load/store instruc-tions. Because the V832 is a RISC proces-sor, arithmetic operations can take placeonly between registers. When a new sam-ple is available, data loads from memoryinto the registers; the algorithm operates

on the data and thenstores it back in mem-ory. The trick is tostore the data backinto the memory butshifted by one posi-tion. For the simplecase of a four-tap fil-ter, the algorithmlooks like Figure 1.

For each tap, theprocessor needs to ex-ecute only ld.h (loadthe sample into theregister), maci (multi-ply-accumulate im-mediate, in which theimmediate value is thecoefficient), and st.h(store the registerback into the memo-

ry according to Figure 1).Listing 1 comprises sample

code for a four-tap FIR filter.(You can download this listingfrom EDN’s web site, www.ed-nmag.com. At the registered-user area, go into the SoftwareCenter to download the filefrom DI-SIG, #2313.) The in-struction arrangement mini-mizes the dependencies in-herent in a pipeline-based mP.The next time the program

executes, all of the samples are in the rightposition, assuming that the ADC inter-rupt routine writes the new sample intoM1 before calling the filter routine. Re-gardless of the number of taps, the pro-gram takes three clock cycles per tap,which in the case of the V832 translatesinto 21 nsec/tap and occupies 3N mem-ory locations. (DI #2313).

RISC mmP implements fast FIR filterSorin Zarnescu, NEC Electronics, Santa Clara, CA

The trick to the RISC-mmP FIR algorithm is to store the databack into a memory location that’s shifted by one position.

NEW SAMPLE

NEWEST DATA

OLDEST DATA (DISCARD)

R1

R2

R3

R4

MEM1

MEM2

MEM3

MEM4

LISTING 1—RISC-mP FAST-FIR ROUTINE

www.ednmag.com


ideasdesign

RISC mP implements fast FIR filter ..........119

Simple algorithm transforms filtercoefficients ....................................................120

Door/window sensor resiststampering ......................................................120

Use a trick to count scope events ............122

A primer on binary-arithmetic rounding ........................................................124

Light powers isolation amplifier ..............128

Low-cost feedback circuit boostsefficiency ........................................................130


F igure 1

January 21, 1999 | edn 119

ideasdesign

Door/window sensor resists tamperingPaul Nocella, Q Research, Brookline, NH

The simple, inexpensive circuit inFigure 1 detects a failure (or delib-erate tampering) on lines connected

to normally closed switch sensors. For ex-ample, common door interlocks anddoor/window sensors consist of normal-

ly open or normally closed magnetic reedswitches. Depending on the monitoringconfiguration, an open or short on a linemay go undetected, thus preventingalarm activation. Embedding a resistor ina normally closed sensor and using bipo-

lar dc power supplies produces the bal-anced configuration in Figure 1. A shortor open on a line (or sensor activation)produces a net positive or negative volt-age at the input of the Q1-Q2 pair.

A positive-voltage imbalance turns Q1

To synthesize infinite-impulse-re-sponse (IIR)-filter functions, ex-pressed as H(Z), you common-

ly use analog prototype-filterfunctions, expressed as H(s), usingthe bilinear-z transform. This operationentails some algebraic complexity in cal-culating the filter coefficients. The simplealgorithm shown here transforms theprototype-filter coefficients (W

0, W

1, W

2)

to the IIR digital-filter coefficients (U0,

U1, U2). These coefficients transformfrom the s (analog) domain to the z (dig-ital) domain as:

The filter conventions are:

where the numerator and denominatorpolynomials undergo independent trans-formation. The matrix equations are

where

and, for first-order filters,

These equations assume that the pro-totype filter is normalized with respect tothe sampling frequency, f

S. For example,

design a second-order Butterworth uni-ty-gain, lowpass IIR filter with cutoff fre-quency, fC,=100 Hz, and sampling rate,fS=1000 Hz. First, you use CW to fre-quency-scale the Butterworth prototype(in normalized form, C

W=1). The ex-

pression for CW

is

The prototype filter is thus

Now, calculate the IIR coefficients usingthe transform in equations 1 and 2:

Figure 1 gives the filter’s flow diagram.(DI #2287).

Simple algorithm transforms filter coefficientsFrank Vitaljic, Bellingham, WA

You combine biquad sections in cascade to form high-order IIR digital filters.

Figure 1


[ ] [ ] , UUUM WWW T210

1T210

1=

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¼¼–¼

1–01

111

M

1½–¼

2–0½

1½¼

M 1–

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11M

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.sec/rad649839.0)1.0tan(2

f

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π=

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;

1056.0

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(2)

02DI.QXD 1/11/99 4:09 PM Page 2

ideasdesign

One advantage digital storageoscilloscopes (DSOs) have overanalog scopes is trace persistence.

You can easily see infrequent waveformfeatures using a scope in infinite-persis-tence mode. However, the frequency ofthese features relative to that of a “nor-mal” signal can sometimes be less thanobvious. You may wonder, does thatglitch appear 10% or only 1% of thetime? And how often does that shortclock cycle occur? When you take tracenoise into account, even a color-gradeddisplay does not directly or accuratelygive the information. A histogram is the

most accurate way to give the informa-tion, but it requires time and expertise.The following hint provides a quick wayto determine, using a DSO, how ofteneach of two waveforms occurs.

First, use a standard nonaveragingmode to find the voltages of the two statesat a fixed point in time (V

1and V

2). Now,

turn averaging on using a large numberof averages. After the trace settles, mea-sure the average level(V

A). The percent-

age of time the signal at V2 is:

The accuracy of your answer dependson the accuracy of your V1, V2, and VA

measurements. To increase the accuracyof VA, simply increase the number of av-erages on the scope. If you can use yourDSO’s advanced triggering capabilities totrigger on only one waveform, then youcan use the DSO’s averaging mode tomake more accurate measurements of V

1,

V2, or both. (DI #2298).

Use a trick to count scope eventsAllen Montijo, Hewlett-Packard, Colorado Springs, CO


%.100VV

VV

12

1A ×1

1

Normally closed sensor pairs form the detectors in a tamper-resistant and foolproof window/door security system.

Figure 1

on; a negative-voltage imbalance turns Q2

on. The back-to-back clamping action ofthe base-emitter junctions of Q

1and Q

2

protects the transistors from excessive re-verse VBE voltages. The clamping pre-vents intrinsic base-emitter zener break-down. R3 limits the input current to Q1

and Q2 in the event of a line short. Thecollectors of Q1 and Q2 form a wired-ORconfiguration that turns Q3 on by pullingits base toward ground. Q

3provides gate

current to trigger the alarm, SCR Q4,

which can handle several hundred mil-

liamperes. Q4 can drive a variety of alarm

indicators, including LEDs, piezoelectricbuzzers, or relays that control high-pow-er alarms.

It’s easy to add monitoring locations,simply by adding sensors in pairs andreplicating the Q1-Q2 circuit configura-tion, including the wired-OR connectionto R5. With power-supply voltages of±5V, worst-case resistor tolerances of±5% and a 2.5% supply imbalance do notcause Q

1or Q

2to turn on. The ±5V sup-

plies should rise approximately simulta-

neously; otherwise, a net voltage imbal-ance would appear at the input of Q

1and

Q2, resulting in alarm activation. Mo-

mentarily opening S3

resets Q4

by inter-rupting its anode current. C

2 provides a

small time delay to allow the voltage atthe input of Q1 and Q2 to stabilize beforeenabling Q3. C1, C3, and C4 prevent strayac pickup or transients from triggeringQ4. (DI #2286).


02DI.QXD 1/11/99 4:09 PM Page 3

ideasdesign

As digital communications anddata compression/decompressionproliferate, signal-processing func-

tions grow in importance. Whetheryou’re dealing with hard-wired logic orprogrammable engines, an understand-ing of binary-arithmetic rounding is im-portant in getting correct and consistentresults. Before we discuss rounding, con-sider a binary number (Figure 1).

At first glance, rounding seems a sim-ple matter. However, several variationson rounding exist. Depending on theapplication, you may use one of the fol-lowing techniques:● Truncation (round to minus infini-

ty)—This form of rounding ignoresany information in the fractionalvalue to the right of the binarypoint. You discard these bits, leavingthe integer value to the left of thebinary point unaffected. Truncationis also called round to minus infini-ty because it has the effect of round-ing to the more negative number.Truncation is in wide use because itis simple to implement: Just ignorethe unused bits.

● Round to plus infinity—This varia-tion is essentially the inverse oftruncation. If the fractional value tothe right of the binary point is notexactly zero, then you round up(make more positive) the integervalue. The implementation is morecomplex than truncation, becauseyou must test all the fractional bitsfor the existence of a one and thenincrement the integer value ifyou find a one.

● Round to zero—Round tozero applies to 2’s complementnumbers. (For the case of posi-tive numbers only, round to zeroreduces to truncation.) For nega-tive numbers, this rounding tech-nique depends on the fractionalvalue—the existence of anynonzero LSBs causes a round upto a less negative number. Thepositive-number case is simplytruncation. The implementationmust consider both the fraction-al-number value and the sign bit.

You increment the integer valueonly when the sign bit equals one(negative number) and the fraction-al value is not zero.

● Up-magnitude (round to infini-ty)—Up-magnitude is the inverse ofround to zero and applies to 2’scomplement numbers. If the num-ber is positive, round up for anyfractional number not equal to zero.If the number is negative, rounddown (truncate) for any fractionalnumber not equal to zero. This algo-rithm is perhaps most useful formaintaining the largest possiblemagnitude for digital-to-analogconversion. The technique finds usein recent standards, such as ISO/IEC11172-3 MPEG audio. Implemen-tation again considers the sign andfractional values: Increment theinteger only when the sign bit equalszero (positive number) and the frac-tional value is not zero.

● Simple round (2’s complementround)—Simple round applies toboth magnitude-only and 2’s-com-plement numbers. You round up theinteger value for all fractional valuesgreater than or equal to half the full-scale value of the fractional number.Half the full-scale value is a one andall zeros at the right of the binarypoint. For fractional values lowerthan half full-scale, the integer num-ber remains unchanged (trunca-tion). Implementation is relativelysimple in that you can add a one to

the number at the bit positiondirectly to the right of the binarypoint. This action increments theinteger for any fractional value equalto or greater than half the fractionalfull-scale value.

● Convergent round—Convergentround is similar to simple round.The difference has to do with thehalf-full-scale value of the fractionalnumber. A fractional numbergreater than half full-scale alwayscauses rounding up of the integernumber, a fractional number lessthan half full-scale causes the inte-ger to remain unchanged, and afractional number equal to half full-scale causes the integer to round upto the nearest even value. Con-vergent round is most useful foriterative processes in which cumula-tive addition causes errors to occurmore readily. Implementation re-quires testing the fractional value, aswell as the LSB of the integer num-ber. The integer number incrementsif the fractional value is greater thanhalf full-scale or if the fractionalvalue equals half full-scale and theinteger LSB is one (producing anodd number).

Listing 1 illustrates the roundingmethods using Verilog HDL. A 12-bitnumber, “x,” with the binary pointlocated to the left of Bit 3 serves as theinput (yielding an 8-bit integer and a 4-bit fraction). Each of the roundedresults are 8-bit integer numbers. Part A

of Listing 1 is the module list-ing, which defines and exercisesthe rounding outputs and dis-plays the results. Part B gives thedisplayed simulation results,which you can use to observe therounding differences. Be awarethat, although this HDL routineis fully synthesizable, the result-ing logic may not deliver the bestperformance or be the mini-mum configuration. You candownload Listing 1 from EDN’sWeb site, www.ednmag.com. Atthe registered-user area, go intothe Software Center to down-

A primer on binary-arithmetic roundingTom Balph, Motorola SPS, Tempe, AZ

A binary number can consist of any number of bits with thebinary point at any bit position. All bits to the left of thebinary point are the integer, or most-significant, bits of thenumber. All bits to the right of the point are the fractional,or least-significant, bits of the number. For 2’s complementnumbers, the most-significant bit has a negative binaryweight and is the sign bit. If no sign bit exists, the number ismagnitude only and unsigned.

F igure 1


ideasdesign

load the file from DI-SIG, #2285.When you implement rounding, per-

formance can suffer if an additional addoccurs, because of the rounding algo-rithm. At times, however, the logic pro-ducing the original number can hide theadditional add. As an example, if you

use simple round (2’s complementround) with a multiplier to round theresults, a constant one can appear in thepartial-product array (at the properlocation), and summing the one alongwith all the partial products producesno loss in performance. Here, the incre-

ment of the integer product is buried inthe multiplier-adder array. (DI #2285).

LISTING 1—ROUNDING EXAMPLES USING VERILOG HDL



ideasdesign

S elf-powered isolation amplifiers,which need no external isolatedpower supply, provide versatile and

convenient interfaces in many applica-tions that require galvanic isolation of thesignal source. Examples of such applica-tions include circuits that serve in indus-trial or medical environments, in whichisolation is necessary for noise reductionor safety. You can use a variety of isolat-ed signal-coupling techniques for the sig-nal paths of these amplifiers. Transform-ers, differential-capacitor, and opto-isolator schemes are all popular choices.For the internal isolated power supply,

transformer coupling is virtually univer-sal, despite the problems inherent in in-ductively coupled circuits. These prob-lems include relatively high interwindingstray capacitance and a tendency to cou-ple switching noise into the signal. Incontrast, the self-powered amplifier inFigure 1 is different in that it incorpo-rates optoisolators to effect communica-tion of both signal and power around theisolation barrier.

As in many isolation-amplifier designs,the signal processing in Figure 1’s circuituses PWM. The isolated-modulatorfront-end circuitry derives from an earli-

er ADC design and works as follows. IC1

compares the ±1V filtered input signalwith the voltage on C

1. The R

4C

4time

constant smoothes IC1’s output, and IC

2

compares the output with IC3’s approxi-

mately 1-kHz triangle waveform. R1, R

2,

and C1

scale and average the resultingvariable-duty-factor square wave andfeed the signal back to IC

1. This feedback

loop continuously adjusts IC2’s duty fac-

tor to maintain equal voltages on C1

andC

2. In doing so, the feedback forces IC

2’s

output square wave to track the uniqueT

+/(T

++T

2) duty factor that maintains

balance at IC1’s inputs.

Light powers isolation amplifierStephen Woodward, University of North Carolina, Chapel Hill, NC

A virtual perpetual-motion machine (when there’s light), this self-powered amplifier provides complete galvanic isolation for both power and signal.

1M*

NOTES: IC1 TO IC4=1/4 LT1443. S1 TO S3=1/3 HC4053. *1% METAL FILM.

ZERO200k

+1

+

1

+

1

20M

100200

C4

100 pF

R4

ISOLATED PWM MODULATOR

0.0047 mF THERMALLYMATCH10M

10M

13

1215

*1M

*1M

*1M

*1M

C5

10

1116

10M

5.1MR3

C2

VIN

0.0047 mF

R1

R2

C1

20M

2 4

5

IC3

IC1

IC2

IC4

C3

20M

9

8

0.022 mF

V1+1

36

714

1.2V

22 mF

+

27k

5

8

2

3

IN4148

1

200k

4

2

1

3

HCPL-2231

13

10

1

6

2

12

115V

1514

S1OI2 9

200

5V

PVI5100

OI1

S2

LT1009

3k

S3

3

4

5 240k 240k

LMC7101

0.022 mF

0.022 mF

3 4

15V

IC5+1 67

1M*V2

2

1M*

5V

VOUT

52.5V

51V

~20 mA

~20 mA

1 mSEC

2.6

0.6

DEMODULATOR AND LOWPASS FILTER

10 pF

+

2

7

6

1 nF

F igure 1


T o implement a step-up converterwith a current output, designers of-ten simply connect the load in place

of the top resistor in a resistive-dividerfeedback network. The bottom resistorthen serves as a current-sense resistor.Though simple, this approach is ineffi-cient. Low efficiency results fromthe relatively high sense volt-ages—usually, 1.25V but as highas 2.5V for some ICs. A switch-modedc/dc converter configured as a 20-mAcurrent source minimizes the efficiencyloss by lowering the sense voltage to 200mV (Figure 1). Advantages of this circuitinclude the factor-of-six gain in efficien-cy; minimal board area; and readily avail-able, low-cost components. Applicationsinclude battery charging, LED drive, andgeneral-purpose current sources.

Resistors R1

and R2

form a voltage di-vider that derives 200 mV from the IC’sreference output. This sense voltage con-nects to one emitter of the current mir-ror comprising Q

1and Q

2. Both collec-

tors connect to the output voltage via200-kV resistors. The collector of Q

2also

connects to the IC’s feedback pin, andQ2’s emitter connects to the low-side cur-rent-sense resistor, R5. The feedback net-work appears to the IC’s control loop as

a common-base amplifier. Selecting a2N3904 for Q

2yields sufficient emitter-

to-collector gain for the purpose: ap-proximately 80V/V. Moreover, the net-work’s large bandwidth (characteristic of

common-base configurations) preventsinstability in the IC’s control loop. (DI#2307).

Low-cost feedback circuit boosts efficiencyJohn Guy, Maxim Integrated Products, Sunnyvale, CA

The use of a current mirror in the feedback loop boosts efficiency and stability in this current-out-put step-up converter.

C5differentiates the IC

2square wave to

provide bipolar drive pulses to the an-tiparallel LEDs in the high-speed, low-current optoisolator OI

2. In turn, OI

2

produces ground-referred pulses. Therather unusual RS flip-flop formed bycross-connected switches S1 and S2 con-verts these pulses back to a logic-levelsquare wave having the same duty factoras IC2’s output. Demodulation and fil-tering of the square wave to accurately re-produce the original analog signal occursthrough the action of the single-pole,double-throw switch, S

3, which chops the

2.500V V2

reference voltage according to

the T+/(T

++T

2) square-wave duty factor.

The lowpass, gain-of-two filter, IC5, then

extracts the dc component of S3’s 0 to

2.5V waveform and scales and offsets itto produce a low-ripple, ±2.5V signal, ac-cording to the formula

Power for the isolated-modulator sideof the amplifier comes from OI1, an In-ternational Rectifier (El Segundo, CA)PVI5100 photovoltaic opto IC. Marketedas an isolated MOSFET-gate driver, thePVI5100 can source approximately 20mA of current at 4V (80 mW), just

enough to keep the anorexic LT1443 aliveand functional. IC

4shunt-regulates OI

1’s

output to provide a stable 4V ratioedagainst the MAX924’s 1.2V±1% internalreference. Overall frequency response isdc to 10 kHz; input impedance is ap-proximately 1 TV with less than 1-pAbias. The circuit can thus provide goodoverall accuracy with high-impedanceinput sources. You can trim gain and off-set errors to zero; the excellent drift specsof the LT1443 maintain the trim overtemperature. (DI #2304).

ideasdesign

Figure 1



.V5.2)TT/(T5.2V IN–O ×=+×= ++

02DI.QXD 1/11/99 4:09 PM Page 7

ideasdesign

Design Idea Entry Blank

To: Design Ideas Editor, EDN Magazine275 Washington St, Newton, MA 02158

I hereby submit my Design Ideas entry.

Name

Title

Phone

E-mail Fax

Company

Address

Country ZIP

Design Idea Title

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Entry blank must accompany all entries. (A separate entryblank for each author must accompany every entry.) Designentered must be submitted exclusively to EDN, must not bepatented, and must have no patent pending. Design mustbe original with author(s), must not have been previouslypublished (limited-distribution house organs excepted), andmust have been constructed and tested. Fully annotate allcircuit diagrams. Please submit software listings and allother computer-readable documentation on a IBM PC diskin plain ASCII.

Exclusive publishing rights remain with Cahners BusinessInformation unless entry is returned to author or editor giveswritten permission for publication elsewhere.In submitting my entry, I agree to abide by the rules of the

Design Ideas Program.

Signed

Date

Your vote determines this issue’s winner. Vote now, by cir-cling the appropriate number on the reader inquiry card.

Entry blank must accompany all entries. $100 cash award for all published Design Ideas. An additional $100 cash award forthe winning design of each issue, determined by vote of readers. Additional $1500 cash award for annual Grand Prize Design,selected among biweekly winners by vote of editors.

Circle 10 or visit www.ednmag.com/InfoAccess


ideasdesign


February 4, 1999 | edn 101www.ednmag.com

Y ou can implement a simple andlow-cost keyboard en-coder by using a key-con-

trolled resistive divider connected to anADC (Figure 1). This type of circuit is es-pecially suitable for embedded systemsthat use a mC with an integrated ADCsection. To obtain the best noise marginbetween keys, select resistors to yield anequal division of the voltage levels. Tomeet this criterion using the circuit inFigure 1, you must use a set of resistorswith all-different, specific val-ues. For example, a 10-keykeyboard uses a 10-kV pullup resistor,R

P, and values of 1.1, 1.3, 1.8, 2.4, 3.3, 5.1,

8.2, 16, and 51 kV for R1

through R9. Us-

ing commonly available resistor valuesand tolerances and taking account of thekey resistivity and ADC linearity errors,you’re limited in the number of keys youcan encode with a safe noise margin. Us-ing an 8-bit ADC, the cited 10-key ex-ample is close to that limit.

The circuit in Figure 2, despite itsmany resistors, overcomes the problem ofthe many restore values. The circuit issymmetric and uses the same two resis-

tor values for all keys. It is also easy to ex-pand the circuit for more keys. As in Fig-ure 1’s circuit, if you simultaneously pressmore than one key, the circuit detectsonly the key whose connection is closestto the ADC. The chain of R

1resistors de-

fines the voltage level asso-ciated with each key. Theirnominal value is a trade-offbetween the power dissipa-tion and the values of R

2

and R3, which depend on

R1; the total number of

keys; and the desired noisemargin. R

2minimizes the

voltage deviations at thenodes of the R

1chain

whenever you simultane-ously press two or more keys.Therefore, you should calculateits value, much higher than thatof R

1, by taking into account R

1

and the desired width of the volt-age window associated with eachkey. Similarly, R

3’s value should

be much higher than that of R2to

ensure that the voltage level as-sociated with each key almostcompletely transfers to theADC’s input.

The circuit was tested by en-coding 15 keys with one 8-bitanalog input of the MicrochipPIC16C71 mC. The resistor val-ues are 47V, 3.9 kV, and 4.7 MVfor R

1, R

2, and R

3, respectively.

Only R1

needs a tight tolerance;the others are less demanding.The window of key acceptance isset to a 7-LSB interval centeredon the theoretical key level. Thisinterval is large enough to ac-commodate the worst case (si-multaneously pressing the two

more-distant keys from the analog input)with a safety noise margin between validkeys of 10 LSBs. (DI #2319).

ADC circuit optimizes key encodingVitor Amorim, Siemens, and J Simões, University of Coimbra, Coimbra, Portugal

This is a simple way to encode keys, but it requires a range ofresistor values for a large number of keys.

This key-encoding circuit simplifies resistor inventories,and provides a comfortable noise margin to boot.

Rn

5V

R1RP R2ADC

INPUT

F igure 1

5V

R1 R2

R2

R2

R2

R3R1

R1

R1

R1

ADCINPUT

F igure 2

ADC circuit optimizes key encoding ........................................................101

RS-232C circuit has galvanic isolation..........................................................102

Digital pot adjusts LCD’s contrast............104

Add speech encoding/decoding to your design ..............................................106

Cheap PWM IC makes synchronous gate driver......................................................110

Circuit detects total on-time ......................112To Vote For This Design,

Circle No. 332

102 edn | February 4, 1999 www.ednmag.com

ideasdesign

Y ou can obtain longer transmis-sion distances with the RS-232C in-terface if you use galvanic isolation

between the two linked terminals. Gal-vanic isolation also eliminates problemsarising from disparate potentials betweenterminals. Using two MAX860/861 ICsand two TPL2200 optoisolators, you canobtain galvanic isolation for three-wiretransmission without external supplies(Figure 1). The MAX860/861 circuits,which generate two voltages of differentpolarity, regardless of the polarity of TxD,which provides the supply voltage, are thebasis of the design.

For the positive TxD polarity, theMAX860/861 ICs function as voltage in-verters, whereas for negative-polarityTxD, the ICs function as voltage dou-blers. Diodes D

1and D

7provide the pos-

itive supply voltages; D4

and D9

providethe negative supply voltages, dependingon the polarity of TxD. The diode-resis-tor pairs D

5, R

1and D

10, R

2determine the

operating mode (doubler or inverter) ofthe MAX860/861 ICs, depending on thepolarity of TxD. Zener diodes D

2, D

3, D

6,

and D8

protect the MAX860/861 ICsfrom supply overvoltages.

The digital-output TLP2200 optoiso-

lators provide galvanic isolation and gen-erate the RxD received signals with RS-232C logic levels. The circuit providesgalvanically isolated communication infull-duplex mode at any standard trans-mission speed. The use of galvanic isola-tion allows transmission over nearlytwice the distance for nonisolated sys-tems. If you use a four-wire cable andsplit the separation circuits at the cableends, you can further increase the trans-mission distance. (DI #2315).

RS-232C circuit has galvanic isolationIoan Ciascai, REI Data, Napoca, Romania

RS-232C-interface ICs and optoisolators provide a supplyless RS-232C transmission link with galvanic isolation for increased distance.

VDD

VSS

OUT

1EN

A

KGND2

2.2k

TxD2

VDD

VSS

OUT

1EN

A

KGND1 3

2

TLP2200

8

7

6

5

IC32.2k

22k

2

3

TLP2200

1N414

1N581

D4TxD1

FC VDD

C1 SHDN

GND LV

C11 OUT

IC2D1

1 8

2 7

3 6

4 5

MAX860

2.2 mF

1N581

8

7

6

5

R1

IC1

D2

D3

5.6V

5.6V

4.7 mF

4.7 mF

FCVDD

C1SHDN

GNDLV

C11OUT

IC4D6

D8

R2 D10

D7

D9

8 1

2

3

4

7

6

5

MAX860

22k

1N581

1N414

2.2 mF

RxD2

1N5815.6V

5.6V

4.7 mF

4.7 mFC4

C5

RxD1

D5

F igure 1



ideasdesign

Y ou can use a digitally controlledpotentiometer for many purposes.In this example, you can use the de-

vice to regulate the contrast of a standard(such as two lines by 40 characters) LCD.You can use the circuit in Figure 1 in aportable test system, in which you needto change the contrast of the LCD as afunction of the viewing angle.You choosethe contrast setup from a menu and thenuse up or down buttons with mC IC

1to

adjust the contrast. The mC stores thecontrast value in the digital potentiome-ter, IC

2. This design uses a Xicor 10-kV

unit (dubbed “EEPOT”), but you coulduse other devices in the design.

The EEPOT connects to the LCD’s VOline. You could connect the other side ofthe potentiometer to ground, but, forbetter contrast, you can apply a negativevoltage to this terminal. This circuit has a

serial interface, so it uses the negative-voltage generator in the MAX232 RS-232C/TTL converter. Listing 1 is the sub-routine for the 8051 mC. The program

calls the routines for contrast-up or -down. (DI #2314).

Digital pot adjusts LCD’s contrastJef Collin, CSE Systems, Turnhout, Belgium

A standard 8051 mmC and a digitally controlled potentiometer provide a convenient way to vary the contrast of an LCD, using contrast-up and -downbuttons.

X1

X2

RESET

EA/VP

IC18051

D0

D1

D2

D3

D4

D5

RS

RW

E

D6

D7

INC

U/D

VH

VSS

VCC

CS

VL

VW

IC2X9103

1 2 3 4 5 6 7 8 9 10 11 12 13 14

GND VCC VO RS RW E DO D1 D2 D3 D4 D5 D6 D7

C1+

C12V+

V2

C22

C2+

T1I

T2I

R1O

R2O

T1O

T2O

R1I

R2I

VCC

GND

IC3MAX232

C2

VCC

VCC

VCC

C3

2

6

14

7

13

8

15

161

3

4

5

11

10

12

9

10 mF C410 mF

C510 mF

10 mF

LCD

R110k

1

2

3

4 5

6

7

8

F igure 1


LISTING 1—ROUTINE FOR LCD-CONTRAST ADJUSTMENT


ideasdesign

Adding speech capabil-ities to a design cansometimes lead to com-

plex algorithms and expensiveDSPs or specialized audiochips. However, with the com-pletion of a simplified adap-tive differential pulse-code-modulation (ADPCM) algo-rithm, you can now imple-ment these audio capabilitiesin low-cost 8-bit mCs, whichtypically have lower power con-sumption and cost than theirDSP or audio-chip counter-parts. A two-chip design is fea-sible by offloading the encod-ing and decoding tasks onto themC as if it were a peripheral.

Since 1991, the InteractiveMultimedia Association (IMA)Digital Audio Technical Work-ing Group (DATWG) has beenworking to define a cross-plat-form digital-audio exchangeformat. An inherent problemexists with the exchange of au-dio data between PC, Mac, andworkstation computers. Eachcomputer has its own datatypes and sampling rates. InMay 1992, IMA DATWG pub-lished the first revision of theCross-Platform Digital AudioInterchange recommendationthat specifies three uncom-pressed and one compresseddata type at various samplerates. The compressed datatype is the Intel (www.intel.com) 4-bit DVI ADPCMalgorithm. This algorithmcompresses a 16-bit signed au-dio sample into 4 bits and takesadvantage of the high correla-tion between consecutive samples, whichenables the prediction of future samples.Instead of encoding the sample itself,ADPCM encodes the difference betweena predicted sample and the actual sam-ple. This method provides more efficient

compression with fewer bits per sampleand yet preserves the overall quality ofthe audio signal. Both the encoder rou-tine (Listing 1) and the decoder routine(Listing 2) are written in C to ease read-ability.

The hardware implementation de-pends on the type of interface. With aparallel interface, you can use thePIC16C556A (Microchip Technology,www.microchip.com) (Figure 1a). Astandard parallel interface uses the chip-

Add speech encoding/decoding to your designRodger Richey, Microchip Technology Inc, Chandler, AZ

LISTING 1—ADPCM ENCODER

select (CS), output-enable (OE), andwrite-enable (WR) pins on PortA. The 8-bit data interface con-nects to the 8-bit Port B on the mC. Youcan use two additional I/O lines for sta-tus information, such as encode/decodeselect, to the mC or an interrupt line tothe main controller to indicate when datais ready. CS, which connects to the RA

4

pin, can interrupt the PIC16C556A onthe start of a transmission.

The second hardware implementationuses a serial interface and an eight-pinmC (Figure 1b). The PIC12C672 usesfour of the pins for power, ground, andoscillator input and output. Three of theremaining I/O pins are for clock (SCK),data in/out (D

IN/D

OUT), and CS. You can

use the other I/O pin to indicate the de-sired encode/decode operation or as aninterrupt to the main controller. CS con-nects to the external interrupt pin, GP

2,

to detect the start of a transmission.Both mCs have a flexible oscilla-

tor structure for use with a crystal,a resonator, or an external clocksignal. Both parts of the figureshow the mC using an externalcrystal as the clock source. Becausethese devices are fully static, themain controller can provide theclock source to the mC. By turningthe clock source on and off as nec-essary, the main controller can fur-ther decrease overall power con-sumption. This method alsoallows control of the speed atwhich the algorithm runs, which isproportional to the sample rate ofthe system.

To fully implement the mC as anADPCM-encoder/decoder peri-pheral requires firmware to im-plement the serial or parallel in-terface, such as listings 1 and 2,and a main routine to tie every-thing together. The main con-troller is responsible for samplingthe incoming audio waveform,storing and retrieving the AD-PCM codes from nonvolatilememory, and then playing the re-sulting samples. The main con-troller feeds samples or ADPCM codes tothe mC and then reads the resulting AD-PCM codes or samples from the mC.

The listings are available for down-

loading from at EDN’s Web site, www.ednmag.com. At the registered-user area,go into the Software Center to downloadthe file from DI-SIG, #2292. (DI #2292)


ideasdesign

Using the simplified ADPCM algorithm, you can now implement audio capabilities in mCs byoffloading the encoding and decoding tasks onto the parallel (a) or serial (b) mC as if it were aperipheral.

(a) (b)

PIC16C556A

RA0 OSC1

RA1

RA2 OSC2

RA3

RA4

RB0 MCLR

RB1

RB2

RB3

RB4 VDD VDD

VSSRB5

RB6

RB7

DATALINES

INT17

18

1OE

2WR

3CS

6

7

8

9

10

11

12

13

E/D

16

15

2

31

8

14

5

GP0 OSC1

OSC2

VDD

VSS

GP1

GP2

GP3

PIC12C6727

6

54

VDD

ENCODE/DECODE ORINTERRUPT

SCKCS

DIN/DOUT

LISTING 2—ADPCM DECODER

F igure 1



ideasdesign

A system with a mP, memory,and peripherals usually re-quires several power-supply

voltages. Designers typical-ly use local switching reg-ulators to produce the desiredvoltage rails. One of the mostcommon topologies, the synchro-nous buck regulator, converts a 5or 12V bus to some other, lowervoltage. This approach has gainedvast acceptance, thanks to its rel-ative simplicity and high conver-sion efficiency. Specialized syn-chronous buck controllers areavailable, but you generally pay apremium for these ICs. Mean-while, many inexpensive, general-purpose PWM controllers areavailable, but they require you toimplement synchronous rectifica-tion with discrete circuitry. The imple-mentation is a difficult task, because itinvolves building two out-of-phase, mutually exclusive gate drivers. The block diagram in Figure 1shows how to use any general-purposePWM controller (for example, theCS3843 from Cherry Semiconductor inEast Greenwich, RI) to configure a syn-chronous buck regulator.

The most critical aspect of the driverdesign is nonoverlap timing, which pre-vents simultaneous high states at gates Hand L, thus eliminating the simultane-ous turn-on of Q

1and Q

2, with result-

ing shoot-through currents. Figure 2shows details of the driver block. The in-put signal passes through two inverters,IC

1Aand IC

1B, to generate the Gate H sig-

nal in phase with the input. The com-plementary follower, Q

1and Q

2, forms a

current amplifier to provide sufficientdrive for the top MOSFET. Meanwhile,IC

1Dinverts the input, and Q

3and Q

4

amplify the signal to drive the bottomMOSFET.

IC1C

and IC1E

provide the nonoverlapfunction. Each of the inverters ensures alow state at the corresponding gate-drive output until the other driver’s out-put falls below a certain threshold. This

Cheap PWM IC makes synchronous gate driverDimitry Goder, Switch Power Inc, Campbell, CA

A sprinkling of TTL gates and four bipolar transistors provide efficient, nonoverlap drive to the twoMOSFETs in a synchronous rectifier.

VCC

GATE

COMP

VFB

GNDANY NONSYNCHRONOUSPWM CONTROLLER(FOR EXAMPLE, CS3843FROM CHERRY SEMI)

12V 5V

GATEDRIVERWITHNON-OVER-LAP 3.3V

OUT+

+

Q1

Q2

GATE H

GATE L

L1

5V

1k

12V

1k

21

PWM IN

7406 7406

7406

7406

7406

IC1A IC1B

IC1D

IC1E

IC1C

65

3 4

Q12N2222A

Q22N2907A

Q32N2222A

Q42N2907A

R1

1.5kR2750

GATELOW

GATEHIGH

9 8

R4750

R3

1.5k

11 10

1k

12V

All it takes to drive high- and low-side MOSFETs from a PWM controller is a simple driver with 1808 out-of-phase outputs, but you must beware of simultaneous MOSFET conduction.

F igure 1

F igure 2


ideasdesign

function prevents simultaneoushigh states, regardless of thecircuit delays and the type ofMOSFETs you use. The TTL switch-ing threshold and the values of R

1, R

2

and R3, R

4determine the nonoverlap

threshold. The threshold is approx-imately 3V for the circuit in Figure2, but you can easily adjust it for oth-er values.

Creating a high-side driver re-quires a bias voltage higher than theinput voltage. A 12V line is com-monly available, so you can use it topower the driver. The outputs ofIC

1Band IC

1Dmust swing between

ground and 12V; you thus need a7406 open-collector inverter with a

high-voltage capability. If12V is unavailable, you canuse charge-pump circuitryto double the input voltage.The driver shows excellentperformance, with 60-nsecnonoverlap time, superior tothat of many available ICs.Figure 3 shows the two gatedrivers’ outputs, with eachdriver switching an IRL3103n-channel MOSFET, a goodchoice for a 10A converter.The total cost of the driverdoes not exceed 30 cents. (DI#2306).

At least 60 nsec separates the turn-on drive from the upper andlower drivers, thus preventing simultaneous MOSFET conduction.

F igure 3

The circuit in Figure 1 provides avoltage that is directly proportionalto the sum of the total on-

times for a number of positivepulses that occur during the interval be-tween sample signals. When a positivepulse arrives at the control input toswitch IC

1A, a constant-current source

charges capacitor C1

through IC1A

for theduration of that pulse and for each sub-sequent pulse. The constant-currentsource comprises Q

1; R

1; C

1; and R

2,

which drives Q1’s gate at C

1’s potential. C

1

and C2

should be noninductive and havelow dielectric absorption.

When you apply a low signal to theSample line, the sample/hold circuit (IC

2)

latches the analog voltage on C1. You ad-

just R4

for 0V at the output with no puls-es at the input. The trailing edge of theSample signal switches IC

1Bon, discharg-

ing C1

to an initial 0V potential. You canconnect unused analog switches in par-allel with IC

1Bto speed the discharge.

Higher supply voltages also improve thecircuit’s speed and performance. (DI#2300).

Circuit detects total on-timeRichard Nachazel, Vista Electronics Co, Ramona, CA

NUL

IN

C OUT

L

LR

LF398

5

SAMPLE

PULSES A B

C

A B

C

74HC4066

74HC4066

DGND

C30.01 mFR6

100k

AGND

12

11

13

1IC1A

IC1B

10

2

300k

R2

Q12N5458

5 V(A)

D

SR1

20k

G

AGND5 V(D)

R84.3k

R75.6k

C10.1 mF C2

0.1 mF

R3

51k

IC2

S/H_OUT

AGND

R5 R4

7.5k 1k

5 V(A)

DGND

2

3

68

7

Two ICs, a FET, and a handful of components form a pulse-width-to-voltage converter.

F igure 1




ideasdesign




Name

Title

Phone

E-mail Fax

Company

Address

Country ZIP

Design Idea Title





Signed

Date




ideasdesign


February 18, 1999 | edn 137www.ednmag.com

Y ou often need to control the dutycycle of a square wave. Thecircuit in Figure 1 works

from a single 5V supply at a frequency of100 kHz. With minor componentchanges, you can configure it for a rangeof frequencies. The circuit consists of aramp (sawtooth) oscillator and a com-parator. The circuit compares the rampto an externally applied voltage, V

CNTRL.

When VCNTRL

is greater than the rampvoltage, the PWM output is 5V. The saw-tooth oscillator consists of a currentsource (R

1, R

2, R

3, and Q

1), a timing ca-

pacitor (C1), and the oscillator-control

circuitry (R4, R

5, R

6, and IC

1A). The oscil-

lator-control circuitry sets the upper andlower voltages of the timing capacitor at3 and 1V.

R1

and R2

set the voltage at Q1’s base to

1V. R3and the V

BEdrop (0.7V) are in par-

allel with R1, so the voltage across R

3is

0.3V for a current of 200 mA. Because theemitter current greatly exceeds the basecurrent, the collector current is nearly200 mA. A capacitor receiving its chargefrom a current source charges linearly.The current in C

1is 200 mA, and the

change in voltage is 2V (1 to 3V). FromI=CdV/dt, dt=10 msec, and the frequen-cy is 100 kHz. The oscillator-control cir-cuitry uses a comparator with hysteresisto compare the capacitor (ramp) voltage

with the charge limits. An externally ap-plied power-on-clear (POC) signal en-sures reliable start-up. POC must con-nect to an open-collector device thatpulls to ground at power-on and pro-duces no voltages when inactive.

After removal of POC, IC1A

’s Pin 5 is atground, IC

1A’s Pin 12 is at open-collec-

tor status, and IC1A

’s Pin 4 is at 3V (thevoltage across R

5). C

1now starts charg-

ing. When the voltage on C1

exceeds 3V,IC

1A’s Pin 12 switches to nearly ground,

IC1A

’s Pin 4 drops to 1V (the voltageacross the parallel combination of R

5and

R6), and the charge on C

1rapidly bleeds

off through D1. The discharge time is

short enough to have a negligible effecton the oscillation frequency. When thevoltage on C

1drops below 1V, IC

1A’s Pin

12 switches to open-collector status, D1

stops conducting, and C1begins to charge

again. The entire cycle repeats, creatingsawtooth oscillation.

The circuit creates PWM by compar-ing the voltage on C

1with V

CNTRL. As long

as VCNTRL

is greater than the voltage on C1,

the PWM output stays at 5V. You shouldlimit V

CNTRLto a bit more than 1V and a

bit less than 3V to prevent comparatoroscillation. If the source of V

CNTRLcan tol-

erate it, you can add hysteresis. The rela-tionship of PWM to V

CNTRLis linear:

PWM width=50(VCNTRL

21)%, valid for1V<V

CNTRL<3V. To increase the operating

frequency, you can replace the LM319with a faster comparator. (DI #2309).

Simple circuit provides efficient PWMKenneth Levine, Eldec, Lynwood, WA

A dual comparator and a handful of components configure an inexpensive PWM generator.

_

+

_

+

R515k

R71k

R6

IC1A

IC1B

D1

12

5V

V1

5V

R1

R2

R3

2N2906Q1

10k 1.5k

40.2k

0.001 mF

11

G

C1

POC

PWM

VCNTRL9

10 LM319

LM319

7

5V

6

11

6

8

3

R410k

4

5

1N914

3.01k

V+

V2

V+

V2

+

2

G

F igure 1

Simple circuit provides efficient PWM ....137

Visual Basic models MDAC offset............138

Charge-pump circuit divides by two ......140

Pass transistor lowers dropout voltage ..144

PIC mC implements CRC-16 algorithm ..146

Monostable makes low-cost F/V converter ........................................................148



ideasdesign

I t’s hard to imagine that, for suchan old-hat item as a standard R-2Rmultiplying DAC (MDAC), there still

exists some “dark area” in modeling andcalculating its dc offset, V

OFF, and related

output resistance, RO. You can obtain

some information from references 1 and2 and other references regarding the codedependency of R

Oand V

O, but the sim-

plified formulas given therein are insuf-ficient for thorough engineering analy-sis/design and computer modeling/simulation. Moreover, these formulas ap-ply mainly to the case in which the Ref er-ence pin (Figure 1) is open, whereas mostMDAC applications connect the Refer-ence pin to a low-impedance source.Also, the source resistance, R

IN, has an im-

pact on VOFF

and RO. This Design Idea in-

troduces an equivalent circuit for theMDAC and discusses mathematicalmodels. A software program, “DAC De-signer AO,” simplifies the offset calcula-tions. You can download the Visual Ba-sic files from EDN’s Web site, www.ednmag.com. At the registered-user area,go into the Software Center to download

the files from DI-SIG, #2305.The models are based on the idealized

R-2R resistive ladder in Figure 1 withzero on-resistance and infinite off-resis-tance in the switches and without currentleakage or parasitic voltages. Figure 2gives an equivalent reciprocal-p networkfor the ladder, in which G

11is the input

conductance with the output terminalsshorted, G

12is the transfer conductance,

and G22

is the output conductance withthe input terminals shorted. The applic-able math formulas are as follows:

It’s obvious that G11

has a constant val-ue, the reciprocal of the base resistance,R. G

12is a linear function of the input

code and base resistance R. The expres-sion for G

22, however, reveals complex,

nonlinear behavior as a function of thedigital input code. A Thevenin transformin Figure 2’s circuit produces the simpli-fied equivalent circuit in Figure 3. Theoutput resistance, R

O, in the most com-

mon case, when the MDAC connects to

TABLE 1—MAXIMUM OFFSET WITH REF PIN GROUNDEDN Binary(bits) Decimal Hex (maximum) VOFF

8 235 00EB 11101011 2.652*VOS

9 469 01D5 111010101 2.763*VOS

10 939 03AB 1110101011 2.875*VOS

11 1877 0755 11101010101 2.986*VOS

12 3755 0EAB 111010101011 3.097*VOS

Visual Basic models MDAC offsetOlga Belousava, Los Alamos, NM, and Alex Belousov, New York, NY

R-2R RESISTIVE LADDER

R R RREF

RIN

2R

SW1

D1 (MSB)

2R

SW2

D2

2R

D(N21) D(N) (LSB)

2R 2R

SW(N)SW(N21)R

A

VOS

RFB

IOUT

IOUT

VOUT

VREF

+

1

+

1

+1

The output impedance of a multiplying R-2R DAC is a complex, nonlinear function (third equation in the text) of the digital input code.

F igure 1

,R/1G11 =

-==

N

1i

ii12 ,R/)2D(G 1

••-

-•+=

-

= +=

=

1N

2i

N

1ij

jj

ii

N

1i

ii22

.R3/)))2D()41(D(

)421(D((G

11

1


ideasdesign

Small size and efficiency approach-ing 100% make switched-capacitorcharge pumps popular for

voltage doubling and inverting inminiature dc-dc applications. Few areaware, however, that most charge pumpscan halve as well as double or invert aninput voltage. The increasing adoption oflow-voltage logic makes this 32 capabil-ity useful for generating low-voltage sup-plies in portable equipment. You can useit, for example, to convert a 3.6V RF-sup-ply voltage to 1.8V for powering low-

Charge-pump circuit divides by twoBudge Ing, Maxim Integrated Products, Sunnyvale, CA

RF CIRCUITSPOWER AMP

DC/DCCONVERTER

MAX660MAX1683

LOW-VOLTAGELOGIC

3.6V

1.8V

F igure 1

a low-resistance source, is the reciprocalof G

22. The offset voltage is thus

Table 1 gives the maximumtheoretical values for V

OFFin 8- to

12-bit MDACs. You can easily obtain theexact values for V

OFFand R

Ofor any ar-

bitrarily chosen input code by using thecited software program. The programalso allows you to compute the statistics(maximum V

OFF, its mean, and standard

deviation) for any predefined range of in-put codes. You can use the suggestedequivalent circuit and mathematicalmodels with any computer simulationpackages in dc-analysis mode. (DI#2305).

References1. Sheingold, Daniel H, Editor, Analog-

Digital Conversion Databook,Prentice-Hall, 1986.

2. Data Converter Reference Manual,Volume 1, pg 2-540 to 2-541, Analog De-vices, 1992.

+2 vOFF

+

2

vOS

A

IOUT

IOUT

RFB=R

MDAC EQUIVALENT CIRCUIT (VREF=0)

RFB

REF G12

RIN

(G11-G12)

(G22-G12)

+2

+

2

AIOUT

IOUT

RO

RFB=R

MDAC EQUIVALENT CIRCUIT (VREF=0)

RFB

VOFF

VOS

The input conductance, transconductance, and output conductance of the MDAC in Figure 1 providea convenient simplification of the circuit.

A Thevenin transformation of the equivalent circuit in Figure 2 produces a greatly simplified circuit.

).GR1(VV 22OSOFF •+•=

F igure 3

F igure 2

Simply reversing a voltage-doubler charge pump converts it to a voltage divider.



voltage logic (Figure 1). Simply reversingthe input and output of a voltagedoubler makes it a voltage divider.Implementing this scheme with MAX660or MAX1683 voltage-doubler chargepumps requires only three external ca-pacitors (Figure 2). Both configurationsin Figure 2 accept input voltages of 3.6 to10V, but they present trade-offs in sizeand output-current capability.

For 3.6V inputs, the robust MAX660,which comes in an eight-pin DIP or SOpackage, delivers 150 mA with efficiencygreater than 88% and an output-voltagedrop of less than 300 mV. If you requirea smaller package, the MAX1683 (avail-

ideasdesign

A MAX660 voltage doubler makes an efficient 150-mA voltage divider (a); the smaller MAX1683does the same for applications requiring only 50 mA (b).

Over the usable 3.6 to 10V input-voltage range, the small MAX1683 (a) exhibits higher output resistance than the more robust MAX660 (b).

Both the MAX1683 (a) and the MAX660 (b) offer better than 90% efficiency over a large portion of their usable operating range.

MAX660

(a)(b)

V+ GND

C+ LV

C2OUTC1

100 mF

0.1mF

INPUTVOLTAGE

OUTPUTVOLTAGE

MAX1683

OUT IN

C+

C2

GNDC110 mF

0.1mF

INPUTVOLTAGE

OUTPUTVOLTAGE

C2100 mF

C210 mF

NOTE: VOUT=VIN

2.

8

7.5

7

6.5

6

5.5

5

4.5

4

3.5

33 4 5 6 7 8 9 10

INPUT VOLTAGE (V)INPUT VOLTAGE (V)

ROUT (V)

ROUT (V)

LOAD=5 mA

LOAD=50 mA

LOAD=50 mA

LOAD=150 mA

MAX1683

MAX660

(a) (b)

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.13 4 5 6 7 8 9 10

1

0.98

0.96

0.94

0.92

0.9

0.88

0.86

0.843 4 5 6 7 8 9 10

EFFICIENCY (%)

INPUT VOLTAGE (V)

1

0.98

0.96

0.94

0.92

0.9

0.883 4 5 6 7 8 9 10

EFFICIENCY (%)

INPUT VOLTAGE (V)

LOAD=5 mA

LOAD=50 mA

LOAD=50 mA

LOAD=150 mA

MAX660

MAX1683

(a) (b)

F igure 2

F igure 4

F igure 3


ideasdesign

able in a five-pin SOT-23) offers 50-mAcapability with a 3.6V input and as muchas 100 mA with inputs higher than 8V. Itsefficiency is 97% at 5 mA and 86% at 50mA. Each device has an internal clock.The MAX660 runs at a nominal 10 kHz(with the FC pin open), and theMAX1683 runs at a nominal 35 kHz.Each divider’s output resistance dependson the internal clock frequency, the fly-ing capacitor (C

1), the resistance of the

internal switches, and the resistance ofthe output capacitor C

2.You can calculate

the output resistance by:where f

OSCis the oscillator frequency, R

1

to R4are the R

DS(ON)values for the four in-

ternal switches, and RESR

is the equivalentseries resistance for the output capacitor,C

2. The graphs in Figure 3 illustrate the

performance of the charge pumps oper-ating in voltage-divider mode. Figure 3ashows the output resistance versus inputvoltage for the MAX1683. Figure 3bshows the same parameters for theMAX660. Figure 4 shows efficiency ver-sus input voltage for the MAX1683 (Fig-ure 4a) and the MAX660 (Figure 4b).(DI #2301).

W ith linear regulators, youmeasure dropout voltage,V

IN2V

OUT, at the mini-

mum input voltage for which the IC sus-tains regulation. Low dropout meanslonger battery life, because the load cir-cuit continues to operate while the bat-tery discharges to a lower terminal volt-age. The external transistor helps to forma linear-regulator circuit whose dropoutvoltage at 100-mA load current is only 10mV (Figure 1). (The linear-regulator ICby itself specs a 100-mV dropout at 100mA.) The external transistor also booststhe maximum available load current to1A.

Unorthodox connections enable the ICto drive Q

1. Connecting Pin 3 to the tran-

sistor’s base allows base current to flowthrough the internal switching MOSFET,out of Pin 4, and through R

2to ground.

The MOSFET then regulates VOUT

bycontrolling Q

1’s base current. Because C

2

sets a dominant pole that stabilizes theloop, you should choose a ceram-ic type or other low-ESR capacitor.C

2improves the phase margin by form-

ing a pole-zero combination that in-creases the phase at crossover. Q

1satu-

rates when the battery voltage drops lowenough for V

OUTto drop out of regula-

tion, and R2

limits the base current forthat condition to approximately 10 mA.Q

1’s collector-emitter voltage at satura-

tion, 10 mV with 1-mA base current and100-mA collector current, sets thedropout voltage for these conditions.

Pass transistor lowers dropout voltageMatt Schindler, Maxim Integrated Products, Sunnyvale, CA

Unorthodox transistor connections to a low-dropout regulator allow you to squeeze a 100-mVdropout voltage down to 10 mV.

Dropout voltage for the circuit in Figure 1 varies from 10 mV at 100 mA to 90 mV at 1A.

+

3.3 TO 4.8V

C210 mF

C110 mF

R11k

Q1FMMT717

1 3

SHDN IN

FB

OUT

GND

IC1MAX8863

R2270

C320 pF

VOUT3.3V

R4100k

R3165k1%

5

4

2

0 100

100908070605040302010

0200 300 400 500 600 700 800 900 1000

LOAD CURRENT (mA)

DROPOUT VOLTAGE

(mV)

F igure 1

F igure 2


,R2)R–R–RR(4Cf

1R ESR3124

1OSCOUT +++=


ideasdesign

The measured dropout voltage varieswith load current (Figure 2). The circuitdelivers as much as 1A at 3.3V. You canadjust the output from 5.5V down to1.25V using the formula V

OUT=

1.25[1+(R3/R

4)], with appropriate

changes to the value of R2, using the for-

mula R2=(V

IN(MIN)20.7V)/10 mA. Small

components allow the entire circuit tooccupy less than 0.24 in.2 of board area.

(IC1

comes in an SOT-23 package.) (DI#2323).

X1 X2 X3 X4 X5 X6 X7 X8

STAGE9

STAGE1

STAGE2

STAGE3

STAGE4

STAGE5

STAGE6

STAGE7

STAGE8

STAGE10

STAGE11

STAGE12

STAGE13

STAGE14

STAGE15

STAGE16

X9 X10 X11 X12 X13 X14 X15 X16

X0

DATA INPUT TO SHIFT REGISTER

(a) POLYNOMIAL REPRESENTATION OF CRC-16: X16+X15+X2+1

(b) HARDWARE REPRESENTATION OF CRC-16

PIC mmC implements CRC-16 algorithmLon Glastner, Solutions Cubed, Chilo, CA

D etecting errors in serial datacan be paramount in completingan embedded-control design. De-

termining which algorithm to use for de-tecting serial-communications errorsdepends on several factors. Ideally, themethod should require minimal hard-ware and little computational powerfrom your processor and still providehigh-level protection against undetect-ed data errors. The cyclic redundancycheck (CRC) combines all these factorsunder one umbrella. A multitude of CRCflavors exists, including the Dow CRC (8bits), CRC-16, and CRC-CCITT (both 16bits). The CRC-16 uses a 16-bit shift reg-ister and can detect the following errortypes:● any cluster of errors within a 16-bit

section of data,● any odd number of errors within the

data field,● all double-bit errors in the data field,

and● most large clusters of errors.

You can characterize the CRC-16 asboth a polynomial expression and as ahardware-based shift register (Figure 1).You can implement a CRC-16 in amidrange PIC mC with minimal codingand without additional hardware. Select-ing a mC with an on-chip USART, such asthe PIC16C63, eases serial communica-tions. This implementation does not fo-cus on the mathematical proof of a CRC-16’s error-correcting effectiveness. TheCRC algorithm is so effective it’s an in-dustry-accepted method for detectingdata errors. The heart of a CRC-16 algo-rithm is a shift register. You generate theshift register by shifting each data bitthrough the algorithm. In this imple-

mentation, the data shifts the most sig-nificant bit first, one data byte at a time.

Two temporary registers buffer thedata to prevent the shifting from cor-rupting the data. The shift register com-prises two separate 8-bit registers,CRC16_HI and CRC16_LO. The mostsignificant bit of CRC16_HI is the loca-tion of Stage 16 (Figure 1). From the fig-ure and Table 1, you can see that the re-sult of XORing the input data bit and thecontents of Stage 16 of the shift registerdetermines the effect that new data hason the shift register. If the result is a one,then you must complement the contentsof stages 2 and 15 before rotating the newdata into the shift register. If the result isa zero, then the new data can rotate im-mediately into the shift register. Somehousekeeping tips can be helpful here.The data transmitter should generate itsCRC-16 in the same manner as the datareceiver. Also, it’s advisable to clean theCRC-16 shift register before rotating thefirst data bit of the data string into it.

You can represent the CRC-16 algorithm as both a polynomial (a) and a hardware-based shift register (b).

TABLE 1—XOR TRUTH TABLEX Y XOR0 0 00 1 11 0 11 1 0

F igure 1



ideasdesign

How does the CRC-16 identify data er-rors? The simplest method is to attach theshift register to the end of the data string.In this implementation, the CRC16_HIregister should follow the last byte of datasent. The CRC16_LO register follows theCRC16_HI register. If the receiving sys-tem computes a CRC-16 value from allthe data bytes and the attached shift reg-ister (CRC16_HI and CRC16_LO), thenthe resulting CRC-16 code is 0000h. Anynonzero result indicates an error in thedata. In some systems, an error may oc-cur that results in all zeros being sent asthe data and attached CRC-16. This typeof error poses as error-free data. In thesesystems, you can overcome the false in-dication by complementing the CRC-16before attaching it to the data string. TheCRC-16 shift register generated by at-taching the complement is always 800Dh.

The code fragment in Listing 1 gener-ates a CRC-16 shift register on a byte-by-byte basis. You could embed this codewithin serial-receive and serial-send rou-tines to provide a powerful error-detec-tion tool. You can easily generate the

CRC-16 on the fly, thus minimizing theuse of processor resources. You candownload the listing from EDN’s Website, www.ednmag.com.At the registered-user area, go into the Software Center to

download the files from DI-SIG, #2321.(DI #2321).

The circuit in Figure 1 is a low-costfrequency-to-voltage (F/V) convert-er. Using a monostable (one-shot)

multivibrator, the circuit accepts anopen-collector square wave that varies infrequency from 0 to 10 kHz. The one-shot produces a pulse of a fixed widtheach time the input signal triggersit. The result is a variable-frequen-cy, variable-duty-cycle signal at the out-put of the one-shot. The time constantdetermined by R

2C

1, 100 msec, deter-

mines the width of the pulses the one-shot produces. This time matches the pe-riod of the maximum input frequency(10 kHz). The duty cycle of the one-shot’soutput is thus 100% when the input is atits maximum frequency.

The variable-frequency, variable-duty-cycle output of the one-shot is the inputfor the lowpass filter comprising R

3and

C3. The net result is, as the input fre-

quency varies from 0 to 10 kHz, the dcoutput signal varies from 0V to V

CC. You

can alter the circuit to accommodate dif-ferent input frequencies by simply ad-justing the R

2C

1time constant to match

the period of the desired maximum in-put frequency. (DI #2322).

Monostable makes low-cost F/V converterMark Brinegar, Dart Controls Inc, Zionsville, IN

A single CMOS one-shot multivibrator provides a simple and inexpensive frequency-to-voltage con-version function.

10k

IC1CD14538BE

VCC

VCC

R1

C1

10k

VCC

R210k

R3

3 5 11 13 16

6

1 8 12

RxCx

+TR

OPEN-COLLECTORSQUARE-WAVE INPUT

(0 TO 10 kHz)

Q

4

2

0.01 mF

C20.1 mF

C310 mF

DC OUTPUT(0 TO VCC)

F igure 1



LISTING 1—PIC CODING FOR CRC-16 SHIFT REGISTER


ideasdesign




Name

Title

Phone

E-mail Fax

Company

Address

Country ZIP

Design Idea Title





Signed

Date




ideasdesign


The circuit in Figure 1 uses a Dal-las Semiconductor DS1820 one-wiredigital thermometer in a multipoint

temperature-measurement system. TheDS1820 sensor allows distributed tem-perature measurement and uses only onewire for both data communication andthe power supply. You can easily connectthe one-wire interface to a mC (in this ex-ample, a PIC16C63). The application ac-commodates as many as 16 DS1820 sen-sors in a 100m-long network, dubbedMicroLAN by Dallas. Unfortunately, withsuch long wires near high-current pow-er cables, inductively coupled high-volt-age peaks can cause mC latch-up, becausethe transient-voltage suppressor, D

1, can-

not limit the line voltage below9.8V. The interface circuit in Fig-ure 1 prevents such faults.

The sensor needs only one data line,but the interface circuit in Figure 1 needstwo CPU-control signals. The first is theinverted-output data line, connected totransistor Q

1through resistor R

3. If this

line is at logic 1, the sensor’s data lineconnects to ground. Otherwise, resistorR

4pulls the sensor’s data line to 5V. If the

sensor transmits data, the mC capturesthe data via R

2. If an overvoltage peak oc-

curs, R2prevents mC latch-up by limiting

the current to the mC pin. During thetemperature conversion, the DS1820needs an effective pullup circuit to pro-vide an accurate conversion. TransistorsQ

1, Q

2, and R

1provide an effective pullup

function, which the mC activates bygrounding the input signal to Q

3.

The pullup function also improves therising edge of the transmitted data. If thesensor connects to the mC through a longwire, the capacitance of the line degradesthe rising edge of the data signals, because

of the line-capacitance-R4time constant.

The short pulse from the pullup circuitimproves the signal’s rising edge. It’s ob-vious that, when the pullup circuit turnson, Q

3must be off. However, the circuit

protects itself against unintended signalcorruption. If Q

3is open, the power volt-

age does not connect to the sensor’s dataline. If you replace R

4with a 1-mA cur-

rent source, you can obtain effective datatransmission with lengths as great as500m (empirically verified). (DI #2317).

Simple circuit prevents processor latch-upMichal Kobylecki and Wojda Wlodzimierz, MK Design, Warsaw, Poland

A simple three-transistor circuit provide both latch-up protection and signal conditioning in thisone-wire sensor/mmC interface.

DS1820

PIC16C63

D12

1

PSOTO5LC

OUTPUT

INPUT

VCCVCC

R44.7k

Q3 R3 22k

R2 22k

R1 22k

C1

Q1

47 pF Q2

F igure 1

Simple circuit prevents processor latch-up ..........................................................107

Dual one-shot makes rising- and falling-edge detector ..................................108

Simple circuit measures diesel’s rotations per minute ..................................108

Fast, compact routine interfacesEEPROM to mC ............................................112

Photodetector sorts objects........................114

Single-button lock provides high security ..................................................116


March 4, 1999 | edn 107www.ednmag.com

108 edn | March 4, 1999 www.ednmag.com

ideasdesign

The design in Figure 1 is an upgrad-ed version of the circuit in aprevious Design Idea (“Edge

detector runs off single supply,” EDN,Dec 4, 1997, pg 140). It has fewer com-ponents, draws less current, and hashigher input impedance. The circuit usesa 4098 dual monostable multivibratorwith both sections connected. The circuitgenerates a pulse on both the rising andthe falling edges of a signal. The durationof the output pulse is T=0.5R

2C

2. R

1and

C1

provide power-on reset. The circuithas another advantage: It provides twoindependent true outputs (Q1, Pin 6 andQ2, Pin 10) and two independent com-plementary outputs (Q1, Pin 7 and Q2,Pin 9). (DI #2316).

A dual monostable multivibrator provides a convenient means of detecting a signal’s rising andfalling edges.

Dual one-shot makes rising- and falling-edge detectorSanto Camonita, Catania, Italy

RxCx(1)

Cx(1)

RxCx(2)

1TR1

Q1

Q1

R1

R2

1TR2

+TR1

Q2

+TR2

Q2

4098

VCC

VDD

VSS

C2

R2

R11M

C1470 nF

2

14

1

0V

8

16

3

13

4

11IN

5

7

6

9

10

12

OUT1

OUT1

OUT2

OUT2

F igure 1

Y ou may find it useful to measurea diesel engine’s rotations perminute to accurately adjust

the idling or to compare the mo-tor’s speed under hot and cold condi-tions, for example. Not all cars or truckscome with a tachometer. The scheme infigures 1 and 2 allows you to measure ro-tations per minute with a DMM or an os-cilloscope. In Figure 1, a piezoelectricsensor and an alligator clip, fastened di-rectly to one of the four metal fuel pipes,detect the fuel-injection pulses. The piezoelement generates a signal that connectsto the signal-conditioning electronics inFigure 2 through a coaxial cable. The cir-cuit uses a charge amplifier.

IC1, a versatile ICL7611 chosen for its

high input impedance, low bias current,

Simple circuit measures diesel’s rotations per minuteDavid Magliocco, CDPI, Scientrier, France

A piezoelectric sensor and an alligator clip provide an easy means of measuring the rpm of a dieselengine.

NEGATIVE ELECTRODE

PIEZOELECTRIC MATERIAL

F (COMPRESSION)

F

POSITIVEELECTRODE

FUELPIPE

F igure 1



ideasdesign

10M 10M

R2 R3

IN+

IN1SENSOR-CLAMPINPUTS

100k

100k R5

R6

+

1 +

1

100 nF

C1

8

7

4

62

3

100 pF

10M

ICL7611

100k

C2

220 nF

Q1BC847C

Q2BC857C

100kR7

C31 mF R9

5.11M

R8511k

5

6

10M

8

2.87M

4

7

IC2TLC393

VOUT

100k

9V

R4

R1

+

IC1

1N4004

F igure 2

A CMOS integrator and comparator condition the signal from Figure 1’s sensor for interpretation by a DMM or an oscilloscope.

and reasonable power consumption, actsas an inverting current-to-voltageconverter. C

1integrates the high-

dV/dt sensor signal. R1

ensures that theoutput of IC

2is high in the absence of a

signal. You must use high values for R2,

R3, and R

4. The two diodes at the input

protect the amplifier against overvoltagespikes. R

5and R

6create a virtual ground,

so the circuit uses the full common-modeinput range of IC

1. Figure 3 shows an os-

cilloscope trace of the amplifier’s output.The three small peaks between the mainpulses are parasitic and come from theinjection pulses of the other cylinders.You can fine-tune the shape of the signalwith C

1.A value near 1 nF yields a smooth

signal with low amplitude; a value lowerthan 100 pF gives a noisy signal with nar-row pulses. The value for the trace in Fig-ure 3 is 100 pF.

From one vehicle to another, the am-plitude of the signal can vary over an ap-proximately 2-to-1 ratio. You can’t use afixed threshold to shape the signal; eitherthe threshold is too low, and you shapethe parasitic pulses, or it’s too high, andyou obtain nothing. Thus, the signal-conditioning method compares the peakvalue to the average value: Only the mainpeaks are higher than the average value.C

2and R

7ignore the dc component of the

charge amplifier’s output signal, and

transistors Q1

and Q2

charge C3

to thepeak value of that signal. You adjust R

8

and R9

for a 90% ratio, which gives IC2, a

low-power CMOS comparator, a largeenough signal to shape. IC

2delivers a log-

iclike signal that you can measure with a DMM (using the frequency/period

range, or the rotations-per-minute rangeon an automotive DMM), or with an os-cilloscope. (DI #2318).

After conditioning, the main peaks in the sensor signal come from the cylinder under test; the sec-ondary peaks, from the other cylinders.

F igure 3


210.0000 mSEC

500 mV/DIV

CYL1

CYL2CYL3 CYL4

40.0000 mSEC

10 mSEC/DIVSTOP MARKER: 37.4000 mSEC.START MARKER: 33.6000 mSEC.DELTA t: 3.80000 mSEC.1/DELTA t: 263.158 Hz.

90.0000 mSEC


ideasdesign

The code in Listing 1 provides the in-terface between any MCS-51 familyof mCs and a 24C01a/2/4/8/16 I2C

EEPROM. The interface is purely soft-ware-driven, so any mC port pins cancontrol the EEPROM. This code is ap-proximately two times smaller and ap-proximately 20% faster than similar rou-tines published by Atmel Corp (www.atmel.com). Careful coding of low-levelroutines and structural optimization pro-

duce the performance improvements.The code is tuned for a -51 running at

12 MHz, but you can also use it at lowerclock speeds. For higher speeds, you mustadjust low-level routines by inserting“nop”instructions to match I2C-specifiedtimings. The maximum data rate whilereading memory content as 16-byteblocks is as high as 8.1 kbytes/sec. Withminor modifications, you can use theroutines to interface any I2C slave device

to a -51 mC.Listing 1 is available for downloading

from EDN’s Web site, www.ednmag.com.At the registered-user area, go into the“Software Center” to download the filefrom DI-SIG, #2329. (DI #2329).

Fast, compact routine interfaces EEPROM to mmCGrzegorz Mazur, Institute of Computer Science, Nowowiejska, Poland

LISTING 1—I2C EEPROM-mC-INTERFACE ROUTINE



ideasdesign

Photodetector sorts objectsAlan Erzinger, Harris Semiconductor, Palm Bay, FL

M ost object-sensing systemshave problems detecting the pres-ence of an object. The system in

Figure 1 uses an oscillator to ease detec-tion problems and allow sorting. The os-cillator reduces power dissipation in thephotodiode by operating the diode at50% duty cycle. The oscillator also en-ables a 50% increase in the noise-filtertime constant, and it functions as a time-base to allow object sorting. The oscilla-tor chops the photodiode’s bias. The sig-nal the photodetector receives is a squarewave; thus, a filter can remove opticalnoise. You normally need filtering whenlight shines through fans onto the opticaldetector. When required, you can place abandpass filter in series with Q

3’s output.

The oscillator frequency has two lim-its: the response time of the phototran-sistor and the accuracy of the object-sensing system. Q

4and Q

3are connected

in a cascode configuration to minimizethe Miller effect in Q

4. This connection

reduces the pair’s optical transient re-sponse to nanoseconds, thus allowing os-

cillator periods of submicroseconds. Ob-jects on a conveyor belt travel at relative-ly low speeds. You can calculate their ex-pected time in front of the photodetector,t, from t=d/s, where s is the conveyorspeed in feet per second and d is the ob-ject width in feet.

An object 2 in. long with a belt speedof 3.5 ft/sec blocks the detector for 47.6msec. If the oscillator period is 250 msec,the object blocks the detector for ap-proximately 200 periods, so each periodequates to 0.5% length accuracy. The sys-tem senses two objects—one 2 in. longand one much longer—so 0.5% accura-cy is more than adequate. When the de-tector is unblocked, the inverting input ofIC

1is dominant, and it keeps the output

of IC1

low. The low state prevents the os-cillator’s output from reaching thecounter (IC

3). Blocking the detector al-

lows C3

to charge to 5V through R6, and

the noninverting input of IC1

becomesdominant, starting the count. When thedetector is unblocked, the one-shot com-prising R

11, C

5, and IC

4Apulses IC

2Bwith

an end-of-object pulse. The one-shot’strailing edge triggers the counter-resetone-shot comprising R

12, C

6, and IC

4C.

C4and R

6form a nuisance filter that re-

jects short optical noise. The timing issuch to enable a 2-in. object to clear thedetector while both Q

6and Q

7are high.

When the end-of-object pulse coincideswith Q

6high, Q

7high, and Q

8low, the

output of IC2B

indicates a 2-in. object.This situation is the only time windowthat can indicate a 2-in. object. If the ob-ject is longer than 2 in., Q

8goes high, in-

dicating a large object. When the objectclears the detector, the reset one-shot re-sets the counter for another cycle, and Q

3

quickly discharges C4

in preparation foranother cycle. With the component val-ues shown, the system can sense and dis-criminate between objects as short as 2in., separated by 0.1 in. (DI #2325).

An oscillator circuit allows a photodetector to both count and sort objects according to size.

IC5ICM7555 IC3

CD4020

6

2

1

3

R24.3k

4

5

8

5V

5V5V 5V

C20.01 mF

C10.01 mF

C30.1 mF

C41 mF

C50.01 mF

R118k

R3180

Q1SEP8706

Q22N3906

R4100k

R5100k

R65.1k

R818k

Q32N3904

Q4SDP8406 R7

10k

R1010k

IC1CA339

+

2

R9620k

R1110k

IC4A IC2B

SMALLBOX

IC4B

IC4C

C61000 pF

LARGEBOX

R1210k

11

13

6

4

5V

5V5V

5V

IC2A

10CK

Q6

Q7

Q8

RESET

NOTE: ALL ICs NEED TO HAVE A 0.1-mF CAPACITOR FROM VCC TO GND.

CD4093

CD4093

CD4082

CD4082CD4093

F igure 1



ideasdesign

F igure 1 is the block diagram ofan easily programmed, single-but-ton combination lock. You operate

the lock by using a series of short andlong pulses from a momentary switchthat masquerades as a doorbell button.The circuit uses inexpensive CMOS log-ic. The retriggerable timer, T

2, locks out

entries made after the T1code-entry win-

dow, thereby greatly enhancing security.The circuit in Figure 2 operates as fol-lows: The Schmitt-trigger quad NANDgate, IC

1, debounces the code-entry

switch and, with the aid of simple ana-log circuitry, produces separate outputsfor activation times of less than and morethan 0.3 sec. These outputs connect to the

select gate, IC5. The initial entry also sets

timer T1

to enable the decoded decadecounter, IC

3. Each entry clocks IC

3.

As IC3steps through its counts, certain

of its output positions represent “short”and connect to IC

4’s inputs; unconnect-

ed lines represent “long” positions. Thiscoding arrangement sets the combina-tion. Short pulse positions change theaddress of IC

5to select the short input

pulse; otherwise, IC5

selects the longpulse input. The short and long inputs,if present in the programmed sequence,produce an output from IC

5. IC

6counts

the outputs and produces an unlockcommand only if it counts all pulses. Thepower-on-reset circuit ensures that no

compromise of security arises under anyconditions after a power outage. Thetimers are crucial to the high security ofthe system.You must enter the code with-in the 8-sec T

1window. If you make a

mistake, you must wait at least 10 sec forT

2to time out before you make another

attempt. If entries occur continuouslyand less than 10 sec apart, as an intrudermight try, T

2continuously inhibits

counter IC6.

The lock proves to be reliable over sev-eral years of use. The circuit in Figure 2uses an eight-character combination,which you can quickly enter. A shortpulse is a quick jab to the button; a longpulse is only slightly longer. A shorter se-

Single-button lock provides high securityMaxwell Strange, Fulton, MD

A handful of timers and counters configures a highly secure, single-button combination lock.

DEBOUNCEPULSE-WIDTH

SEPARATOR

CODEENTER

LONG/SHORTSELECT

DECODEDCOUNTER

CLOCK

LONG

SHORT

UNLOCKCOMMAND

10SEC

ENTRYWINDOW, T1

(8 SEC)

R-1

R-2

FIRSTTRIGGER

DECODERCOUNTER

1234

5678

ORGATE

CODE-ENTRY

WINDOWTIMER

(T1)

RETRIGGER-LOCKOUT

TIMER(T2)

CLOCK

TRIGGER

TRIGGER

TRIGGERLOCKOUT, T2

(10 SEC MINIMUM)

RESETR-1 COMBINATION

SET(SEE TEXT)

LONG/SHORTADDRESS RESET

R-2

F igure 1


ideasdesign

quence would also be secure; you can im-plement a shorter code by simplytaking the unlock pulse from alower count on IC

6. IC

6’s output returns

low after 10 sec when T2resets. If desired,

you can generate a lock command, whichneed not be secure, by adding the simplecircuit in Figure 3. (DI #2327).

"SHORT" PULSESFROM IC1, PIN 10

~7 mSEC

1

2

14

++

1 mF7

1M

LOCKCOMMAND

R224k

1/4 CD4093

~600 mSEC

3

You can generate a lock command with this additional circuit by rapidly entering four or moreshort pulses.

F igure 3

You program your combination by hard-wiring the IC3-IC4 output-to-input connections, LLSSLSSL, where L and S are long and short inputs, respective-ly, in this example.

CODE-ENTRYBUTTON

100k

100k

3

11

13

1210

16

25

7

1 8 15

14

1

2

3

4

5678

2 91011

12

13

5

34

A B

1 16

13

89

9

15

1514

IC5CD4019

IC6CD4011

16

14

8

13

1

23

4

5

6

A

B

NO

IC2CD4538

IC4CD4072

IC3CD4017

DUAL TIMER(T1 AND T2)

TRIGGER

+

+

10M8.2M

1 mF 1 mF

R-115

8 13

22k 1000 pF

14 16

2

4

4

7

10

1

5

6

9

IC1CD4093

20-mSEC CLOCKDELAY

COMBINATION SET(LLSSLSSL SHOWN)+

+

+

14

7

1

9

1214

8

13

100k

240k

22k43Ok100k

0.082 mF

1 mF

1 mF C

D

7

11

10

+"LONG"(>0.3 SEC)

"SHORT"(<0.3 SEC)

0

0

~7 mSEC0

LONG/SHORTADDRESSLINES

UNLOCKCOMMAND

+

+

+

++

POWER(5 TO 15V)

10 mF20V

TANTALUM

22 mF20VTANTALUM

POWER-ONRESET

1M

22k

220k

+

NOTE: ALL DIODES=1N4148.R-2

0

F igure 2



ideasdesign




Name

Title

Phone

E-mail Fax

Company

Address

Country ZIP

Design Idea Title





Signed

Date




Y ou can run initial high-level sim-ulations of custom numerical algo-rithms, such as digital filters, using

floating-point numbers in an environ-ment such as C or Matlab. Unfortunate-ly, you won’t see include fixed-point ef-fects, such as truncation due to limitedprecision and register overflow, until youuse a Hardware Design Language (HDL),such as Verilog or VHDL. However, atechnique that models these effects inC—the function “bit_limit” in Listing1—provides faster execution and betterportability than HDLs and allows earlyexploration of the trade-off between buswidth and performance.

Figure 1 shows a flow diagram that cal-culates the output E=A/4+A•B. Table 1shows the effect of the chosen bus width.For example, the output of the multipli-er truncates to 10 bits, and the output ofthe adder truncates to 9 bits. In this ex-ample, when input A=201.8 and inputB=0.19, the output E=87.5; an ideal mod-el without truncation would give 88.792.

Listing 1, the ANSI C code for thebit_limit function, shows how the codetruncates. The code first converts float-ing-point numbers a_fl and b_fl to justi-

ideasdesign


Model fixed-point DSP arithmetic in C ..............................................125

Two ADC channels double sensorprecision ........................................................126

Transistor pair lowers PWM IC’s start-up current ............................................128

Autozero a position-sensing detector ....130

OTP mC controls Boomer amplifier ........132

LED driver displays standing-wave ratio ......................................................134

Comparator provides stable hysteresis........................................................136

Model fixed-point DSP arithmetic in CRoger Maher, SSL Ltd, Dublin, Ireland

March 18, 1999 | edn 125www.ednmag.com

LISTING 1—FUNCTION “BIT_LIMIT” C CODE


fied integers by scaling. Themacro PREC sets the number ofbits that the code uses to store thefractional part of the input, which are thebits to the right of the “binary” point.The bit_limit function truncates a_fl to8 bits on the left of the binary point andto 0 bits on the right; the respective fig-ures for b_fl are 0 and 4 bits. Because thecode stores the numbers as normal inte-gers, the standard operators can performaddition and multiplication. However,the code must rescale the result of a mul-tiplication because both operands arejustified. The bus widths are set at pointsA, B, C, D and E; the code displays the bit-limited value of E and compares this val-ue to the result from full-precision arith-metic.

You can handle signed arithmetic us-ing 2’s complement numbers by extend-ing the bit_limit function to sign-extendthe MSB after each truncation. You canperform rounding using the followingstatement:

bit_limit(8, 0, A + 0.5•(1<PREC)).The number of bits in the “int long”

data type on the simulation platform sets

the major limitation of this technique.Normally, the number is 32 bits, so allnumbers in the simulation, including theunscaled result of a multiplication, mustbe less than 231. You can slightly extendthis range by using “unsigned int,”or youcan double the range by using “int longlong” when this type maps to 64 bits.

Listing 1 is available for downloadingfrom EDN’s web site, www.ednmag.com.At the registered-user area, go into theSoftware Center to download the filefrom DI-SIG, #2328. (DI #2328)

ideasdesign

The accuracy of the on-chip ADCs of numeroussmall and inexpensive 8-

bit mPs is well-suited for manyapplications. However, somesituations benefit from just alittle more accuracy from a resistive po-sition sensor, for example. The resistivecircuit in Figure 1 uses two ADC pins ona mP to double the precision of a resistiveposition sensor. In effect, the 8-bit ADCbecomes a 9-bit ADC. The resistive partof the circuit shown in Figure 1 costs aslittle as $3; the cost is higher if you use aprecision potentiometer as the positionsensor.

The concept behind using twoADC channels is simple. One ADC inputtakes direct measurements of the positionsensor. The second ADC input measuresthe voltage out of a second potentiome-ter that is a 1/2 bit behind the first input.

This scheme creates a “phasing” of thetwo analog-to-digital results (Table 1).Adding the two results produces a 9-bitanswer that is limited to a value of 510.

To set up the circuit for op-eration, you will need to ac-curately measure V

REF, which

is 5.000V in this case, and setADC

1(VR

1) to a known volt-

age, 3.000V in this case. Then,adjust ADC

2(VR

2) according to the fol-

lowing equation:

Thus, an ADC2=2.990V sets input-chan-

nel ADC2

to a 1/2-bit lag. (DI #2332)

Two ADC channels double sensor precisionLuke J Barker, Reinke Manufacturing Co Inc, Deshler, NE

Using two ADC pins on a mmP doubles the preci-sion of a resistive position sensor.

ADC1

ADC2

5V

VR1POSITIONSENSOR

VR215 TURN

10k3006-103

(BOURNS INC)

Binary pointA 1 1 0 0 1 0 0 1 1 1 0 0 201B 0 0 0 0 0 0 0 0 0 0 1 1 0.1875C=AB 0 0 1 0 0 1 0 1 1 0 1 1 37.5D 0 0 1 1 0 0 1 0 0 1 0 0 50E=C+D 0 1 0 1 0 1 1 1 1 0 0 0 87.5

A simple flow diagram implements the output E=A/4+A•B.

A8

E= +ABA49

34

2

4

B

+

C

10

D

SEVENMSBs

TABLE 1—TRUNCATION EFFECTS BASED ON BUS WIDTH

F igure 1

F igure 1


.V990.22

5/255000.3

2

255/VADCADC REF

12

=łŁ

=

łŁ=

1

1


ADC1

ADC1

9-BITRESULT

0 1 1 2 2 3 . . .

0 0 1 2 2 3 . . .

0 1 2 3 4 5 . . .

253 254 254 255 255

253 253 254 254 255

506 507 508 509 510

TABLE 1—ADC “PHASING”


ideasdesign

A n auxiliary windingusually provides powerfor the popular

UC384X-based offlineswitch-mode power supplies(SMPSs). This winding feedsthe main PWM controllerduring steady-state opera-tion. However, the controlleralways needs a small start-upcurrent, which clearlyplagues the efficiency in verylow-power standby SMPSswith P

OUT=500 mW, for ex-

ample. Any wasted sourcepower, such as for the start-up network and controllersupply, adds to the powerdrawn from the mains andsignificantly degrades theoverall efficiency. Obtainingan acceptable efficiencyat high line voltage rep-resents a tough designtask. Some tricks totallystop the start-up current byusing a high-voltage bipo-lar or MOSFET (Reference1). However, the addition ofa high-voltage componentburdens the bill-of-materi-al cost of a small-powerSMPS.

An alternative and inex-pensive solution allows youto program the start-up cur-rent at any value, whateverthe PWM IC (Figure 1). Im-plemented around two low-voltage off-the-shelf bipolar transistors,Q

1and Q

2, the circuit brutally connects

the controller to bulk capacitor C1

whenC

1’s voltage level is adequate. This level

determines the C2V product that islarge enough to feed the PWM IC untilthe steady-state operation takes over. Thedesigner can then select any small start-up current to charge the bulk capacitorin agreement with time-constant recom-mendations. During the charge, seriespnp transistor Q

1is locked off, which

prevents any current consumption fromthe main controller. When the voltagereaches a defined level, Q

2starts to pull

Q1’s base to ground. Q

1’s collector volt-

age rises and further saturates Q2through

the reaction resistor, R1. The charged bulk

capacitor is now fully connected to thePWM IC, which starts to oscillate. A fewcycles later, the auxiliary winding takesover, and Q

1stays on.

The level VTHRESHOLD

at which Q2

turnson is simply given by:

If you assume a linear charge from thestart-up network, R

4+R

5, then the time at

which Q2

starts to conduct is equal to

where

With the values in Figure 1, C1

connectsto the IC when its voltage reaches 17V,which occurs in less than 350 msec atVDC=350V. The circuit offers betterthan 50% efficiency at high-line(250VAC), drawing less than 1W for a500-mW output power. The MMG-05N60D insulated-gate bipolar transis-tor (Motorola Semiconductor, http://mot-sps.com/scg/) also contributes tothe circuit’s performance because of itslow capacitive parasitic elements, in-cluding a 5-nC gate charge. The circuitthus minimizes commutation losses. Fig-ure 2 shows the start-up phase of thelow-power SMPS at very low line, 70V ac.(DI #2330)

Reference1. Basso, Christophe,‘Low-cost MOS-

FET quashes power resistor’, EDN, June9, 1994, pg 140.

Transistor pair lowers PWM IC’s start-up currentChristophe Basso, Motorola Semiconductor, Toulouse, France

A pair of bipolar transistors, Q1 and Q2, work with C1 to turn any PWM controller into a low-current startupdevice.

A low line voltage, 70V ac, start-up sequence of the two-bipo-lar network shows the charging of C1, the turn-on point of Q2,and the resultant VCC for the UC3845 PWM IC.

+

++

HIGH-VOLTAGE DC RAIL

IC1UC3845

330kR4

330kR5

5V AT100 mA

100 mF/10V

470 mF/10V

10 mH1N5819

1N4148

LP=6.5 mH.1:0.055 (POWER)

1:0.12 (AUX)

5.1V

MOC8106

2

3

4

8

7

6

5

20k

1 nF 470 pF 10

1k

1k

MMG05N60D

10 mFC1

100kR1

R2

3.3MR3

Q22N3904

Q12N3904

10 nF

100k

1.5k

F igure 1


.R

RR)Q(V

4

541BE

+•

,I

VC

UPSTART

THRESHOLD1

-

•

.RR

VDCI

54UPSTART +

»-

F igure 2

VC1


ideasdesign

A utozeroing schemes can be nec-essary to minimize the input-offsetvoltages of position-sensing detec-

tors (PSDs), particularly when you usethese detectors with high dc gain. PSDsare useful optical transducers for accu-rately measuring displacement. In prac-tice, their typical configuration is as a dif-ferential current-to-voltage circuit(Figure 1). The ratio of the photocur-rents I

1-to-I

2linearly divides between the

electrodes, proportional to the incidentlight beam. The magnitude of the pho-tocurrents is a function of the light in-tensity.

Although PSDS are photodetectors,using them with high dc gain can quick-ly get you into trouble. Input-offset volt-ages can easily multiply due to the rela-tively low sheet resistance between pins1 and 2, which typically ranges from 5 to100 kV. Consider the following nodalequations:

An offset multiplication occurs becauseof the low intrinsic diode impedance, R

S,

of the PSD, and the high values of RF. For

normal photodetectors, RS

is very high,and, therefore, no multiplication occurs.FET-input op amps are usually the choicefor photodetector circuits because theyhave a higher input impedance and low-er current-noise density at high-imped-ance levels than their bipolar counter-parts.

For a typical pair of FET op amps mis-matched by ±3 mV and with an R

Fof 1

MV and sheet resistance of 20 kV, VOUTB

would be 20.303V, and VOUTA

would be0.303V. For a theoretical pair of op ampsmismatched by ±10 mV, an R

Fof 1 MV,

and a sheet resistance of 20 kV, VOUTB

would be 20.001V and VOUTA

would be0.001V. Ultimately, it would be nice to usea low-noise, low-bias-current amplifierwith a very closely matched front end.However, it is a much more difficultprocess to match the input FET differen-tial pair than that of a bipolar transistor.Nevertheless, this circuit shortcomingdue to the sheet resistance is also the keyto its success; you can force the offsetvoltage to be equal.

You can accomplish this goal by sam-

pling and integrating the difference of thetwo input-offset voltages and forcing thepositive input of Amplifier A with the re-sult (Figure 2). The two amplifier out-puts converge to the input offset voltageof Amplifier B with the difference in thetwo output voltages equal to the offset ofamplifier C. V

OUTAreduces to

and VOUTB

reduces to

Note that biasing the wrong op ampcauses the two outputs to diverge, andyou must choose an op amp for Ampli-fier C on the merits of its dc specifica-tions.

The second approach to forcing theoffset voltage to be equal is to use a po-tentiometer to adjust one of the op ampsat its offset-adjustment pins. This circuitconverges or diverges in a manner simi-lar to that depicted in Figure 2. (DI#2331)

Autozero a position-sensing detectorJames Zannis, Renishaw S A, Champs-sur-Marne, France

A differential current-to-voltage circuit is the typical configuration for aposition-sensing detector (PSD).

Sampling the difference of the two input-offset voltages, integratingthese voltages, and using the result to drive the positive input ofAmplifier A causes VOUTB and VOUTA to converge to the input offset voltageof Amplifier B and to differ by the offset of Amplifier C.

_

+

_

+

_

+

VOSB

_

+

VOSA

VOUTB

VOUTA

V+

V1

V+

V

B

VOUTB=I2RF+[1VOSA(RF/RS)+VOSB((RS+RF)/RS)]

VOUTA=I1RF+[1VOSB(RF/RS)+VOSA((RS+RF)/RS)]

RF

RS

RF

I2

I1

PSDV+

A

_

+

_

+

_

+VOSB

_

+

VOSA

VOUTB

VOUTA

V+

V+

V1V1

_

+

V+

V

B

RF

RS

RF

I2

I1

PSDV+

A

100k

100k

VOUTB=I1 RF+VOSB

VOUTA=I1 RF+VOSB+VOSC

C

CF igure 1

F igure 2


. R

)RR(V

R

RV

RIV

S

FSOSB

S

FOSA

F2OUTB

œß

øŒº

Ø +•+•

+•=

1

. R

)RR(V

R

RV

RIV

S

FSOSA

S

FOSB

F1OUTA

œß

øŒº

Ø ++•

+•=

1

,V VRIV OSCOSBF1OUTA ++•=

. VRIV OSBF1OUTB +•=


ideasdesign

F igure 1 shows a circuit that usesa one-time-programmable (OTP)mC in an unusual way. A

COP8SGR7 mC uses digitalsignals to “bit-bang”an LM4835 (dubbed“Boomer” by National) amplifier. Al-though the amplifier is designed for po-tentiometer control, you can modify it tomake it a fully digitally controlled part.Figure 2 shows the flow chart for the con-trol process.A PWM signal and a lowpassfilter allow you to use digital signals tocontrol the amplifier. The technique setsthe mC in processor-independent mode.You load the values affecting the duty cy-cle into the appropriate timer registers.When a control bit goes high, the mC de-livers a PWM signal.

The PWM signal goes to a first-orderlowpass filter. The output from the filter

Instead of tweaking potentiometers, you can use pushbuttons and a mmC to control National’s Boomer amplifier IC.

Depressing the volume-control pushbuttons sets the duty cycle of the PWM signal the COP8SGR7mmC generates.

OTP mmC controls Boomer amplifierWallace Ly, National Semiconductor Corp, Santa Clara, CA

PB1

PB2

5V

SHUTDOWNGAIN SELECTMODEMUTEDC VOLRIGHT DOCRIGHT INBEEP INLEFT INLEFT DOC

RIGHT OUTRIGHT OUT

RIGHT GAIN2RIGHT GAIN1

BYPASSHP SENSE

LEFT GAIN1LEFT GAIN2LEFT OUT+

LEFT OUT1

GND0

GND

GND1 GND2 GND3 GND4

+

+

+

+

VDD2 VDD0 VDD1

0.1 mF

0.068 mF

0.068 mF

220 mF

1 mF

220 mF

0.1 mF

0.1 mF

20k

20k

20k

20k

R1320k

1k1k

20k

20k

200k

200k

0.33 mF

10 mF

1 mF

U6

U5

5V

LEFT IN

RIGHT IN

COP8SGR728M8mC

VCC

5V

1k

HEADPHONE SWITCHSW1

3

LM4835BOOMER AMPLIFIER

20k

20k 20k

+

1

+

1

RIGHT SPEAKERSPEAKER

4V

SPEAKER4V

LEFT SPEAKER

+

HEADPHONEOUTPUT

HP+

HP1

5V

0.33mF

BEGIN

VOLUME=0

NO

INCREASEVOLUME VOLUME++YES

DECREASEVOLUME VOLUME11YES

TIMERREGISTERS=VOLUME

IS BUTTON A ON?

IS BUTTON B ON?

F igure 1

F igure 2


The circuit in Figure 1 uses anLM3914 LED driver to directly dis-play standing-wave ratio (SWR) in

a low-cost, rugged instrument. TheSWR-sensing head is derived from theARRL Antenna Handbook in an articlethat describes the tandem match. Theforward voltage and reflected voltage(V

F+V

R) signal drives Pin 6 (R

HI), and

the VF2V

Rsignal drives the normal sig-

nal input at Pin 5. You can use this basicarrangement to display the ratio of twovoltages in other applications. The in-ternal circuit of the LM3914 comprises10 voltage comparators that compare theinput voltage at Pin 5 to an internal, 10-step, linear-voltage-divider string be-

tween Pin 6 (RHI

) and Pin 4 (RLO

). Thevoltage-divider levels, V

N, are

VN=V

REF2n/10, where n is the voltage-

divider step from 1 to 10, and VREF

is thevoltage between pins 6 and 4.

When the signal voltage on Pin 5 sat-isfies the equality in the following equa-tion, the nth LED energizes in the dot-mode display (with approximately 1 mVof hysteresis).

If you force VREF

to equal VF+V

Rand

the voltage at Pin 5 to equal VF2V

r, you

can arrange the terms as in the follow-ing equation.

where VF+V

RV

F2V

Ris the definition of

the SWR. Two sections of the quad opamp, IC

1, buffer the forward and reverse

voltages developed in the SWR bridge.The remaining two sections serve as adifference amplifier to produce the volt-age V

F2V

Rand as a noninverting sum-

ming amplifier to produce the voltageV

F+V

R. Even though the circuit does not

use the internal voltage regulator, youmust properly terminate it to establishthe LED current. (DI #2324).

LED driver displays standing-wave ratioRichard Panosh, Vista, Bolingbrook, IL

You can use an LED-driver IC to produce a thermometer-type indicator for the standing-wave ratio in RF systems.

VF INPUT

VR INPUT

_

+

_

+

_

+

9

10

8

_

+

13

12

14

100k

IC1D

100k

IC1C

100k

100k

100k

100k

100k

100k

100k

200k

2

3

1 VF-VR

11

4

IC1AOP491

76

5

100k

IC1B 820

1

2

3

4

5

6

7

8

9

9V

10k

LO

1V

+V

RLO

SIG

RHI

REF

ADJ

MODE

IC2

LM3914

HI

LED1

18 12

11

17 13

16 14

15 15

14 16

13 17

12 18

11 19

10 20

K

K

K

K

K

K

K

K

K

K

A

A

A

A

A

A

A

A

A

A

10

9

8

7

6

5

4

3

2

1

+10 mF

SWR

6.4-TO-1

3.9-TO-1

2.7-TO-1

2.2-TO-1

1.8-TO-1

1.5-TO-1

1.3-TO-1

1.2-TO-1

1.1-TO-1

1-TO-1

NOTE: 50 mV<VF+VR<7.5V.

F igure 1

.V10

1NVV

10

NREF5PINREF ·

+<£·

,1N

10

V

V

VV

VV

N

10

5PIN

REF

RF

RF

+>=

+‡

1

ideasdesign

is a dc voltage, whose amplitude is pro-portional to the duty cycle of the PWMsignal. The processor-independent modeallows the mC to perform other dutiesand calculations while it generates thePWM signals. With the COP8SGR7 mC,three PWM outputs are available; there-

fore, the mC can control three amplifiers,or six channels of audio. The mC de-bounces the two (volume-up and -down) pushbuttons. The controller alsohandles the mute, shutdown, beep, vol-ume, and headphone functions. You candownload the C code for controlling the

mC from EDN’s Web site, www.edn-mag.com. At the registered-user area, gointo the Software Center to download thefiles from DI-SIG, #2326. (DI #2326).




ideasdesign

Comparator provides stable hysteresisFernando Garcia, Lucent Technologies, Brownsville, TX

Unless a voltage-comparator cir-cuit is sampling an extreme-ly clean signal, the compara-

tor always requires some hysteresis.Traditional comparator circuits obtainthe required hysteresis by using positivefeedback derived from the ratio of two re-sistors. The voltage at the noninvertinginput is the superposition of a fraction ofthe input and output voltages, each di-vided by its respective resistor ratio. Withan inverting comparator, the noninvert-ing input usually connects to a voltagereference with reasonably low imped-ance, and you can choose the hysteresis-setting resistors without concern forloading. However, for the noninvertingcomparator, the input voltage comesfrom the actual source the circuit is sam-pling. This source has a series impedance,R

SOURCE, which can be a significant

fraction of the input resistance R6

(Figure 1). This impedance may not berepeatable or may change value withchanging circuit conditions; therefore, itmay result in hysteresis errors.

Although you can change the feedbackand input resistor values to minimize thesource-impedance impact, you face apractical limit on the increases, becausethe value of the feedback resistor that theresistor requires to maintain the properresistor ratios can become excessivelyhigh. Traditionally, you could use an opamp configured for unity gain to bufferthe high-impedance source from thecomparator. However, in some applica-tions, cost, board-area, or current-con-sumption constraints may precludeadding an op amp. The circuit variant inFigure 2 eliminates the source-imped-ance problem. The voltage source undercomparison connects directly to the non-inverting input. Hysteresis does not comefrom resistor feedback, but rather fromMOSFET Q

1. If the voltage you are sam-

pling is less than the threshold, the com-parator’s output is low, and Q

1turns off.

The comparator’s inverting input es-sentially sees a reference voltage identi-cal to the reference voltage in Figure 1.

However, when the voltage exceeds thethreshold, the comparator’s output goeshigh, turning on Q

1. The MOSFET shorts

out the lower portion (R5) of the resistor

divider. This action has the net effect oflowering the reference voltage to thecomparator’s inverting input. The differ-ential voltage thus increases, providingthe required hysteresis. The source im-pedance basically sees only the compara-tor’s input impedance. This impedance isextremely high, so the source-impedance

impact on offset is low. Most small-signalMOSFETs can work in this application,provided that the R

DS(ON)is at least one

order but preferably two orders of mag-nitude lower than the resistor it mustshunt. This application requires a logic-level FET that turns completely on withV

GS=5V. (DI #2335).

Source impedance has virtually no effect in this circuit; hysteresis comes from manipulating thethresholds at the inverting input.

Finite source impedance can provoke large errors in the hysteresis that you carefully calculateusing resistor feedback ratios.

2

18

5VR2

R3

V1

D1

R4

R6

R1

R5

22k22k

4.7M

39k

47.5k

47.5k

9

10

4

V1

V28

4 LM339

LM385M-1.2

OUTPUT

2

1

2

1IC1ARSOURCE

2

18

5VR2

R3

V1

D1

R4

R1

22k

22k

44.2k

R5

3

1

Q1

2

3.32k

47.5k

9

104

8

4

LM385M-1.2

OUTPUT2

1

RSOURCE

2N7002/PLP

V1

V2

LM339

2

1IC1A

F igure 1

F igure 2



ideasdesign




Name

Title

Phone

E-mail Fax

Company

Address

Country ZIP

Design Idea Title





Signed

Date




A recent Design Idea de-scribed a method forproducing an analog

voltage from one digital output ofa mC (“Generate an analog signalwith a mC,”EDN, Oct 22, 1998, pg108). The method involves gener-ating a PWM output with a con-trolled duty cycle and filtering theswitching waveform with a simplesingle-pole RC filter. Althoughthis method provides an accuratedc output with 8 bits of resolu-tion, it requires a filter with a lowcutoff frequency to reduce theripple to less than 1 LSB.

An alternative method doesn’thave this problem. The circuit inFigure 1 and the correspondingcontrol program borrow a tech-nique from direct digital synthe-sizers. The technique consists of anumerically controlled oscillator (NCO)that distributes the duty cycle as evenly aspossible across the main period of theoutput, which is 256 clocks for both theNCO and PWM approaches. Figure 2aand Figure 2b illustrate the operation of

the NCO and the PWM methods, re-spectively, with the duty cycle set to10/256. Figure 2a’s NCO digital outputhas the same duty cycle as Figure 2b’sPWM output but distributes the duty cy-cle evenly across the period.

The benefit of the NCO is that the rip-ple amplitude after filtering is almostconstant with changes in the duty cycle.In contrast, the PWM method has a rip-ple amplitude equal to that of the NCOapproach at the lowest duty cycle, and theripple worsens at midscale.

Figure 3 compares the expected out-put for each of the two methods using thesame duty cycle as before, 10/256. A sim-ple IIR filter that simulates a single-poleRC low-pass filter, performed the filter-ing. The time constant for this filter is 256

clocks. This figure shows that the NCOoutput has much lower ripple than thePWM output at this output duty cycle(Figure 3a). As the DAC value approach-es midscale, which corresponds to a dutycycle of approximately 128/256, thePWM ripple gets progressively worse, butthe NCO ripple improves by as much asa factor of 2 (Figure 3b).

The accompanying listing to Figure 1runs on the PIC16C711, but, because theroutine doesn’t use the ADC and theTMR0 interrupts, you can use it with oth-er processor types. (You can downloadthe program from EDN’s Web site,www.ednmag.com.At the registered-userarea, go into the Software Center todownload the file from DI-SIG, #2346.)

The DAC routine uses only two regis-

April 15, 1999 | edn 129www.ednmag.com

ideasdesign


NCO technique helps mC produce clean analog signals ..................129

mC generates musical sounds ................132

Continuity buzzer is frugalwith power ....................................................134

Stereo jack adds no-costpower/logic control ....................................136

S/H circuit minimizes aperture ................140

NCO technique helps mmC produce clean analog signalsSteve Ploss, Veridian Corp, Wright Patterson AFB, OH

10k

150

15 pF 15 pF

RA2/AN2

MCLR!/VPP

VSS VDD

C1

OSC1/CLKIN

OSC2/CLKOUT

OUTPUT

PIC16C711

0.01 mF

0.03 mF 0.01 mF5V

5V

20 MHz

6.8k1.2k

1

4

5

16

15

14

F igure 1

A numerically-controlled-oscillator (NCO) technique allows a mmC and a handful of passive components tooutput analog signals that, after filtering, have a ripple amplitude that is constant over changes in dutycycle.

130 edn | April 15, 1999 www.ednmag.com

ideasdesign

ters; the phase accumulator and the hold-ing register form the DAC input val-ue. Two additional registers providesine-wave values to the DAC routine. Oninitialization, the phase accumulator setsto zero, and the DAC value sets to mid-scale (0x80). On each update, the value ofthe DAC register adds to the phase accu-mulator. When the phase accumulatorrolls over—an event signaled by the set-ting of the carry bit—the circuit sets theoutput high for one update. The processthen continues indefinitely. To generate asine wave, the program counts the num-ber of times it loops and every 32nd timeit retrieves the next value from the look-up table. The table holds 16 values of afull cycle, so the period of the sine waveis 512 times the loop time, plus a smallamount of time for the branch out of theloop. With a 20-MHz crystal, the looptime is approximately 3.5 msec, and thesine-wave frequency is approximately625 Hz.

To output an analog waveform, youneed only to change the value of the DACregister. This change can happen atany time. The analog output al-most immediately starts updating. Whenyou use this method for your own appli-cation, remember to update the DACoutput as often as possible to lower theripple amplitude. The rate need not beprecise, because you are merely setting aduty cycle—the period of which is rela-tively unimportant. More likely, you needto control the period of your analogwaveform.

If you can afford to use a mC with atimer interrupt, it’s best to use that in-terrupt to determine when to change tothe next DAC value. The rest of the time,you can continuously update the out-put. If you don’t want to use the timerinterrupt, you can update the DAC aspart of a polling loop, as shown in thisexample, waiting for a loop counter toreach a predetermined value beforechanging the DAC value. However, youmay want to make sure that the branchfrom the polling loop always takes thesame amount of time, so that the DAC-value changes occur at a constant rate.Also, if the branch is going to take acomparatively long time, consider set-ting the output bit to a high-impedancestate for the duration of the branch. If

you do not take this precaution, the out-put will hold the last value—whetherhigh or low—for the duration of thebranch and could produce a transient on

the filter output. (DI #2346)

The NCO digital output (a) has the same duty cycle as the PWM output (b) but distributes the dutycycle evenly across the period.

The output ripple that results from the numerically-controlled-oscillator (NCO) method—for exam-ple, at a duty cycle of 10/256—is much lower than that of the PWM method (a). As the DAC valueapproaches midscale—a duty cycle of approximately 128/256—the PWM ripple gets progressivelyworse, but the NCO ripple improves by as much as a factor of 2 (b).

F igure 2

F igure 3


OUTPUTLEVEL(V)

OUTPUTLEVEL(V)

FILTERED OUTPUT(V)

FILTERED OUTPUT(V)

5

2.5

0

0 50 100 150 200 250

0 50 100 150 200 250

0 500

200 400 600 800 1000 1200 1400 1600 1800 2000 2200

1000 1500 2000 2500

5

2.5

0

0.4

0.3

0.2

0.1

00

0

5

2

OUTPUT UPDATES

OUTPUT UPDATES

OUTPUT UPDATES

OUTPUT UPDATES

(a)

(b)

(a)

(b)


ideasdesign

M any modern devices send au-dible signals to their op-erators to indicate some

of the predetermined conditions orstates of the system under control. Toavoid annoying human sensibilities,these sounds should match the musi-cal scale. Several chips on the marketprovide such sound capabilities; forexample, a programmable sound gen-erator or an ISD1016 voice messager.The circuit in Figure 1 does not use adedicated sound generator but rathergenerates sounds using software rou-tines. The circuit uses an inexpensiveMC68H705J1A mC and saves addi-tional expense by eliminating the needfor a sound chip. In Figure 2a, a noterepresents the pitch of each musical

tone; Figure 2b shows the dura-tion of the tone.

The first step in programminga sound-output system is choos-ing the type of sound signal: in-dividual sounds or a section ofa melody. As an example, con-sider a portion of the song Jin-gle Bells. Write the sequences ofpitches and durations into thetables of Figure 2 and then putthem into memory in addressesaMEL and aDUR (Listing 1).The addresses of these tables oc-cupy the end of the availableEPROM space. The commen-taries in Listing 1 explain thestructure of the subroutineMELODY. The std-jia.asm file is

An inexpensive mmC can provide programmable sound outputwithout the need for expensive sound chips.

A musical passage consists of pitches (a) and durations of the notes (b); you enter these values into the mmC’s pitch and duration registers.

mmC generates musical soundsAbel Raynus, Armatron International, Melrose, MA

+

9

MC68HC705J1A

SOUNDOUTPUT

17A1

1

2

5V

R1100k

20 RESET

10

4 MHz

C11.5 mF

OSC1

OSC2

VSS

VDD

NOTEC D E F G A B C D E F G

DO RE MI FA SOL LA TI DO1 RE1 MI1 FA1

264 297 330 352 396 440 495 528 594 660 704

SOL1

792

3.78 3.36 3.04 2.84 2.51 2.3 2.0 1.9 1.68 1.5 1.4 1.26

1.89 1.68 1.52 1.42 1.26 1.14 1.01 0.94 0.84 0.76 0.71 0.63

189 168 152 142 126 114 101 94 84 76 71 63

f, Hz

T, mSEC

1/2T, mSEC

NUMBER TOPUT INTO NR

NOTE SHAPE

DURATION WHOLE HALF QUARTER EIGHTH 16TH

PUT INTO DR 16 8 4 2 1

(a)

(b)

DFACEG

CEGBDF

F igure 1

F igure 2


ideasdesign

LISTING 1—ROUTINE FOR GENERATING MUSICAL SOUND

the standard address list of the registersand the bytes of the mC. You can down-load Listing 1 and its associated files fromEDN’s Web site, www.ednmag.com. At

the registered-user area, go into the Soft-ware Center to download the files fromDI-SIG, #2336. (DI #2336).

Continuity buzzer is frugal with powerHans Krobath, EEC, Nesconset, NY

The continuity detector in Figure1 is based on W Dijkstra’s “Fleapow-er circuit detects short circuits”

(EDN, July 2, 1998, pg 122). The buzzer

indicator allows you to devote full atten-tion to making the connection withouthaving to observe an LED. The circuitalso consumes less power than Dijkstra’s

circuit. Power comes from two AA orAAA cells, which last for a period equalto their shelf life. Current consumptionis less than 2.5 mA when the circuit de-



ideasdesign

This audible-signal continuity tester consumes little power and allows you to detect opens and shorts without observing an LED.

+

1

IC1

IC1=AD 0P150, MAXIM MAX495, BURR-BROWN OPA340,NATIONAL LMC272 (1/2 OF DUAL), TI TLC272C (1/2 OF DUAL),TI TLV2221 (SEE DATA SHEET FOR PINOUT), PHILIPS NE5230.

Q1

R456k

R23.3k

R5100k

R610k

S1

R1100RX

R3220

R71.5k

3

24

67

2N3904

PANASONICP9912 OR

PROJECTS UNLIMITEDAT-138

RX=LESS THAN 12V=BUZZ.NOTES:

221.5V

F M

G

3V

OP150

+

1

F igure 1

Stereo jack adds no-cost power/logic controlGary O’Neil, IBM Microelectronics, Research Triangle Park, NC

M any battery-powered devicesuse peripherals that require onlytwo conductors to complete their

interfaces.You can use stereo phone jacksand monaural plugs to perform power-or logic-control functions in addition tocompleting their required I/O connec-tions. Monaural plugs short-circuit thering and sleeve of stereo jacks. You canplace the ring connector, normally con-sidered a redundant ground return, into

service as an spst switch. A simple wire-less transceiver illustrates how you canuse stereo jacks for switching withmonaural plugs, stereo plugs, or both(Figures 1 and 2). Using the design inFigure 1, you can connect the battery re-turn to the ring of stereo jacks servingone or more I/O devices. The circuit inFigure 2 connects the returns of individ-ual circuits to the ring.

With this scheme, power control be-

comes automatic with the plugging andunplugging of devices using monauralplugs, by virtue of the ring-to-sleeveshort circuit. Three examples illustratethe principles of operation. In the first ex-ample, the transciever comprises a trans-mitter, a receiver that contains an audioamplifier, a battery supply for power, andtwo stereo phone jacks (J

1and J

2) for

transmitter modulation and audio out-put, respectively (Figure 1). J

1’s tip con-

tects continuity and less than 1.7 mA foran open circuit. Open-circuit voltage isless than 100 mV, and short-circuit cur-rent is less than 1 mA.You can use a num-ber of op amps for IC

1, provided that the

specs indicate rail-to-rail operation witha low-voltage single supply.

The piezo oscillator driver uses only700 mA when operating and consumesonly Q

1’s leakage current when it is not

operating. This type of piezo transduceris a passive, resonant-feedback type,

which provides high power efficiency andlow-voltage operation. With R

Xvalues

greater than approximately 12V, the in-verting input of the op amp is at a high-er potential than that of the noninvertinginput. The resulting output is 0V plus thesaturation voltage of the output stage.This output provides no bias currentthrough R

5and thus keeps Q

1cut off.

With RX

values lower than approximate-ly 12V, the inverting input of the op amphas a potential lower than that of the

noninverting input. The resulting outputis 3V minus the saturation voltage of theoutput stage. The approximately 3V out-put biases Q

1into the linear region. Q

1

and the piezo transducer, with their as-sociated feedback, oscillate at their reso-nant frequency. Most transducers and thelisted op amps operate with supply volt-ages as low as 2V. (DI #2350).


nection carries the modulation input tothe transmitter. This input could be akeying line for CW (continuousmodulation, for Morse code); adigital modulation interface; or an ana-log input, such as in a wireless micro-phone. The output of the audio amplifi-er (demodulated digital data, controltones, voice, music, or other) connects tothe tip of J

2.

With no peripheral attached, the neg-ative side of the battery floats, with no re-turn to ground. Therefore, the transceiv-er receives no power. The negative side ofthe battery connects to the rings of alljacks you want to use for power-on/offcontrol. Inserting a telegraph key, digital-modulation device, or microphone into J

1

via a monaural plug connects the negativeside of the battery to ground via the ring-to-sleeve short circuit, and the transceiv-er turns on. Plugging an earphone orspeaker into J

2via a monaural plug com-

pletes an alternate, or redundant, groundreturn for the battery. Thus, inserting aplug into either jack completes the pow-er path to all the transceiver circuits.

In another example, you can se-lectively isolate and enable circuits usingstereo jacks to maximize power conser-vation. When you plug a peripheral intoJ

1, the circuit in Figure 2 enables only the

transmitter circuit. When you plug a pe-ripheral into J

2, the circuit enables only

the receiver and audio-amplifier circuits.The return paths of the individual circuitfunctions float and connect to the ring ofone or more stereo jacks associated witha peripheral that requires those circuitfunctions to operate. The battery per-manently connects to the same groundreference as the sleeve of all jacks. Youneed both the receiver and audio ampli-fier to operate during the receive func-tion; they share a common return pathwith the ring of J

2. You enable these cir-

cuits by inserting an appropriate periph-eral (speaker or headphone) into J

2via a

monaural plug.In the final example, you can further

conserve power in specialized cases fea-turing remote on/off control, such as fortransmitter on/off keying (Figure 2).Youuse insert a stereo plug into J

1to remote-

ly locate the ring/sleeve connection. Thering/sleeve path to the negative side of the

battery is incomplete until a peripheralswitch or a key closes. You can define aring/sleeve, tip/sleeve, or ring/tip/sleeveshort circuit and use it to complete thedesired electrical connections. In this ex-ample, the circuit consumes power only

when you enable the transmitter; thus,you have maximum control of battery re-sources. (DI #2355).


ideasdesign

Inserting any monaural plug completes the battery’s ground-return path, thus enabling all circuitsin the transceiver.

The absence of a peripheral plug breaks the ground return for either the transmitter or the receiv-er/audio-amplifier portion of the transceiver.

TRANSMITTER RECEIVERAUDIO

AMPLIFIER

BATTERY SUPPLY AUDIO

OUTPUT

RING

TRANSMITTERKEY TIP

SLEEVE

V1

1+ V1+ V1 +V

J2J1

V+

ANTENNA

TRANSMITTER RECEIVERAUDIO

AMPLIFIER

BATTERY SUPPLY

AUDIOOUTPUT

RING

TRANSMITTERKEY TIP

SLEEVE

V1

1+ V1+ V1 +V

J2J1

V+

ANTENNA

F igure 2

F igure 1



ideasdesign

C onventional sample-and-hold(S/H) circuits use one hold capaci-tor that charges during the track

phase and disconnects during the holdphase. The voltage that the capacitorholds usually drives an A/D converterthat operates synchronously with the S/Hcontrol signal. This approach can some-times place excessive demands on the S/Hcircuit’s bandwidth and settling capabil-ities. You can improve perfor-mance by using two hold capacitors to imple-ment continuoussampling (Figure 1). One ca-pacitor or the other is alwayssampling the input signal, andthe output is always the heldvalue. A phase-reversal switch(IC

1) interconnects the input,

output, and hold capacitors.When the control signal

(Clock) is low, the input con-nects to the C

2hold capacitor

via R2. C

2and the on-resis-

tance of the switch form a160-nsec time constant, pro-viding ample time to chargethe capacitor. When Clockgoes high, C

2connects to the

output via the lower switch,

and C1

connects to the input. Many fac-tors affect the performance of this circuit.Droop rate on the hold voltage, for ex-ample, is a strong function of the output-load impedance. If the A/D-converterload is excessive, you should add a bufferamplifier at the output of the S/H circuit.The hold capacitors should be low-di-electric-absorption types, and the phase-reversal switch should specify low charge

injection and make-before-break timing.Figure 2 (input and output at 100k sam-ples/sec) and Figure 3 (detail at 400ksamples/sec) show good performancewith the values shown. The high-speedtransitions exhibit little overshoot orringing. (DI #2354).

S/H circuit minimizes apertureJohn Guy, Maxim Integrated Products, Sunnyvale, CA

A simple phase-reversal switch uses two hold capacitors to implement a continuous-sampling sample/hold circuit.

At a 100k-sample/sec sampling rate, the circuit in Figure 1 provides excel-lent hold accuracy.

The S/H circuit in Figure 1 exhibits low ringing and overshoot characteris-tics when sampling at 400k samples/sec.

51

51

5V

MAX45281INPUT

OUTPUT2

3

4

V+

V1

8

7

6

5

10 nF

10 nF

1 nF

1 nF

R1

IC1

R2

C3

C2

C1

C4

0

CLOCK

5V

GND

F igure 1

F igure 2 F igure 3


A simple, low cost, and precisionfrequency meter uses onlytwo pins of a pc parallel port

(Figure 1). The TTL-level period-ic input signal with frequency f

INcon-

nects to the ACK pin of LPT1. This in-put produces an IRQ7 hardware in-terrupt on every rising edge (Figure 2).The software counts the number of IRQ7interrupts in the time unit of timebase T.If this timebase is 1 sec, the frequency ofthe input signal equals the number ofIRQ7 interrupts in 1 sec.

You can use many ways to preciselygenerate the timebase, T, such as usingthe delay() or sleep() functions in C. Youcan also use software calibration loops.Unfortunately, these techniquesare unreliable because they arebased on polling. The best choice is to usea second interrupt, such as IRQ0 (soft-ware 0x1C). This interrupt is related tothe internal PC timer and occurs 18.2times/sec. For precise measurements, youcan use proportional constants. For ex-ample, if your timebase equals the 18IRQ0, you must correct the result by afactor of 18.2/18.

The software in Listing 1 is simple and

interrupt-based, which allows for resi-dent operation in an MS-DOS environ-ment and for multitasking mode underWindows. For a timebase of 1 sec and us-ing a 100-MHz Pentium PC, the fre-quency meter gives good results in therange of 10 Hz to 10 kHz with errors less

than 0.26% for DOS and 0.94% for Win-dows (Figure 3). This design uses a Tek-tronix (www.tek.com) CFG280 functiongenerator for reference. A faster PCshould produce even better results.

Listing 1 is written in Borland C++compiler, and you can use the same pro-

ideasdesign


Make a simple PC-based frequency meterRadovan Stojanovic, University of Patras, Patras, Greece

Make a simple PC-based frequency meter ................................................................89

Simple circuit safely deep-discharges NiCd battery ....................................................92

Algorithm extracts roots of decimal numbers ..........................................................94

Reset circuit provides snappy action ........96

Diodes improve inverter efficiency ............96

fIN

ACK

GND

10

25

LPT1

DB25

F igure 1

IRQ7 ACK

IRQ0

VIN (fIN)1

1 18

2 i n11 n

i

T~1 SEC

F igure 2

A simple, easy-to-make PC-based frequency meter uses just two parallel-port pins.

Input fIN, which connects to the ACK pin of LPT1, produces an IRQ7 hardware interrupt on everyrising edge. The software counts the number of rising edges that occur during the timebase, T,which IRQ0 helps to generate.

www.ednmag.com April 29, 1999 | edn 89


ideasdesign

gram for DOS-based C compilers, suchas Turbo C. Also, you can use the secondparallel port LPT2, with interruptIRQ5, to perform this same fre-quency-meter function. If you add onevoltage-to-frequency, current-to-fre-quency, or temperature-to-frequencyconverter, the frequency meter can alsoperform simple, low-cost, and high-res-olution measurements of analog values.(DI #2342)

WINDOWS 95

MS-DOS

100

10 2000 4000 6000 8000 10,000 12,000

80

60

40

20

0

ERROR (Df)

FREQUENCY (Hz)

F igure 3

For a timebase of 1 sec and using a 100-MHz Pentium PC, the frequency meter gives good results thatrange from 10 Hz to 10 kHz with errors less than 0.26% for DOS and 0.94% for Windows.

LISTING 1—C++ FREQUENCY-METER PROGRAM


N ickel-cadmium (NiCd) batteriescan possess an undesirablememory effect due to par-

tial discharges. The remedy is a completedischarge before charging again. Figure1a shows a simple circuit that performsthis feat.

Although relatively straightforward inconcept, the circuit has three redeemingfeatures: It receives its power from thebattery undergoing the discharge; afterthe battery is fully discharged, the currentdrain is only approximately 4 mA, whichis usually well below the self-dischargelevel of a battery alone; and an LED flash-es at end-of-charge.

Ignoring LED current, RD

determinesthe rate at which the circuit dischargesthe battery, as follows:

A NiCd or nickel-metal-hydride(NiMH) battery has a nominal cell volt-age of approximately 1.2V at midchargeand approximately 1V at end of charge.Do not discharge past the end-of-chargevoltage, because you may damage thebattery. The values in Figure 1a are for afour-cell battery. R

1and R

2determine the

end-of-voltage limit referenced to thebuilt-in 1.182V bandgap reference.When battery voltage is high, compara-tor IC

1turns on Q

1, a power n-channel

MOSFET, which discharges the batterythrough R

D.

When the battery reaches the end-of-charge voltage, the circuit’s behavior getsinteresting. R

3and C

1provide positive ac

feedback to ensure that the comparatorfully switches and prevents the circuitfrom becoming a linear regulator. How-ever, the intrinsic internal resistance ofthe battery also causes negative dc feed-back. As the MOSFET turns off the bat-tery terminal voltage, the comparatorturns the MOSFET back on. The positiveac feedback overwhelms the negativefeedback, thus ensuring switching, butonly for a short time, and the circuit os-cillates. The frequency is roughly

Oscillation eventually stops when thebattery voltage stays below the hysteresisthreshold, which the intrinsic resistanceof the battery determines. The higher theresistance, the longer the LED will flash.The circuit takes advantage of the factthat this resistance is greatest at the end

of charge. When the discharge cyclestops, the LED stays off, and the only cur-rent drain is from IC

1and the R

1/R

2di-

vider. Both of these values are smallenough to leave the battery connected in-definitely. (DI #2348)


ideasdesign

Simple circuit safely deep-discharges NiCd batteryJim Hagerman, Science & Technology International, Honolulu, HI

When the battery reaches the end of charge, this deep-discharge circuit (a) oscillates until the bat-tery voltage stays below the hysteresis threshold (b).

PATTY 09d2348a

_

+OUT 8

+

2 1

V1 GND

6

5

4

3

REF

HYST

IC1MAX921

IN1

IN+

3.3M

R3 C110 nF

7V+

Q1

RD

510

LED

6V

R13.3M

R21M

F igure 1

GND

(a)

(b)


D

BATTERYDISCHARGE

R

VI =

.C)RRR(2

1f

1213 •+•p•=

Algorithm extracts cube root”(EDN, Jan 15, 1998, pg 100) cov-ers only the one-third power (cube

root). In contrast, the C routine in List-ing 1 calculates the Kth root (X1/K) ofpositive decimal numbers X. Both K andX can vary widely. You type in X, K, andan estimate of the root; the routine thencalls the calcRoot function in the soft-ware program. Upon calculating theroot, the routine prints on screen thenumber of iterations performed and theroot result X1/K. The routine raises this re-sult to the Kth power and displays the re-sult so you can make a comparison withthe original X. The algorithm applies aNewton-Raphson approach to the equa-tion Y=X1/K. If you differentiate the equa-tion and express it in recursive form, youobtain

This recursion monotonically con-verges toward the Kth root of the num-


ideasdesign

Algorithm extracts roots of decimal numbersFrank Vitaljic, Bellingham, WA

TABLE 1—CUBE-ROOT MAXIMUM ERRORSX % Error0.001 0.0010.01 0.00050.1 0.000210 0.00005100 0.000021000 0.00001

TABLE 2—CUBE-ROOT ITERATIONSNumber Number

of iterations thisX 1998 Design Idea Design Idea0.001 10 100.01 12 Eight0.1 14 Six10 19 Seven100 23 111000 22 14

LISTING 1—KTH-ROOT EXTRACTION FOR DECIMAL NUMBERS

5 4, 3, 2,K

AND3 2, 1, ,0nFOR

,)n(KY

)n(YX)n(Y)1n(YERROR

1K

K

K

K

=

=

=+=1

11


ideasdesign

The circuit in Figure 1 provides a 1-sec reset, using multiple AND gatesfor increased fanout. Intended for

breadboarding or prototyping,the circuit generates a “snappy”master reset that remains active longenough to eliminate questionable start-ups.When you apply power to the circuit,the timing capacitor begins chargingthrough the 1-MV resistor, turning onthe npn transistor. The AND-gate inputsgo low, generating the reset signal andturning on the reset LED. When the tim-ing capacitor brings the transistor’s basenearer to ground, the transistor turns off,and the 2.2-kV resistor pulls the ANDgates’ inputs high. The transistor isolatesthe capacitor from the AND gates’ inter-nal pull-up resistors and provides asmooth transition through the logicthreshold. Upon removal of power, the1N4001 diode discharges the timing ca-pacitor. (DI #2351).

Reset circuit provides snappy actionSteve Kelley, Protobyte Inc, Liberty, MO

Eschew marginal, wimpy reset signals by using this high-fanout, snappy-reset circuit.

1k

POWER ON

2.2k+

4.7 mF

1M1N4001

220kMPS2222A

5V DCVCC

RESET-ON

1

2

3

4

1k

7408/5408

R

R

R

F igure 1

In “Switched-capacitor regulatorprovides gain” (EDN, March 13,1998, pg 80) a switched-capacitor

voltage inverter wired as a supply split-ter steps a positive voltage down to an

output voltage equal to half the supplyvoltage. The input current to such a cir-cuit is one-half the output current; thus,you obtain higher efficiency and lowerpower loss than you would from a linear

regulator performing the same function.You can obtain the same benefits whileinverting the input voltage. Figure 1shows the principles of operation. Typi-cal switched-capacitor inverters contain

Diodes improve inverter efficiencyJeff Witt, Linear Technology Corp, Milpitas, CA

ber. The routine terminates the iterationwhen

The error in the calculation is

Table 1 shows cube-root errors for

numbers 0.001 to 1000. The number ofiterations varies from six to 14. Table 2compares the number of iterations in-herent in the algorithm with the numberof iterations of the earlier Design Idea.For increased accuracy, you can set themaximum ERROR define to 1.0e214 atthe expense of increasing the number ofiterations. You can download the C list-

ing from EDN’s Web site, www.ednmag.com. Click on “Search Databas-es/Links Page” and then enter the Soft-ware Center to download the file for De-sign Idea #2339. (DI #2339).



.10ERROR)n(Y)1n(Y 611 =£+

.)ACTUAL(Y

100ERRORERROR%

·£


ideasdesign

Adding a few diodes to a switched-capacitor inverter doubles the current from input to output.

four internal switches. Two switchescharge a flying capacitor from the inputvoltage to ground; the other two switch-es discharge the capacitor, pulling thepositive side to ground and gen-erating a negative output voltage.

By adding three diodes to steer the cur-rent, you can use the switches to chargetwo capacitors in series and then dis-charge them in parallel to an output ca-pacitor. Figure 1 shows the current paths.The absolute value of the output voltageequals half the input voltage minus someloss from the switches and diodes. Figure2 shows a practical circuit, which con-verts 12V to 24V at 100 mA. IC

1modu-

lates the voltage drop across Switch 1 toregulate the output, maintaining 24Vfrom an input of 11 to 15V. Many nega-tive supplies power loads that can pull theoutput above ground (op-amp circuits inparticular). Q

1prevents such a load from

pulling IC1’s output pin above the voltage

on the op amp’s ground pin. Becausemost of IC

1’s operating current flows

from its ground pin, the input current tothis circuit is slightly more than half theoutput current. When the circuit delivers100-mA load current, measurements

show that the 12V input delivers 64 mA.The circuit dissipates only 350 mW, so anall-surface-mount configuration runscool. (DI #2352).

VOUT

VREF

C3

VIN

33 mF

C4

D1D2

D3

IC1

6.8 mF

C133 mF

C233 mF

86.6k

100k

20k

14V100 mA

(11 TO 15V)

GND

FB

V+

CAP+

CAP1

LT1054

+

NOTES:C1, C2, C3=TAJB336M010R.C4=TAJB685M025R.D1, D2, D3=MOTOROLA MBR0520LT1.Q1=IR IRLML2402.IC1=LT1054CS8.

Q1

VIN

VOUT

COUT

4

2

3

VIN

VOUT

COUT

4

2

3

(a) (b)

PHASE 1

1

PHASE 2

1

F igure 2

F igure 1


This 12V to 24V converter delivers 100-mA output current with 63-mA input current.

April 29, 1999 | edn 101www.ednmag.com

ideasdesign




Name

Title

Phone

E-mail Fax

Company

Address

Country ZIP

Design Idea Title





Signed

Date




May 13, 1999 | edn 99www.ednmag.com

The circuit in Figure 1 shows an ex-ample of how you can use an inte-grated switching regulator (ISR) to

efficiently vary the speed of a per-manent-magnet dc motor. In thisapplication, the rotating head of a robotsenses the presence of an oncoming ob-ject (perhaps a human). If the robot sens-es an object, it slows the rotation of itshead to closely survey the surroundings.If an object is indeed present and comeswithin a certain distance of the robot, therobot’s head stops rotating and “looks” inthe direction of the object. The robot usesa typical proximity-detection device thatsenses reflected light (Figure 2). It’s nosecontains a photodetection device thatsenses the light that reflects from an on-coming object. The primary source of thelight is the robot’s eyes, which containtwo lamps. The photodetector in the noseresides in a black tube to reduce the ef-fects of ambient light.

The sensed light causes a photodetec-tion current to flow through the pho-todetector and R

4, developing a voltage

across R4(Figure 1). The LM324 op amp,

which you configure as a noninvertingamplifier with an adjustable gain of

Switching regulator drives robot motorDonald Comiskey, Power Trends Inc, Warrenville, IL

This robotic circuit uses an integrated switching regulator as a power op amp to control the rota-tion of an object-seeking robot’s head.

R2D2 has lamps in his eyes to provide a light source and a photodetector in his nose to detect lightreflected from an oncoming object.

6V-DC MOTOR

5 TO 8

GND

INTEGRATEDSWITCHINGREGULATOR

VOUT

C1100 mF

9 TO 11

2 TO 4

VOUT

VIN ADJUST

INHIBIT

1

LM324

R1150k

12

1

PT6101

+

1

12V

4

11

R2100k

R31k

R4100k

3

2

VC

PHOTODETECTOR

LAMP LAMP

1

C20.1 mF

12V-DC INPUT +

+ 1

LAMPS

MOTOR

PHOTODETECTOR

OBJECT

F igure 1

ideasdesign


Switching regulator drives robot motor . . . . . . . . . . . . . . . . . . . . . . . .99

Simple fix adds door-chime repeater . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Clock multiplier circumvents PLL . . . . . . .102

Synthesize optimal digital-frequency dividers . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Voltage regulator controls scanner-lamp brightness . . . . . . . . . . . . . . . . . . . .108

Simple changes improve Schmitttrigger . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

F igure 2

100 edn | May 13, 1999 www.ednmag.com

ideasdesign

Simple fix adds door-chime repeaterDennis Eichenberg, Parma Heights, OH

E lectromechanical door chimescan enhance your home, but theyare vulnerable to costly repair prob-

lems. A defective pushbutton switch or acareless visitor can maintain the chime inan energized state for a prolonged peri-od, thereby damaging the chime. The cir-cuit in Figure 1 prevents damage to thechime and improves the chime’s effec-tiveness by repeating the chime strike foras long as the pushbutton remains de-pressed. The circuit controls both frontand rear chimes. The heart of the circuitis timer IC

2, which you configure as an

astable multivibrator. The timing com-ponents, R

1, R

2, R

3, and C

3, provide the re-

quired pulse widths.The maximum duty cycle of a typical

chime is 25%. The energized time is0.76(R

3+R

4)C

3, which you can adjust

from 7.6 msec to 0.4 sec. The de-ener-gized time is 0.693(R

1+R

2)C

3, which you

can adjust from 0.3 to 1 sec. IC2drives the

12V relay, K1, via resistor R

5and transis-

tor Q1. D

5is a flyback diode that protects

K1. You must select K

1to fit the specific

chime. The coil current can be as high as200 mA. The circuit normally uses closed

contacts so that illuminated pushbuttonswitches operate properly. The 16V-acdoor-chime power energizes the circuitvia bridge BR

1. IC

1provides voltage reg-

ulation, and C1

and C2

provide filtering.Diodes D

1and D

2provide power from

the rear-door pushbutton. D3isolates the

filtered timer power from the relay. (DI#2349).

RESET VCC

TRIGGER

OUTPUTTHRESHOLD

DISCHARGE

CONTROLVOLTAGE

GND

7

5

6

C40.1 mF

C20.1 mF

C10.1 mF

D31N4001

D21N4001

D11N4001

D51N4001

C30.1 mF

R3500

R21M

R51k

IC2

IC1

R1470k

R410k

D4

1

1N4148

POT

84

2

3

LM7812CIN OUT

GND

2

3

4 BR14-1N4001

3

Q1

REARCHIME

A

B

2N2222A

12V

RELAY_DPDT_b

K1

NC1

COM1

COM2

NO1

NO2

NC2

21

16VAC

REAR

FRONT

FRONTCHIME

LM555

F igure 1

You can both protect your door chime and obtain pleasing chime repetition with this circuit.



1+R2/R

3, amplifies this voltage. The am-

plified voltage is a control voltage, VC,

which routes to the ISR’s Adjust pin viaR

1. A decrease in V

C, relating to a decrease

in light level, causes the ISR’s output volt-age and the corresponding speed of thedc motor to increase. An increase in V

C,

relating to an increase in light level, caus-es V

OUTand the corresponding motor

speed to decrease. A further increase inlight level causes V

Cto increase to a point

at which VOUT

becomes low enough tostop the rotation of the motor. A linearrelationship exists between V

Cand V

OUT:

VOUT

=2VC+6.25V.

In the absence of light, the output volt-age of the op amp saturates near 0V. Theequation shows that a control voltage of0V produces an ISR output voltage of6.25V, causing the motor to rotate at itsmaximum speed. A light level that pro-duces a 6.25V control voltage results in

an ISR output voltage of 0V, causing themotor to stop rotating. Intermediate mo-tor speeds result from control voltagesbetween the extremes of 0 and 6.25V.Youcan adjust feedback resistor R

2, which sets

the op-amp gain, to obtain any desiredsensitivity. The PT6101 ISR in Figure 1 is85 to 90% efficient and supplies motorcurrents as high as 1A. (DI #2353).


U sing a standard PLL circuit,such as the CMOS 4046B withsome passive components, is a well-

known way to design a clock multiplier.Unfortunately, using a PLL in a digitalcircuit has two disadvantages: It takes along time for the circuit to reach a stableoutput frequency, and the frequency-drift compensation has a complex design.

An alternative clock-multiplier ap-

proach uses simple combinatorial logicand a delay line (Figure 1). By taking intoaccount the propagation delays in com-binatorial logic and the fact that mostlogic designs are edge-triggered, the cir-cuit can multiply by 2, 3, 4, and poten-tially beyond. You can use this techniqueto increase the system clock speed andmaintain a low-frequency clock for therest of the circuit, thereby helping to re-

duce EMI and cost in high-speed logicdesigns. Also, the circuit exhibits a veryfast start-up. This approach is commonin modern mP architectures that useclock-doubling techniques to achievebetter performance at low costs.

In place of the silicon delay line, youcould use standard CMOS logic. Howev-er, the differing propagation delays forhigh-to-low and low-to-high transitions

Clock multiplier circumvents PLLJose Carlos Cossio, Santander, Spain

Using a delay line and a phase-comparison scheme with XOR gates (a), this circuit multiplies the input clock by 2, 3, and 4 without a PLL (b).

ideasdesign

F igure 1

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

CLK=1.0416 MHz

1

4

5

6

7

9

12

14VCC

TAP1

TAP2

TAP3

TAP5

TAP4

TAP6

TAP8

TAP7

TAP9

TAP10

GND

IN15VDS1010-400

CLK22

CLK23

CLK24

(a)

(b)


ideasdesign

Internally delayed clock signals produce the desired clock-multiplication factors of 233 (a), 333 (b), and 433 (c).

F igure 2

(tpdHL

ÞtpdLH

) presents a problem. A stan-dard delay line with fixed and known de-lay taps is preferable.

The circuit in Figure 1a uses a DallasSemiconductor (www.dalsemi.com) DS-1010-400 delay line, which has 10 built-in fixed delays of 40 nsec, to implementa 23, 33, and 43 clock multiplier thatoperates from an external 1.0416-MHzclock. This design requires XOR gateswith short propagation delays, such asadvanced-bipolar or fast CMOS gateswith propagation delays of less than 10

nsec, so that the XOR-gate delays are neg-ligible.

The circuit works by using the XORgates to perform a phase comparison.These gates monitor the difference be-tween the incoming clock signal and thedelayed clock signals. First, the circuitshifts right, or delays, the signal to bemultiplied: once for 23, twice for 33,three times for 43, and so on. Then, be-cause an XOR gate sits between thesource and the delayed signals, the resultof the XOR operation is the signal mul-

tiplied by 2, 3, and 4. The resultant clocksignals have the same duty cycle as the in-coming signal (Figure 1b). Figure 2shows the internally delayed clock signalsthat are necessary to produce the 23, 33,and 43 clocks.(DI #2344).

For many applications, you need todivide a reference clock into one ormore subclocks to use in different

parts of the system. Sometimes, this di-vider circuit is simple. For example, a cir-cuit that divides by an integer number iseasy to construct using a few flip-flopsand assorted logic gates. However, oftenyou must build a noninteger divider, forexample, a divide by 7/8 or 512/1025. Inthese cases, you could use a divider anda PLL to divide the input reference by the

denominator and then multiply the re-sult by the numerator, but the circuitwould become relatively complex and re-quire analog components.

However, if your application can tolerate some clock jitter, there is anoth-er answer: the binary-rate-multiplier(BRM) circuit. This well-known circuitworks by multiplexing two dividers intoand out of the divide path. Unfortunate-ly, it is sometimes difficult to find the setof design parameters that gives the least

amount of jitter and the desired dividerratio. Using the following method andcircuit you can easily generate optimumBRMs.

The average frequency, fOUT

, of theBRM output is:

where fIN

is the frequency of the input ref-

Synthesize optimal digital-frequency dividersLindo St Angel, PrairieComm Inc, Arlington Heights, IL

(a)

(b)

(c)


,)DIVREP()DIVREP(

)REPREP(

ff

2211

21

INOUT

·+·

+

·=

(1)


ideasdesign

erence clock, DIV1is the number of times

the first divider divides the input clock,DIV

2is the number of times the second

divider divides the input clock, REP1

isthe number of input clock cycles forwhich the first divider is active, and REP

2

is the number of input clock cycles forwhich the second divider is active.

Instantaneous frequency of the BRMoutput equals the frequency of the inputclock divided by the the active divider.The BRM output jitters between thesetwo frequencies. However, you can min-imize this jitter by choosing the parame-ters DIV

1and DIV

2according to

and

You then need to choose values for theparameters REP

1and REP

2. One way to

choose these values is to transform Equa-tion 1 into an optimization problem andfinding the values of REP

1and REP

2that

minimize the transformed equation, giv-en your chosen values for DIV

1and DIV

2:

The constraints on this equation arethat Z is greater than or equal to zero andthat REP

1and REP

2are integers that are

greater than or equal to unity.You can solve Equation 4 using integer

nonlinear optimization techniques.Many commercial software packages, in-cluding Microsoft Excel, solve these class-es of problems. Enter Equation 4 into Ex-cel and use the solver from the toolsmenu to operate on the equation, usingthe above constraints.

To get Z to exactly equal zero, it is im-portant to increase the solver’s precisionand tolerance settings to about 10 timestheir default values. Also, make sure thatyou check your results by plugging in allvalues and checking that Z exactly equalszero. If it doesn’t, you have to increase thesolver’s precision and tolerance settings.

Once you have obtained values for allthe parameters, you can use them in theVerilog model to get a circuit from a log-ic-synthesis tool (Listing 1). If you don’thave access to logic synthesis, the Verilogmodel can give you some idea of how tomanually build up the circuit from gates.You can download Listing 1 from EDN’sWeb site, www.ednmag.com. Click on“Search Databases/Links Page,” and thenenter the Software Center to downloadthe file for Design Idea #2358. (DI#2358).


.1DIVDIV 12 +=

,f

fINTDIV

OUT

IN1 = (2)

(3)

.1)DIVREP()DIVREP(

)REPREP(

f

fZ min

2211

21

OUT

IN

1·+·

+

·=

(4)

LISTING 1—BINARY-RATE-MULTIPLIER VERILOG


ideasdesign

An image-scanning device per-forms best when the scanner IC con-trols the brightness of the image re-

flected into the light sensors. The bestway to control brightness is by adjustingthe intensity, or light output, of the fluo-rescent lamp that shines light onto thescanned item. Traditionally, adjustable

brightness has been economically unfea-sible in most scanners because it is cost-ly to implement a high-current voltagesource that is also software-programma-ble. However, you can use a simple, low-cost circuit to implement full-rangelamp-brightness control (Figure 1).

The fluorescent lamps in most low-

cost scanners operate from a fixed 12Vsource, which operates the lamp at max-imum brightness. If you reduce thesource to a lower voltage, you can adjustthe brightness of the lamp to virtually anylevel. You can accomplish the voltagechange using a circuit that takes in 12Vand produces a regulated dc output volt-

Voltage regulator controls scanner-lamp brightnessChester Simpson, National Semiconductor, Santa Clara, CA

A lamp-brightness control regulator provides full-range brightness control depending on the duty cycle of the control signal from IC1.

PC

PCPARALLEL

PORTIC1

LM9830

A

A

B

B

128K228SRAM

LIGHTSENSOR

LAMPASSEMBLY

SCANNING-BAR ASSEMBLY

LAMP-BRIGHTNESS

CONTROLREGULATOR

OBJECT TOBE SCANNED

LAMP-BRIGHTNESSCONTROL SIGNAL

12V IN 0 TO 12V OUT

STEPPERMOTOR

12V

SENSEA

SENSEB

SENSOR OUTPUTS

SENSOR CONTROL SIGNALS

F igure 1

This control regulator averages the control signal to provide an adjustable reference input to IC1B that ultimately determines the level of VOUT.

+

+

1

+

IC1ALM358

1

+

IC1B

R651k

R4100k

R2

C40.1C3

0.1

R1

R551k

5.1k

10kQ1

NDP6020P

C122 mF/25V

C547 mF/16V

VOUT0 TO 12V AT 0.5A

VOUT=122(DUTY CYCLE)

C20.01

R3100k

8

7

4

5

6

SG

D

2.8k1%

1/4W

2k1%

1/4W

GNDGND

12V IN

CONTROLSIGNAL

5V

0F=10 TO 50 kHz

1

2

3

NOTES:ALL RESISTORS ARE 5% TOLERANCE, 1/8W, UNLESS OTHERWISE INDICATED.C1 AND C5 ARE SOLID TANTALUM. ALL OTHER CAPACITORS ARE CERAMIC.SOLDER Q1 TO PC BOARD WITH COPPER AREA Ä1 IN.2 FOR HEAT SINKING.

F igure 2


ideasdesign

age that varies from 0 to 12V, dependingon the lamp-brightness control signalcoming from IC

1’s scanner IC. IC

1sets the

duty cycle of the control signal, which isa 5V pulse train.

The lamp-brightness control regulatortakes in 12V and regulates this input toany voltage from 0 to 12V (Figure 2). Be-cause the on-resistance of the NDP6020PFET is only approximately 50 mV, themaximum regulated output voltage thecircuit provides is within approximately25 mV of the input voltage at the typicallamp current of 0.5A.

The circuit generates a regulated out-put using error-amplifier IC

1B, the R

1/R

2

resistive divider, and an adjustable refer-ence voltage at Pin 6 of IC

1B. The circuit

produces this reference voltage by aver-aging the input control signal’s square-wave pulse train. R

3, C

3, R

4, and C

4filter

the square waves into a dc voltage. Thevoltage across C

4is the average value of

the pulse train, which is directly propor-tional to the duty cycle:

By adjusting the duty cycle of the 5Vpulse train, you can linearly vary the ref-erence voltage at Pin 6 of IC

1Bfrom 0 to

5V.You can program a maximum of 4095duty-cycle values for the LM9830 scan-ner IC, which yields 4095 brightness lev-els.

IC1B

compares the voltage across C4

with the voltage at the center of R1

andR

2, which the circuit derives from V

OUT.

The regulating action of IC1B

constantlyadjusts the gate-drive voltage to Q

1, forc-

ing VOUT

to a value that keeps equal thevoltages at the inputs of IC

1B. In this way,

the voltage at C4, which is proportional to

the duty cycle of the pulse train, controlsthe regulated voltage, V

OUT. You can cal-

culate VOUT

using the following equation:

where VPK

is the peak amplitude of thepulse train (5V in this application) andduty cycle is the pulse on-time divided bythe total period.

R5, R

6, C

1, C

2, and C

5are necessary for

compensation and stability. For the com-ponent values in the ffiigguurree, the best per-formance occurs when the frequency ofthe pulse train is 10 to 50 kHz. (DI#2356).

The classical Schmitt trigger cir-cuit that you’ll find in text-books provides some noise

immunity, such as for the front end ofmagnetic pickup in position-sensor cir-cuits (Figure 1a). You adjust the twothreshold levels using R

1and R

2or R

2and

R3. The circuit works acceptably but has

two problems. First, each resistor affectsboth levels, making the circuit adjust-ment an iterative process. Second, the opamp’s current-sinking ability limits yourchoices for R

3and, hence, your ability to

adjust the circuit. The improved triggercircuit in Figure 1b has independentlyadjustable levels; you first adjust R

1and

then R2. The circuit also eliminates the

sensitivity to the op amp’s current-sink-ing capability. (DI #2361).

Simple changes improve Schmitt triggerRon Patrick, ECM, Los Altos, CA

The classical Schmitt-trigger circuit (a) requires an iterative adjustment and the op amp’s sink cur-rent affects the ability to adjust the circuit. The adjustable levels of an improved circuit (b) are com-pletely independent.

VCC

R1

R2

R3

LM393+

1

VCC

R110k

R210k

LM393+

1

(a)

(b)

ZVN3306

1k

F igure 1



CYCLE.DUTY V5V 4C ·=

,R

RRCYCLEDUTY

VR

RRVV

2

21

PK2

214COUT

+·

·=+

·=


ideasdesign



Name

Title

Phone

E-mail Fax

Company

Address

Country ZIP

Design Idea Title



Exclusive publishing rights remain with CahnersPublishing Co unless entry is returned to author, or editorgives written permission for publication elsewhere.In submitting my entry, I agree to abide by the rules of the


Signed

Date


Design Idea Entry BlankEntry blank must accompany all entries. $100 Cash Award for all published Design Ideas. An additional $100 Cash Award forthe winning design of each issue, determined by vote of readers. Additional $1500 Cash Award for annual Grand Prize Design,selected among biweekly winners by vote of editors.


Access odd memory locations without hardwareSorin Zarnescu, NEC Electronics, Santa Clara, CA

Some risc controllers, like theNEC V850 family, use an in-ternal 32-bit architecture

with an external 16-bit bus. The archi-tecture also allows interfaces with 8-bitmemories. However, with 8-bit memo-ries, accesses to and from odd locationsautomatically access the higher-orderbyte. Thus, you would need externaltransceivers to access both even and oddlocations. However, you can “trick” theprocessor and thereby save the space andcost associated with the external trans-ceivers. Like everything else in life, themethod doesn’t come free—the price youpay is execution time.

The idea (Figure 1) is fairly simple:Connect the memory data bus to theleast-significant bit (D0 to D7) of the mC.Then, connect the memory-address busto the mC without using A0, so that thememory never sees an odd address. Thus,addressing the memory generates onlyeven addresses. At first glance, themethod might seem wasteful, becausethe memory occupies twice the space itneeds, but with large memory spacesavailable (the V850 family can address asmuch as 16 Mbytes), the wastage shouldnot present a problem. As an example,

suppose register r2 contains the follow-ing data that you should store in a 1k38memory, starting at address 0x100:

Most Leastsignificant significantbyte byte30 20 10 00

After storing is complete, the memoryresembles the following:

Address Data::0x100 00

0x101 100x102 200x103 30::Assuming (r1)=0x100, the sample

program in Listing 1 arranges the stor-age operation. The tradeoff between ex-tra hardware and longer execution timedepends on the application’s require-ments. (DI #2366)

A simple technique allows you to access odd memory locations without the need for externaltransceivers.

mC MEMORY

D0 TO D7

A4 TO A10 A3 TO A9

D0 TO D7

A1

A2

A3

A0

A1

A2

LISTING 1—SAMPLE PROGRAM TO ARRANGE STORAGE OPERATION

ideasdesign


Access odd memory locations without hardware . . . . . . . . . . . . . . . . . . .101

Charge indicator gauges lead-acid batteries . . . . . . . . . . . . . . . . . .102

Use derivatives to catch RF calibration errors . . . . . . . . . . . . . . . . . . .104

mC-based circuit performs frequency multiplication . . . . . . . . . . . . . . . . . . . . . .108

Kick start a crystal oscillator in Spice . . .110

F igure 1


www.ednmag.com May 27, 1999 | edn 101

Although rechargeable,sealed lead-acid cells areuncommon in portable

applications, they are a good choicefor standby applications, such asemergency lighting and burglaralarms. A key advantage to usingthese batteries is that you can deter-mine the amount of remainingcharge by measuring the open-circuitvoltage. This technique is invalid forNiCd or NiMH cells. Figure 1 showsthe relationship between the amountof remaining charge versus the open-circuit battery voltage. This curve isaccurate to approximately 10%, pro-vided that you have not charged ordischarged the battery for at least 24hours. A simple circuit measures theopen-circuit voltage, such as the ex-

panded-scale voltmeter circuit inFigure 2, which follows the curve inFigure 1.

Sealed lead-acid batteries are avail-able in several sizes, from a single Dsize (2.5 Ahr) to multicell rectangu-lar battery packs. These cells can pro-vide high output currents and yearsof reliable backup power. Other de-sirable features include relativelysimple charge requirements and lowself-discharge. The low self-dischargeand ease of determining the remain-ing charge make sealed lead-acid bat-teries an ideal choice for flashlightsand portable lighting. The low self-discharge, which is approximately5% per month at 25°C, means that arechargeable flashlight using sealedlead-acid cells will still have usable

ideasdesign

Charge indicator gauges lead-acid batteriesFran Hoffart, Linear Technology Corp, Milpitas, CA

The curve of remaining charge versus open-circuit bat-tery voltage for a sealed lead-acid battery is accurate toapproximately 10%, if you haven’t charged or dis-charged the battery for at least 24 hours.

2.16

2.12

2.08

2.04

2.00

1.96

1.92 100 80 60 40 20 0

REMAINING CHARGE (%)

CELL

VOL

TAGE

(V)

VCC

VREF CS/SD

CLK

DOUT

GND

4

8-BIT SERIAL ADC

TOmP

8

TO BATTERY

OPTIONAL ADC OUTPUT CIRCUITANALOG METER OUTPUT

IC2LTC1096

+IN

1IN

5 1

2 7

3 6

TO PIN 6

TO PIN 1

METER FACE0 TO 100%

50-mAPANELMETER

(~60 mV)~

R62k

R516.9k

IC1LT1541

+

1

2 8

1.2V

R4499k

3

6

NOTES: USE 1% RESISTORS FOR STABILITY. FOR R1, SELECT A 16.2-kV RESISTOR THAT MEASURES HIGH.

THE VALUE OF R5 VARIES WITH DIFFERENT METER MOVEMENTS. WHEN USING THE OPTIONAL ADC OUTPUT CIRCUIT, CHANGE R4 TO 600 kV.

R35k

R260.9k

R116.3k

100k

28.0k

14.0k

28.0k

SIX CELLS 12V

FOUR CELLS 8V

ONE CELL 2V

THREE CELLS 6V

RANGE SWITCH

A

1

+

4.5VTHREE

AA CELLS

1 mF

BATTERY

+

F igure 1

To measure a sealed lead-acid battery’s open-circuit voltage, an expanded-scale voltmeter circuit uses an op amp and reference to provide the neces-sary gain and offset to drive an analog or digital-panel meter, or optionally an ADC.

F igure 2


ideasdesign

capacity of approximately 30% after oneyear of inactivity. NiCd and NiMH cellslose approximately 30% of their chargeper month. A flashlight using NiCd cellsrequires a trickle charge when not in useto ensure reliable power when necessary.Without trickle charging, NiCd cells willcompletely discharge after three to fourmonths of inactivity.

With the range switch in Figure 1 inthe one-cell position, the panel meterdoesn’t move until the input voltage ex-ceeds 1.930V. Full scale corresponds to aninput voltage of 2.130V. The op amp andreference provide the gain and offset fordriving a digital panel meter, an ADC, oran analog meter with the meter scale cal-ibrated from 0 to 100% of remainingcharge. A rotary switch allows you to usethe meter circuit with multicell batterypacks containing one to six cells.You canmeasure other cell quantities by selectingthe appropriate resistor divider values.

The circuit configures the op-amp sec-tion of IC

1, which also includes an un-

used comparator, as an inverting gain-of-five amplifier. This configuration pro-duces a 1.000V change at the output fora 200-mV change at the input. The neg-ative terminal of the battery connects tothe op amp’s inverting input resistor. Toaccomplish the 1.930V offset, IC

1’s inter-

nal 1.200V reference, R2, and R

3gener-

ate a current that flows into the op amp’ssumming node (Pin 2). The op-amp out-

put drives a standard 50-mA analog pan-el meter with a scale from 0 to 100%.Youcan also use a 1V full-scale digital panelmeter or an ADC (Figure 2). The 8-bitADC, IC

2, uses the 1.2V reference voltage

of IC1

for the ADC reference, giving afull-scale output (8 bits) for a 1.2V input.If you use the ADC, the op amp’s gainmust increase from 5 to 6 to provide anoutput of 1.2V from the op amp for a200-mV change at the input. To makethis change, you simply increase the val-ue of R

4to 600 kV. You can also use ana-

log meters ranging from 100 mA to 1 mA,if you reduce the values of R

5and R

6.

Calibrating the circuit requires an ad-justable voltage source, preferably withcoarse and fine voltage adjustment anda digital voltmeter. With three AA cellsfor power and the range switch in theone-cell position, apply a precise12.130V to the input at point A. Con-nect a DVM to the op amp output (Pin1) and adjust R

3for a 1.000V reading on

the DVM. Next, adjust R6

for a full-scalereading, 100%, on the analog meter. De-creasing the voltage source by 100 mV to12.030V should drop the DVM reading

to 500 mV and drop the analog meter tomidscale, or 50%. Dropping the voltagesource an additional 100 mV to11.930V results in a DVM reading near0V and a corresponding meter indicationof 0%. Because of minor resistor and off-set-voltage errors, the output may not ex-actly equal 0V, but may be a few mV pos-itive. For this application, this value ismore than adequate. Resistor values of1% provide the best accuracy and stabil-ity, but you can use a standard 16.2-kV10% resistor that measures approxi-mately 100V high for R

1. You can use

Table 1 to verify other ranges.The circuit does not require a power

switch because the op-amp section of thecircuit draws extremely low quiescentcurrent (12 mA). Battery life should equalthe shelf life of the battery, which is sev-eral years. The op amp’s input also in-cludes overvoltage and reverse-voltageprotection. (DI #2359)

TABLE 1—BATTERY VOLTAGE VERSUS METER READINGNumber of cells Nominal voltage (V)% 0% 50% 100%

1 2 1.93 2.03 2.133 6 5.79 6.09 6.394 8 7.72 8.12 8.526 12 11.58 12.18 12.78

Many RF-system calibrations in-volve checking for minimum pow-er available or removing system

offsets. One example is the checking of anRF source’s output power. The systemspecifications may call for a minimumsource power minus any cabling powerloss, but a typical source may be able toprovide more power than the manufac-turer specifies as the minimum. To min-

imize the system cost, it is best to set thetest-line limit to the minimum powerplus a suitable instrumentation uncer-tainty (Reference 1).

This simplistic test may not catch all ofthe possible system problems. Loose RFconnections or bad cables may result inpower holes. Although these power holesmay not always be deep enough to dropthe power below the specified minimum

test limit, no one wants to ship a systemwith a loose RF connection, or worse.Trained personnel may catch such aproblem if they view it graphically, butthis sort of test is very hard to quantify.

A better way to detect problems is todifferentiate the data and place limits onthe data’s rate of change. This method isa surefire way to test for system problemsthat don’t show up in the minimum-

Use derivatives to catch RF calibration errorsSteven C Hageman, Hewlett-Packard Co, Santa Rosa, CA



ideasdesign

power test. You can apply this techniqueto a large class of RF test and calibrationissues, primarily the removal ofsystem offsets during calibration.Many systems function properly withlarge offsets because calibration removesthese offsets. However, the data usuallyhas typical mismatch ripple effects overfrequency, which cause the offset value tochange as the frequency changes. If theoffset ripple is too great or changes withfrequency at a large rate, the stability ofthe calibration may be in jeopardy; asmall change in the location of the ripplefrequency may cause a large change incalibration offset data. By looking at thederivative data of the calibration, you canview the rate of change of the offset.When the rate of change reaches a certainlevel, the test alerts you, thereby the testis less subjective.

Assuming that your test is computer-controlled, you should be able to easilyaccess the test data.You can apply the for-ward difference equation to the test datato find the first derivative on a point-by-point basis:

Figure 1a shows the results of a suc-cessful minimum-power test. The pow-er is well above the 12-dBm limit andis well-behaved. The derivative data isalso small. Figure 1b shows the same sys-tem when a connector is loose. In thiscase, the minimum power data is abovethe specification but is not well-behaved;in fact, a power hole appears. The powerhole does not cause a failure in the min-imum specified power, but remains acause for concern for three reasons:

● a power hole results when a systemproblem in unstable with time, tem-perature, or shipping;

● as the loose connection moves, thenull frequency may move in fre-quency, rendering subsequent cali-brations useless;

● only a trained eye can determinefrom the plot that there is a failure.

You cannot determine the failure bysimply looking at a pass/fail result. How-ever, the derivative data from the powerhole can generate a hard-fail indication.

The derivative of the data in Figure 1b is10 times the derivative data in Figure 1a.If you set the pass/fail criteria for the de-rivative data at 5 dB/Dx, the data fromFigure 1a easily passes, and the data fromFigure 1b fails.

You can use a small statistical base ofmeasurements on different systems to seta qualified, statistical three-sigma limiton the derivative data. This limit will beinsensitive to offset magnitude but willshow point-to-point rate of change. Us-ing the derivative data limits and theminimum power limits together will

eliminate any chance of shipping an im-properly functioning system to a cus-tomer. (DI #2360)

Reference1. Application Note AN64-1, “Funda-

mentals of RF and Microwave PowerMeasurements,” Hewlett-Packard Co,Palo Alto, CA.

5

4

3

2

1

0

21

22

23

24

25

40

30

20

10

0

210

220

230

240

1.11 1.23 1.34 1.45 1.57 1.68 1.8 1.91 2.02 2.14 2.251

1.11 1.23 1.34 1.45 1.57 1.68 1.8 1.91 2.02 2.14 2.251

DERIVATIVE

DERIVATIVE

POWER

POWER (dBm)

FREQUENCY (GHz)(a)

5

4

3

2

1

0

21

22

23

24

25

40

30

20

10

0

210

220

230

240

DERIVATIVE

DERIVATIVE

POWER

POWER (dBm)

FREQUENCY (GHz)(b)

F igure 1

In a well-behaved system (a), both the power data and its derivative are above the 12-dBm level.Tests of the same system with a loose connector (b) show that the power curve still doesn’t dipbelow 12 dBm, but the derivative data indicates the existence of a power hole.



x

)x(F)xx(F)x(F

D

D+=¢

1

ideasdesign

The traditional frequency multi-plier requires many elements: a phasecomparator to detect the phase error

between the input and the output signals,a lowpass filter to convert the phase error

to a dc control signal, a VCO to generatethe output, and a divider to set up themultiple ratio. The circuit in Figure 1uses a different approach to multiply fre-quency with a programmable multiple

ratio from 1 to 7 (Table 1). Because thecircuit is edge-triggered, the 50% outputduty cycle is independent of the duty cy-cle of the input waveform. Test resultsshow that the output frequency-range is

mmC-based circuit performs frequency multiplicationYongping Xia, Teldata Inc, Los Angeles, CA


LISTING 1—FREQUENCY-MULTIPLIER CODE

Starting up oscillator circuitsand getting them to maintain oscil-lation in a Spice simulation is diffi-

cult. Some high-frequency crystal cir-cuits require days for the oscillation toreach steady state. Thus, most designersseparate the crystal’s circuit simulationfrom the rest of the system design. How-

Kick start a crystal oscillator in SpiceAdam Chen, Cypress Semiconductor, Woodinville, WA

ideasdesign

from 31 Hz to greater than 30 kHz.The AT90S1200 is a low-cost,

high-speed mC, and most instruc-tions need only one clock cycle. With a12-MHz clock, these instructions take83.3 nsec. This number places the highlimit on the input frequency becausesoftware performs all functions. The pro-gram in Listing 1 includes an endlessloop to generate a square-wave output.The frequency of the output depends onthe value of a 16-bit delay register thatcomprises two 8-bit registers: dly_1 anddly_2. The delay function is a countdownloop until it reaches zero. The larger thenumber in the delay register, the longerthe delay time. The functions of the end-less loop and the delay register are anal-ogous to a VCO.

The AT90S1200 has an 8-bit counterwhose input is the output signal. Becausethis counter is an up counter, the pro-grammable multiple ratio loads into thecounter in the 2’s complement format.For instance, if the multiply ratio is four,the software loads that counter with 0xfc.Because the initial value of the counter

is 0xfc, four output pulses cause thecounter to overflow, which generates aninterrupt. The function of this counteris analogous to the divider in a traditionalfrequency multiplier.

Every rising edge ofthe input signal alsogenerates an interrupt.Thus, the interruptsubroutine must iden-tify the events that trig-ger the interrupts. Ifthe input causes the in-terrupt, the frequencyof the output is toolow. If the counter trig-

gers the interrupt, the output frequencyis too high. In both situations, the soft-ware must adjust the value of the delayregister accordingly. The interruptionsubroutine is analogous to a phase com-parator.

Listing 1 is available for downloadingfrom EDN’s Web site, www.ednmag.com.Click on “Search Databases”and then en-ter the Software Center to download thefile DI #2362.

A simple mmC-based circuit can multiply frequency by 1 to 7.

RESET VCC

PD0

PD1

XTAL2

XTAL1

PD2

PD3

PD4

PD5

GND

PB7

PB6

PB5

PB4

PB3

PB2

PB1

D2

D1

D0PB0

PD6

IC1

AT90S1200-12

19

18

17

16

15

14

13

12

11

20

5V

0.1 mF

OUTPUT

1

2

3

4

5

6

7

8

9

10

12 MHz

INPUT

22 pF 22 pF

F igure 1

TABLE 1—FREQUENCY-MULTIPLIER SETTINGSD2 D1 D0 Output frequency0 0 0 —0 0 1 x10 1 0 x20 1 1 x31 0 0 x41 0 1 x51 1 0 x61 1 1 x7



LISTING 1—SPICE NETLIST

ever, a technique that gives a“kick” to an RLC equiva-lent circuit solves thisproblem. This method makessure the simulation starts fast andquickly reaches the steady state.

Figure 1a shows the equivalentRLC circuit of a quartz crystal.Most clock chips, such as CypressSemiconductor’s (www.cypress.com) CY227x and CY228x fami-lies, have a crystal circuit similarto Figure 1b. The circuit com-prises the crystal, an inverter/gainblock, and a feedback network.

Conventionally, Spice uses aninitial condition for the RLC res-onator, such as setting the induc-tor initial current to a certain val-ue, to start the simulation. Thereference frequency of the most commonclock chips is 14.1318 MHz. Thesimulation takes a least a day toreach constant oscillation amplitude be-cause high-Q resonators require long pe-riods of time to reach a certain energylevel.

The key to quickly starting this type ofoscillator is giving a kick to the RLCequivalent circuit in the form of a high-voltage damped sinusoid that ultimatelyfades away. The frequency of this excita-tion is the expected frequency of the res-onator. The source looks like a short cir-cuit in the RLC circuit and does not alterany of the circuit’s dc- bias conditions.Figure 2 shows the simulation input/out-put waveforms, and Figure 3 shows theexcited sinusoidal voltage. The excitedvoltage is in the kV range becausethe voltages across L1 and C1 arein kV range when the LC tank is oscillat-ing.

For a 14.318-MHz crystal, the equiva-lent circuit has Co=4 pF, C1=13.613 pF,L1=9.076 mH, and R1=25V. The excitedvoltage source is a simple Spice sinu-soidal voltage source, Vsin in Listing 1.The Vsin statement includes the damp-ing factor. (DI#2357)

The equivalent circuit of a quartz crystal (a) includes equivalent resistance, R1; inductance, L1; capacitance,C1; and inner electrode capacitance, Co. In addition to the crystal, clock chips include an inverter/gain blockand a feedback network (b).

Co

L1 R1

Rf

ViC1

QUARTZ CRYSTAL QUARTZ CRYSTAL

xtalin xtaloutA1 A2

Ca Cb

OUT

(a)

NOTES:R1=EQUIVALENT RESISTANCE.L1=EQUIVALENT INDUCTANCE.C1=EQUIVALENT CAPACITANCE.Co=INNER ELECTRODE CAPACITANCE.Vi=EXCITED SINUSOIDAL VOLTAGE SOURCE.

(b)

NOTES:Ca=Cb=34 pF, Rf=1MV.QUARTZ CRYSTAL=14.318 MHz.A1, A2 CMOS INVERTER.

F igure 1

F igure 3

F igure 2

An excited voltage source in the RLC circuit ensures oscillation startup and then quickly fadesaway.

The crystal circuit’s simulation waveforms reach steady state in approximately 0.5 mmsec.

ideasdesign

VOLTS

XTALIN

XTALOUT

VOLTS

TIME (SEC)

TIME (SEC)



A s the resolution of ADCs in-creases from 12 to 16 bits and high-er, the difficulty in testing the “no-

missing-codes” specification grows pro-portionately. To fully guarantee no miss-ing codes for a 16-bit ADC requires test-ing all 21621 possible output codes.Undertaking such a production testcould add much extra cost to the ADCwithout a quick method for testing allcodes. Fortunately, a simple approach cantest the no-missing-codes specificationfor a 16-bit ADC—in this case, a 10-msecADS7805, in typically less than 7 sec (Fig-ure 1).

This missing-codes tester comprises ananalog ADC servo loop that you can alsouse to measure the integral nonlinearityand differential nonlinearity of 16-bitADCs (Reference 1). The servo loopworks by finding the ADC’s input voltagethat corresponds to the Code

i-to-Code

i+1

output transition. The circuit uses an 18-bit DAC729, IC

1, as a pedestal DAC to

quickly set the input voltage to the ADC

under test to approximately the level cor-responding to the programmed inputcode. The output transfer function of thepedestal DAC matches the transfer func-tion of the ADC under test—in this case,±10V for the ADS7805. The DAC729MSB bit-adjustment pins, pins 36 to 40,are open because the unadjustedDAC729’s linearity is sufficient for per-forming only the ADC missing codes test.

The procedure successively tests eachpossible output code of the ADC undertest by programming a PC with the de-sired 16-bit code, Code

i. Applying a 100-

kHz clock to pin 24 of the ADC providesfor continuous operation of the ADS-7805. When the ADC completes a con-version, two 8-bit 74HC682 magnitudecomparators, IC

2and IC

3, and accompa-

nying interface logic, IC4

and IC5, com-

pare the ADC’s output code to the pro-grammed data-bus code. The signaloutput from IC

4Asignifies whether the

input voltage to the ADC needs to in-crease or decrease to achieve an ADC out-put equal to the programmed Code

i. The

signal from IC4B

indicates whether theoutput code from the ADC matchesCode

i; a logic-low level indicates that the

code was found.Because both the P>Q

16and P=Q

16sig-

nals from IC4A

and IC4B

, respectively, canbe momentarily indeterminate duringthe ADC conversion, the circuit latchesthese signals into flip-flops IC

6and IC

7

when the conversion is complete. Theclock signal for these latches is a delayedversion—approximately 200 nsec—ofthe rising edge of the ADS7805 end-of-conversion signal, BUSY. The circuit usesthe P>Q

16signal clocked into IC

6to con-

trol the ramp direction of integrator opamp IC

8. The 0 to 5V output of HC-type

flip-flop IC6directly drives the integrator

input of IC8. R

1, R

2, and the 215V pow-

er supply shift the 0 to 5V output level toapproximately 22 to +2V. C

1filters any

high-speed transients that arise from theswitching action of IC

6’s output.

Op amp IC9attenuates the integrator’s

output by 100 and sums the result withthe output of the pedestal DAC. For thecomponent values of IC

8’s integrator

stage, the maximum ramp rate at the in-put of the ADC is approximately 2mV/msec, which is equivalent to 0.067LSB per conversion. Feedback of the ser-vo-loop circuit maintains the dc level ofthe integrator’s output by continuouslyadjusting the input voltage of theADS7805 to the level required for theCode

i-to-Code

i+1output transition.

Thus, the servo-loop circuit locks in theinput voltage to the ADC to maintain theCode

i-to-Code

i+1output transition.

The P=Q16

signal that the circuit clocksinto flip-flop IC

7indicates whether the

programmed Codei

exists for the ADCunder test. The output of IC

7connects to

an input control line, CNTL6, on the con-

trolling PC’s I/O card. After the controlprogram sends each new Code

ito the

tester, the PC reads the state of CNTL6.

A high level on CNTL6

indicates thatCode

iexists and is not missing.

ALIGN PEDESTAL DAC WITH ADC UNDER TEST

Before starting the missing-codes test,the procedure requires alignment of thepedestal DAC’s endpoints with those ofthe ADC under test. This alignment en-sures that the pedestal DAC’s outputclosely matches the corresponding ADCinput voltage for all codes programmedto the tester. Under this condition, thevoltage needed to sum with the pedestalDAC output should be only a few LSBs(referred to the ADC input), thus keepingthe dc output level of the integrating op

ideasdesign


Missing-codes tester checks 16-bit ADC in 7 sec . . . . . . . . . . . . . . . . . . . . . . . . . . .113

Switch-mode supply draws 43-mW standby power . . . . . . . . . . . . . . .116

Circuit rejects ambient light . . . . . . . . . . .118

V/I converter accommodates grounded load . . . . . . . . . . . . . . . . . . . . .120

Digitally controlled potentiometer sets cutoff frequency . . . . . . . . . . . . . . . . . . . .122

Precision reference bans precision resistors . . . . . . . . . . . . . . . . . . .124

Easy method calculates comparator trip points . . . . . . . . . . . . . . . . . . . . . . . . .124

EDN selects 1998 Design Ideasgrand-prize winners . . . . . . . . . . . . . . . . .128

Missing-codes tester checks 16-bit ADC in 7 secMark A Shill, Burr-Brown Corp, Tucson, AZ

www.ednmag.com June 10, 1999 | edn 113

114 edn | June 10, 1999 www.ednmag.com

ideasdesign

An analog servo loop tests for no missing codes by finding the ADC’s input voltage that corresponds to the Codei-to-Codei+1 output transition.

RESET

V REFOUT

V REFIN

1

V REFIN

2

BPO1

+VCC

2V CC

BPO2

DCOM

ACOM

WR EN1

EN2

LDAC

DAC2813

74HC139

8255 PORT C

8255 PORT B 8255 PORT A

DB 11MSB

DB 10

DB 9

D11

Y0 Y1 Y2

CNTL2

PC2

D15 D14 D13 D12 D11 D10 D9 D8

D15 D14 D13 D12 D11 D10 D9 D8

PB7 PB5 PB4 PB3 PB2 PB1 PB0

D7 D6 D5 D4 D3 D2 D1 D0

PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

PC1 PC0

CNTL1 CNTL0

Y3

D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

B1M

SB

B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 VDD

VOUT

B18 LSB

IC1

IC11

IC12

DB 8DB 7

DB 6DB 5

DB 4DB 3

DB 1DB 2

VOUT1

VOUT2

DB 0LS

B

14

13 21 26 25 24 23 18 22 1920

16 15 17 1 2 3 4 5 6 7 8 9 10 11 12

28

1M

27

G A B

GAIN A

DJ

REF G

ND

REF O

UT

REF IN

DAC729

DGND

IC13

74HC573

AGND

I OUT V CC

2V CC

10KFB

10KFB

SJ

1 2 3 4 5 6 7 8 9

1 2 3 4 5 6 7 8 9

10 11 12 13 14 15 16 17 18 19 20

11 19 18 17 16 15 14 13 12

1Q 2Q 3Q 4Q 5Q 6Q 7Q 8QC

1D 2D 3D 4D 5D 6D 7D 8DOE

PB6

Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8

Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8

D7 D6 D5 D4 D3 D2 D1 D0

Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0

IC14

74HC573

1 2 3 4 5 6 7 8 9

11 19 18 17 16 15 14 13 12

1Q 2Q 3Q 4Q 5Q 6Q 7Q 8QC

1D 2D 3D 4D 5D 6D 7D 8DOE

34 33 32 31 30 29 26 25 24 22 21

23

5V

100k

0.0022 mF

15V 215V

15V

5V

215V

CB

PEDESTAL DAC OUT

F igure 1

amp, IC8, close to 0V. Thus, for each Code

i

setting, the integrator output never needsto slew very far from the dc level of 0V.

Comparators IC10A

and IC10B

form awindow comparator for the output ofIC

8. The window voltage is equal to 100

mV, which corresponds to approximate-ly 3.3 LSBs, referred to the ADS7805 in-put. I/O control lines CNTL

4and CNTL

5

read the outputs of IC10A

and IC10B

, re-spectively to determine the level of theintegrator’s output voltage. If CNTL

4is

high, the integrator output is more than100 mV. If CNTL

5is high, the integrator

is less than 2100 mV. If both CNTL4

andCNTL

5are low, the integrator output is

within the 100-mV window.A dual, 12-bit latched DAC, IC

11, ad-

justs the pedestal DAC’s endpoints.VOUT1

and VOUT2

adjust the pedestal DAC’s off-set and gain, respectively, to the endpointsof the ADC under test. First, the controlprogram adjusts the DAC729’s offset byprogramming and latching Code

ito FFFE

(hex) and then counting up or down ac-cordingly so that V

OUT1brings the inte-

grator voltage within the 100-mV settingof the window comparator. Next, the pro-gram sets IC

1’s gain by programming and

latching Codeito 0000 and again count-

ing up or down so that VOUT2

brings theintegrator output to a null.

The same I/O data bus programs boththe DAC2813 and the 74HC682 digitalcomparators. The 74HC139 decoder,IC

12, selects either the input Code

ilatch-

es, IC13

and IC14

, or the internal latches ofthe DAC2813. IC

11has two input-latch-

enable pins, one for each of its outputDACs. Input LDAC loads the DAC’s in-put latch data into the internal latches,thus simultaneously programming bothV

OUT1and V

OUT2. I/O control lines CNTL

0

and CNTL1

select the desired latch, andCNTL

2strobes in the data from the bus.

The listing of the Pascal program forcontrolling the missing-codes tester isavailable for downloading from EDN’s


D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

P7 P6 P5 P4 P3 P2 P1 P0

Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0

Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8

D14D15

AGND1 BUSY DGND VANA VDIG

IC5CIC5B

IC5A74HC04

IC4A

VREF

VIN

CAP AGND2 BYTE CS R/C2

+ IC9

15V

2

3

7

4

6

OPA627

2

+

2

+

IC10A

IC8 C1 R2

15V

15V

15V

215V

215V

215V

2

2

3

34

1

2

+

IC10B

215V

5

6

6

7

7

330 pF

10k

1M

14.9k

14.9k

100

100

200

ADS7805DUT

17 15 13 11 8 6 4 2

18 16 14 12 9 7 5 3

IC274HC682

P>Q P>QH

P=QHP=Q

1

19

P7 P6 P5 P4 P3 P2 P1 P0

IC4DIC4C IC4B

IC5D

CNTL6

IC5EQ7 Q6 Q5 Q4 Q3 Q2 Q1 Q0

Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0

17 15 13 11 8 6 4 2

18 16 14 12 9 7 5 3

IC374HC682

P>QP>QL

P>Q16

P=Q16

P=QLP=Q

1

19

+ +

+

CNTL4

CNTL5

ADC CLOCK 100 kHz

222.2 mF

74HC74D

PR

CLCLK

Q

Q

IC7

74HC74D

PR

CLCLK

IC6

DUT POWER

1k

270 pF

10 pF

10 mF

74HCOO

5V

OPA602

100k

30k

R15k

215V

5V

2

1

3 4 5 23 25 24 26 14 27 28

33.2k

6 7 8 9 10 11 12 13 15 16 17 18 19 20 21 22

10k

LM293

10k

10k

5V

0.1 mF

8255 PORT C

CNTL6

PC6 PC5 PC4

CNTL5 CNTL4

web site, www.ednmag.com. Click on“Search Databases/Links Page” and thenenter the Software Center to downloadthe file for Design Idea #2334. The sec-tion of the program that outputs codesto the data bus and reads the state of theCNTL

6line is based on a custom I/O card

built with an Intel 8255A programmableperipheral interface. The I/O routines arefor reference only, and you should mod-ify them according to the protocol usedby the user’s specific I/O card.

The EndPoints procedure in the listingaligns the offset and gain of the pedestalDAC to that of the ADC under test. Itprograms IC

11as necessary to null the in-

tegrator output for both offset and gain.The Detect procedure programs eachCode

i, from 0 to 65534, to the missing-

codes test board. After programmingeach new code, the program reads thestate of the CNTL

6line. If CNTL

6is a log-

ic high, indicating the programmed codeexists, the Count variable is increment-ed. The Detect procedure loops for thegiven code until a minimum number ofoccurrences are detected, set by the vari-able MinCount. The variable MaxTry setsthe maximum number of times that theprogram trys to find Code

i. The program

loops for an appropriate delay time to en-sure that measurements of the state of

the line occur only once per analog-to-digital conversion or, in the case of theADS7805, approximately every 10 msec.For the variable MinCount set to 3 andMaxTry set to 30, the missing-codestester can test the 10-msec ADS7805 forall 21621 codes in less than 7 sec. (DI#2334)

Reference1. Shill, Mark A, “Servo loop speeds

tests of 16-bit ADCs,” Electronic Design,Feb 6, 1995, pg 93.



ideasdesign

Switch-mode offline supplies of-fer better efficiency than linear sup-plies. However, the efficiency of a

switchmode power supply (SMPS) seri-ously degrades with light loads, and com-mutation losses provoke power dissipa-tion well above 1W even with no load. Agood way to build a low-standby-currentSMPS is to use a hysteretic architecture,which delivers high-frequency pulses un-til the output passes a threshold and thenno pulses until the output again dropsbelow the threshold. The SMPS con-sumes little energy delivering the re-freshment pulses. Figure 1 shows a cir-cuit that uses an MC34063 controller ICand an insulated-gate bipolar-transistor(IGBT) output device.

The MC34063 operates in current

mode. Q3

trips the IC when the voltageon sense resistor R

16drops to approxi-

mately 550 mV. (IPEAK

=160 mA in this ex-ample.) You can adjust the peak currentto compensate for the transformer’smagnetorestrictive effects. Any trans-former you use in an SMPS produces au-dible noise at a low frequency.You can ei-ther buy an expensive transformer whoseconstruction ensures low audible noiseor keep peak current low, as in Figure 1’scircuit. When reducing the peak current,you need to increase either the primaryinductance or the switching frequency(by varying C

8) to keep the output pow-

er constant.The MMG05N60D IGBT has low par-

asitic capacitance that degrades efficien-cy at low peak currents. When you open

the high-voltage switch in a MOSFET-based flyback converter, the peak currentdoes not immediately drop to zero. De-pending on the amount of parasitic ca-pacitance, the current keeps circulatingwhile the drain voltage rises, and effi-ciency suffers. Figure 2a illustrates thiswasteful behavior in a high-voltage,MOSFET-based switcher. The MMG-05N60D IGBT has low parasitic capaci-tance; its total gate charge at V

GS=10V is

only 4 nC. Figure 2b shows the currentin Figure 1’s circuit with zero outputpower.

The start-up circuit for the MC34063uses Q

4and Q

2. When you apply the

power main, the voltage on C14

starts torise. The ratio of R

20and R

22 causes Q

4

and Q2

to remain open. The IC receives

Switch-mode supply draws 43-mW standby powerChristophe Basso and François Lhermite, Motorola SPS, Toulouse, France

A hysteretic architecture in an offline switch-mode power supply makes it possible to achieve less-than-100-mW standby power.

R182.5M

R192.5M

R211M

R1100k

R4560

R1410k

R151k

R8560

R163.3

D66.8V

IC2MOC8103

Q1MMG05N60D

T1G6518-00* D5

1N5819L210 mH

R17270

C12100 mF

C11470 mF

R2233k

R201M

C1447 mF C10

10 mFC8470 pF C9

470 pF

IC1MC34063 Q3

MMBT2222

Q2MGSF1P02

D41N4148

Q4BC559C

4.7 mF/350VC13

421N4007

85 TO 260V AC1

2

3

45

6

7

8

+

+

+7.4V2.3W

*AVAILABLE FROM THOMSON OREGA.

F igure 1


ideasdesign

no power, and the current that flows infrom C

14is small. When the voltage

reaches a threshold, Q4

starts to conductand pulls Q

2’s gate toward ground. Q

2’s

drain voltage rises and strengthens the

conduction in Q4. C

14rapidly discharges

into C10

, and the MC34063 oscillates. Thecircuit offers efficiency ranging from 59.4to 73%. It dissipates no-load power lev-els of 42.5, 65, and 82.8 mW at dc input

voltages of 120, 325, and 360V, respec-tively.(DI #2363).

In some applications, you need todetect light signals in the presence ofbackground light whose in-

tensity can change by orders ofmagnitude. The circuit in Figure 1 usesan integrated photodiode/amplifier(OPT201) in conjunction with an inte-grator that drives two linear optocou-plers (TIL300). The optocouplers sub-tract the background-light-generatedcurrent from the current the optical sen-sor produces. C

2integrates any dc signal

present at the output of IC1. The output

of IC2

drives two optocouplers, IC3

andIC

4. The four photodiodes in both

TIL300s connect in parallel with thediode in the OPT201 to subtract the dccomponent from the signal path. IC

3

and IC4

need 60-mA drive to produce re-jection current as high as 1.5 mA. Thisdesign uses the optocoupler configura-

Circuit rejects ambient lightMassimo Gottardi, IRST, Trento, Italy

The two optocouplers use input-series, output-parallel connections to halve the driving current anddouble the output rejection current.

IC2

1

1

+

+

75

1M

IC14000 pF

4

5

OPT201

40 pF

R2 1M

R1 1M

C10.1 mF

C20.1 mF

2

8

15V

Q12N2222

R3 1001/2W

IC4 TIL300

IC3 TIL300

The turn-off characteristic of a lateral MOSFET (a) results in significant wasted power in a no-load condition; lower parasitic capacitance in an IGBTleads to lower dissipation during the turn-off period.

F igure 2


(a) (b)

F igure 1

ideasdesign

The voltage-to-current (V/I) converter inFigure 1 uses three common op amps,two medium-power transistors, and onlya few passive components. The first opamp (IC

1) inverts the sum of voltages V

IN

and VOUT

to V1=-(V

IN+V

OUT). The second

op amp (IC2) and transistors Q

1and Q

2

invert this voltage to produce VIN

+VOUT

.The formula for calculating the outputcurrent is thus:

The formula shows that the value ofI

OUTdepends only on V

INand R

6. Voltage

follower IC3

reduces to a negligible levelthe current from the circuit output toIC

1. The advantages of the circuit are:

● load-grounding possibility;● simple control of I

OUT/V

INratio;

● high precision, linearity, stability,and bandwidth;

● wide IOUT

range, approximately 1mA to I

C(max) of Q

1and Q

2; and

● high output resistance of approxi-mately 50 MV. (DI #2365).

V/I converter accommodates grounded loadMichele Frantisek, Brno, Czech Republic

A versatile voltage-to-current converter provides a handy current source in many analog applications.

1

+1

+

R733k

VIN R4

100k 1%IC1OP-77

115V

100k 1%

R1

15V

R3

V1

R2

100k 1%

100k 1%

1

+

15V

115V

IC3OP-77

115V

15V

15V

R847k

IC2OP-77

2N4033

115V

R5

V2

R6

1k 0.1%

100k 1%

2N3019

Q2

Q1

IOUT

VOUT

F igure 1

tion instead of a simple resistor, becausethe optocouplers’ nonlinear characteris-tic allows a higher current range withoutsubstantially affecting the noise gain of

the transimpedance amplifier. The totaloutput noise in the circuit is 80 mV rms.A 6.8-kV resistor can reject the same1.5-mA dc current, but it produces 200-

mV output noise. (DI #2364).




.R

V=

R

VV+V

=R

VV=I

6

IN

6

OUTOUTIN

6

OUT2OUT

1

1


ideasdesign

The traditional method ofcontrolling the upper cutofffrequency in the basic inverting-am-

plifier circuit of Figure 1 is to add capac-itor C in parallel with R

2. The value of C

controls the cutoff frequency. R1

and R2

independently establish the magnitude ofthe circuit gain, which equals R

2/R

1. If

you need a variable cutoff frequency, youuse a variable capacitor. However, this ap-proach has two major problems: The cir-cuit does not lend itself to computer con-trol, and few variable capacitors areavailable with values in the nanofarad re-gion.

The circuit in Figure 2a is an invert-ing amplifier that uses a digitally con-trolled potentiometer and a fixed capac-itor as an input Tee network. The mag-nitude of the gain for this inverting cir-cuit is also R

2/R

1. However, in this case,

R1, C, and the location of the wiper along

the resistor array of the potentiometer es-tablish the cutoff frequency. The uppercutoff frequency is programmable be-cause the wiper of the potentiometer isunder digital or computer control.

Several analysis approaches help de-termine the circuit gain as a function offrequency. One approach is to use y, oradmittance, parameters. If you treat net-works A and B as two ports (Figure 2b),the ratio of the short-circuit admittancecoefficient for the input port, y

21 A, to y

12B

for the feedback port produces the fol-lowing gain expression:

In this equation, k is a number thatvaries from 0 to 1 and reflects the pro-portionate position of the wiper fromone end of the potentiometer (0) to theother end (1).

The circuit’s gain expression is

This equation has the same form as anequation for an amplifier or lowpass fil-ter with a gain of 2R

2/R

1and a cutoff fre-

quency of

As you program the wiper from oneend of the potentiometer to the other, kvaries from 0 to midscale (1/2) to 1, andthe cutoff frequency varies from infinitehertz to a minimum frequency and backto infinite hertz. The minimum frequen-cy is

For the XDCP family of digitally con-trolled potentiometers (Xicor Inc, www.xicor.com), k can vary from 0 to 1. Thenumber of taps or programmable wiperpositions determines the resolution. R

1

represents the RTOTAL

of the potentiome-ter. The number of taps varies from 32 to256, and R

TOTALvaries from 1 kV to 1

MV, depending on the potentiometer.The potentiometer can store a wiper orcutoff-frequency setting in nonvolatilememory, which permits the circuit’s cut-off frequency to return to a predeter-mined value on power-up.

For the circuit in Figure 2a, gain is 4.7,and the cutoff frequency varies from 6.4kHz to a theoretically infinite hertz. Thecircuit uses a 10-kV potentiometer, theX9C103, which has 100 taps and a three-wire interface. The circuit is useful foraudio, control, and signal-processing ap-plications. (DI #2367)

+

1

VO

R1VS

C

R2

(a) (b)

VS

VO

1

+

NETWORK B

R2

VO

1

+

R2

C

kR1 (11k)R1

NETWORK A

47k

26

3

3

CONTROL AND

MEMORY

5 4

R1

C0.01 mF

LT1097

15V

4

76

5V

2 1 7 8

5V

VS

CS

INC

UID

X9C103

F igure 1

Digitally controlled potentiometer sets cutoff frequencyChuck Wojslaw, Xicor Inc, Milpitas, CA

Controlling the cutoff frequency using a tradi-tional inverting amplifier circuit has some limi-tations, such as a limited selection of variablecapacitors.

An inverting amplifier that uses a digitally controlled potentiometer and a fixed capacitor provides for a programmable cutoff frequency (a). You cananalyze the circuit as a two-port network (b).


F igure 2

.

)k1(CkR

1j

)k1(CkR

1

R

R

y

y

V

V

1

11

2

B 21

A21

S

O

1

111

+ω

==

.j

A

V

V

C

Co

S

O

ω+ωω

=

.)k1(CkR2

1f

1C 1π

=

.CR2

4f

1)MIN(C π

=


ideasdesign

Combining a switched-capacitorcharge pump with a precision refer-ence yields an inverted reference

from a positive power supply (Figure 1).Unlike the more typical combination ofa positive three-terminal reference and anop-amp inverter, this circuit per-forms accurate inversions withoutthe need for precision resistorsand a negative supply. The com-pact circuit requires only threesurface-mount capacitors,and the ICs occupy tinySOT-23 packages.

The charge-pump inverter, IC2,

delivers 25V by inverting the out-

put of a 5V precision reference, IC1. IC

1

has an input range of 5.2 to 12.5V. Re-placing IC

1with a 2.5V reference that ac-

cepts 2.7 to 12.5V inputs produces a-2.5V output.

Output-voltage accuracy depends

partly on the initial accuracy of IC1,

which in this case is 1%. To determine theoverall accuracy, you must add the errorfrom the dropout voltage, which is lessthan 2 mV for 90 mA of load current(Figure 2a). For a -2.5V output, the cir-

cuit draws quiescent currentthat ranges from 86 mA for a2.7V input to 105 mA for a 12.5Vinput. For 25V outputs, the cir-cuit draws 127 mA for 5.2V in-puts and 140 mA for 12.5V in-puts (Figure 2b). (DI #2368)

GND

IC1MAX6150

(MAX6125)IN OUT

GND

IC2

MAX828IN OUT

VIN5.2 TO 12.5V

(2.7 TO 12.5V)

+3.3 mF

+3.3 mF

VOUT15V

(12.5V)

+

C1 C+

3.3 mF

1 10 100 1000OUTPUT CURRENT (mA)

LOAD CURRENT (mA)

SUPP

LY C

URR

ENT

(mA

)

OUTP

UT

VOLT

AGE

DROP

(m

V)

(a) (b)

0

22

24

26

28

210

212

214

216

VOUT=25V

VOUT=22.5V

NOTES:FOR TRACE A, VIN=12.5V, AND VOUT=25V.FOR TRACE B VIN=5.2V, AND VOUT=25V.FOR TRACE C, VIN=12.5V, AND VOUT=22.5V.FOR TRACE D, VIN=2.7V, AND VOUT=22.5V.

250

200

150

100

50

00 10 20 30 40 50 60 70 80 90 100

A

B

C

D

F igure 1

Precision reference bans precision resistorsBudge Ing, Maxim Integrated Products, Sunnyvale, CA

Combining a voltage reference and a charge-pump inverter formsa precision negative reference.

For a S5V output, the dropout voltage is less than 2 mV at 90 mmA of output current (a). For a 225V output, quiescent current ranges from 127 to 140mmA.


Using Millman’s Theorem to cal-culate the resistor ratio reduces thetime it takes to calculate the trip

points on a comparator with hysteresis.

This method eliminates lengthy compu-tations and substitutions. Using this re-sistor ratio, you select two resistors, as-sign convenient values, and then

calculate the third value.Assume an inverting comparator with

an upper limit of 4V and a lower tripvoltage of 1.333V. The voltage on the in-

Easy method calculates comparator trip pointsVirgil Lawrence, Micro Linear, San Jose, CA

F igure 2


ideasdesign

Circle No 5 or visit www.ednmag.com/InfoAccess

verting input needs to reach 1.333V forthe output to switch to V

CC. Then, for the

output to return to zero, the input volt-age needs to reach 4V.

Millman’s Theorem states that the sumof the products of the voltages times theirrespective conductances divided by thesum of the conductances gives the com-mon junction-point voltage V

X(Figure

1). Or,

where Gt1/R.Using Millman’s Theorem, with

VCC

at the top of R1

and RF

(Fig-ure 2), set up the numerator witha Millman equation. Set up the denomi-nator with another Millman equationwhen the output voltage is zero (with onlyone voltage source in the denominator).Assume that R

Cis llR

Fand therefore neg-

ligible in the calculations. The resultantequation for the voltage ratio is:

This large fraction equals the voltageratio 4/1.333t3. First solve for R

Fin terms

of R1, and select R

1in relation to R

F, such

as R1t1 MV, and R

Ft500 kV. Then solve

for R2. The resistance ratio always equals

the voltage ratio minus one. (DI #2372)

Millman’s theorem states that the sum of theproducts of the voltages times their respectiveconductances divided by the sum of the con-ductances gives the common junction pointvoltage VX.

Using Millman’s theorem, you can calculatethat the voltage ratio of the trip points equals(RF+R1)RF.

VX

RN

VN

R1 R2

F igure 1

RC

VCC12V

R1

R2

VCC

RF

+

F igure 2

,G

GVV

N

NNX ∑

∑=

.RATIO VOLTAGER

RR

R

12R

12

R

12

G

GV

G

GV

V

V

F

1F

1

F1

N

NN

N

NN

)LOW(IN

)HIGH(IN

=+

=

+==

∑∑∑

∑


www.ednmag.com

ideasdesign

EDN is pleased to announce the grand-prize winners for De-sign Ideas published in 1998. Lukasz Sliwczynski and MarcinLipinski of the Institute of Electronics at the University of Min-ing and Metallurgy, Krakow, Poland, specialize in fiber-optictransmission for nontelecommunications applications and oth-er optoelectronic circuits. The pair takes the honors for “Cir-cuit uses simple LED for near-IR light,” EDN, Sept 1, 1998, pg92. The choice was difficult given the high quality of 1998’s De-sign Ideas. EDN chose the winning Design Idea for its simplic-ity, cleverness, and usefulness. The circuit eliminates the needto configure a bulky and expensive mechanical fixture to gen-erate light with precisely controlled power levels. The honorstook the pair by surprise.

“We never suspected that, among so many interesting ideas,ours might be prized as the best one,”says Lipinski. He says thathe and co-designer Sliwczynski thought of the idea after par-ticipating in a project involving some optical reflectometers re-

quiring a precise and stable light source. “We have done lots ofexperiments with semiconductor lasers, but found that they areunsuitable for this purpose,” says Lipinski. After these experi-ments, the pair decided to use the hybrid LED module that thewinning Design Idea describes. The idea has already found usein a real-world application. A pro-ecological installation usesthe reflectometer to measure the fumes from industrial chim-neys. It has been in use for a long time and performs well, ac-cording to Lipinski. This Design Idea was one of six that Sliw-czynski submitted and the only one Lipinski submitted last year.

In his spare time, the 30-year-old Sliwczynski, who is single,plays electric guitar and travels to historical sites. Lipinski, 52,is married with two children and likes classical music, skiingin the wintertime, and camping in the summertime. Each de-signer plans to use his half of the $1500 cash prize for the up-coming summer holidays.

Jan 1, 1998,“Fax saver cuts wear, tear, and power,”Hugh Adams, FortWalton Beach, FL.

Jan 15, 1998,“LED flasher and triac pulser work off ac line,” DennisEichenberg, Parma Heights, OH.

Feb 2, 1998, “Vital-signs monitor consumes less than 50 mA,Leonard Schupak, Discovision Associates, Irvine, CA.

Feb 16, 1998, “Antenna extension provides open-door policy,”Richard Panosh, Vista, Bolingbrook, IL.

March 2, 1998,“Isolated driver forms solid-state circuit breaker,”BobWatson, Corley Manufacturing Co, Chattanooga, TN.

March 13, 1998, “Inexpensive relays form digital potentiometer,”Robert Perrin, Z-World, Davis, CA.

March 26, 1998, “Alternating LED blinker uses four parts,” AndyMeng, Cincinnati, OH.

April 9, 1998, “10-kHz VFC uses charge-pump variation,” StephenWoodward, University of North Carolina, Chapel Hill, NC.

April 23, 1998, “$5 junk-box circuit determines phase sequence,”Hugh Adams, Fort Walton Beach, FL.

May 7, 1998, “MCS-51 endows MicroLan-like protocol to UARTs,”SK Shenoy, NPOL, Kochi, India.

May 21, 1998, “High-frequency AGC has digital control,” RonMancini, Harris Semiconductor, Melbourne, FL.

June 4, 1998,“25-kV generator tests insulation,” Lukasz Sliwczynskiand Przemyslaw Krehlik, University of Mining and Metallurgy, Krakow,Poland.

June 18, 1998,“Use a printer port to record digital waveforms,”DeanShen, Dycam Inc, Chatsworth, CA.

July 2, 1998, “Circuit protects against ac-line disturbances,” BasilioSimoes, ISA, Coimbra, Portugal.

July 16, 1998,“Step-up/step-down converter takes 2 to 16V inputs,”Luciano Bordogna and Luca Vasalli, Maxim Integrated Products, Mi-lan, Italy.

Aug 3, 1998,“Circuit translates TTY current loop to RS-232C,” JerzyChrzaszcz, Warsaw University, Poland.

Aug 17, 1998,“Replace an external gate with a resistor,”Stan D’Souza,Microchip Technology Inc, Chandler, AZ.

Sept 1, 1998,“Circuit uses simple LED for near-IR light,” Lukasz Sli-wczynski, Marcin Lipinski, Institute of Electronics, Krakow, Poland.

Sept 11, 1998,“Add-on modulator has high bandwidth,’’ MJ Salvati,Flushing Communications, Flushing, NY.

Sept 24, 1998,“Bipolars provide stable current source,”Bill Morong,Morong’s Harness, Dover-Foxcroft, ME.

Oct 8, 1998,“Video equalizer sharpens VCR images,” Wayne Sward,Consultant, Bountiful, UT.

Oct 22, 1998, “Photo-flash charger minimizes parts count,” StevenChenetz, Micrel Semiconductor, San Jose, CA.

Nov 5, 1998, “Short-circuit finder uses few parts,” Boris Khaykin,Candid Logic Inc, Madison Heights, WI.

Nov 19, 1998, “CMOS inverter VCO tunes octave to UHF,” ShawnStafford, AM Communications Inc, Quakertown, PA.

Dec 3, 1998, “Eight-channel data-acquisition system features auto-calibration,” Mark Shill, Burr-Brown Corp, Tucson, AZ.

Dec 17, 1998, “Circuit eases three-phase monitoring,” HennoNormet, Tavares, FL.

Every month readers pick one Design Idea from the issue as the winner. Congratulations to all the winners, andkeep the innovative ideas coming.

128 edn | June 10, 1999

EDN selects 1998 Design Ideasgrand-prize winners

You can assemble a differentialmonitoring display using rail-to-railanalog hardware and a 12C671

eight-pin controller (Microchip Tech-nology, www.microchip.com) (Figure 1).The controller, IC

1, reads the scaled ana-

log input reference into its internal ADCat an approximately 3-msec rate. Thecontroller’s program provides a dynam-ic display to the four LEDs based on thedeviation from an initially set sensor ormonitored value. The “rolling” displaymoves from end to end at a rate based onthe direction and magnitude of the de-viation.You can download the accompa-nying program from EDN’s Web site,www.ednmag.com. Click on “SearchDatabases” and then enter the SoftwareCenter to download the file for DesignIdea #2373.

To use the circuit, you apply the refer-ence level and adjust the gain at Pin 7 ofIC

2Bto bring the display to an “all-lite”

condition. This adjustment artificiallysets the reference to half of the internalADC’s span. The absolute value of thedeviation about this reference setting isscaled into eight equal steps above andbelow this fixed reference to the limits ofthe converter. For a 5V application, thisresults in approximately 0.31V indexes((5/2)/8). The circuit passes the resultingindex to a rate table, which sets the dis-play update period. A second indexpointer increments each time the dis-play’s update period times out. Positivedeviations from the reference incrementthis mask pointer, and negative devia-tions decrement the pointer. This secondpointer then indexes through a mask

table, which defines the display’s pattern.The controller uses 127 bytes of code

with the eight-step rate table, the rela-tively small display, and the related 7-bytemask sequence. A stable reference, IC

3,

reduces the display’s drift over time andtemperature.

Although this format is too inflexibleto use for all types of monitoring, youcould add filtering and span and offsetadjustments to provide a more flexibledeviation display. You could also imple-ment an expanded display using a16C710 mC (MicroChip Technology), anexternal PLD, or one of several 74xx de-coders. (DI #2373)

The controller’s program for this differential monitoring display provides a dynamic display to thefour LEDs based on the deviation from an initially set sensor or monitored value.

12C6711

2

3

4

8

7

6

5

560

560

560

560

VCC

10.0k

10.0k

VCC

+

2

+

2

10

9

VREF

8

4.7k

IC3LM4040-2.5

4.7k

4.7k

7

+

2

10.0k

4

VCC

6

5IC2B

20k

IC2AMAX47530.1k

30.1k 2

3

S2

S+

SENSOR+12

POWER+12

GND

POWER GND

IC1

4.7k

1

11

10.0k



ideasdesign

Controller supports differentialmonitor display ............................................113

Ultrasonic range finder uses few components ..........................................114

Simple technique improves transient dynamics ......................................118

Multiplying DAC makes programmable resistor ..............................120

Equip switchers with overcurrent protection ................................122


Controller supports differential monitor displayWilliam Grill, Riverhead Systems, Littleton, CO

F igure 1


ideasdesign

An ultrasonic, or sonar, rangefinder is a common sensor in robot-ic systems and industrial environ-

ments. Even home and automotive usesare possible. A novel sensor design con-sists of a mC, a few peripheral compo-nents, and a pair of ultrasonic transduc-

ers (Figure 1). The range-finder moduleconsists of a mC, a transmitter, a receiv-er, a direct-receive inhibit circuit, and anRS-485 interface. The module’s usablerange is approximately 4 in. to 16 ft withan accuracy of approximately ±2 in. Thisperformance is sufficient for many in-

dustrial, automotive, and robotic uses.Measuring distance with ultrasonic

signals requires a transmitting ultrason-ic transducer; a medium, such as air orwater; a reflecting surface or object; a re-ceiving ultrasonic transducer; and atime-of-flight measurement circuit. The

Ultrasonic range finder uses few componentsDaniel R Herrington, National Semiconductor, Arlington, TX

TRANSMITMA40B8S

(a) (b)

(c) (d)

(f)

(e)

T1200:8

IC1

TXPOS

32 pF

32 pF

10 MHz

mCIC2

INIT

RS-485 INTERFACE

DECOUPLING CAPACITORS

DIRECT-RECEIVE INHIBIT

RECEIVER

INIT

47k

REF

D31N4148

R1

R21M

5V

5V

5V

5V

5V

5V

0.01 mF

0.01 mF

100k

1k 1M

100k

100k

3.9k

RECEIVEMA40B8R

10 mF

0.001 mF

ECHOC7

0.001 mF D2

1N60

D11N60

C2

C1

IC4

5

2

43

1

LMV821

100 mF 0.1 mF 0.1 mF 0.1 mF0.015 mF

IC3 VCC

J1RJ11 6P4C

40

3938

34

33

TXNEG

TXPOSCMPOUT

RDATAROREDE

DI

VCCDO

DOGND

TXD2

TXD+

123

4

87

65

TENA

TDATA

101112

6

1

7

8

G7/CK0

C2 C1

RESET

GND

C0G3/T1A

F1/CMP1IN2

F2/CMP1IN+

F3/CMP1OUT

L1/CKX

L2/TDX

L3/RDX

COP8SGR740Q3

CKI

VCC

TENA

TDATA

RDATA

REF ECHOCMPOUT

20

19

18

TXNEG

74HCT041

3

5

9

11

13

4

2

6

8

10

12

++

+

–

0.2 mF

DS36F95

TRANSMITTER

1 32 4

The range-finder module consists of five main subcircuits: a transmitter (a), a mC (b), a receiver (c), a direct-receive inhibit circuit (d), and an RS-485interface (e), in addition to the requisite decoupling capacitors (f).

F igure 1


ideasdesign

speed of sound in air at 20-C is approxi-mately 343m/sec, which translatesto about 1 in. per 74 msec. Dou-bling the time gives you the round-tripspeed, which is 1 in. per 148 msec. Fouraspects of the system limit the maximummeasurable distance: the amplitude ofthe sound wave, the texture of the re-flecting surface, the angle of the surfacewith respect to the incident sound wave,and the sensitivity of the receiving trans-ducer. The receiving transducer’s directreception of the sonar pulse—and notthe echo—usually dictates the minimummeasurable distance. Although you canuse a discrete timer circuit to measure thetime of flight, a mC can simplify the hard-ware design. Using a mC makes it easy tostore and serialize the data and thentransmit it to a PC or other master con-troller. The COP8SGR mC from Nation-al Semiconductor (www.national.com)includes peripheral blocks, such astimers, analog comparators, and a hard-ware UART. These peripherals reduce theamount of external hardware or internalsoftware necessary to process the senso-ry data.

In Figure 1, the mC, IC2, waits for an

“address” from a host controller over theRS-485 interface. When it receives thecorrect slave address, IC

2begins a 250-

msec pulse of 40 kHz to the ultrasonictransmitter circuit. The mC outputs ahigh INIT signal to charge C

1. During the

transmit pulse, IC1

drives audio trans-former T

1in a push-pull manner to gen-

erate about 40 to 50V p-p across thetransducer. In Figure 1, the transmit andreceive transducers are the matchingMA40B8S and MA40B8R (MuRata,www.murata.com), respectively. At theend of the transmit pulse, the mC bringsthe INIT line low again and C

1discharges

through R1

to the level that voltage di-vider R

1/(R

1+R

2) dictates. D

3keeps the

current from flowing back into IC2’s

PORTC2 (INIT) pin.The circuit uses the decaying voltage

on the REF signal as a reference for theincoming echo (Reference 1). Op ampIC

4amplifies the echo from the receive

transducer. After amplification, D1

andD

2rectify the signal to a positive voltage.

C2

smoothes the resulting signal, and thecircuit sends this preprocessed echo sig-

nal to IC2’s onboard analog comparator.

The CMPOUT signal feeds back intoIC

2’s T1A pin to perform an input-cap-

ture operation on the result of the com-parison. A positive edge on the T1A pincauses IC

2’s Timer 1 to latch the current

countdown value in microseconds. Sub-sequent scaling reduces the 16-bit meas-urement in microseconds to an 8-bit val-ue that represents distance in inches. Thecircuit transmits this 8-bit value backover the RS-485 interface, IC

3, to the host

controller.An assembly-code program performs

all of the software processing necessaryfor ultrasonic distance measurement.The program is available for download-ing from EDN’s web site, www.ednmag.com. Click on “Search Databas-es”and then enter the Software Center todownload the file for Design Idea #2371.

Figure 2 shows an example of the threewaveforms: REF, ECHO, and CMPOUT.The comparison of the ECHO and REFsignals effectively inhibits the large-am-plitude signal received directly from thetransmitter at time t=0.2 msec. Thismethod allows the minimum measurabledistance to be as low as approximately 4in. This method also eliminates the needfor an ADC, as well as the problems as-sociated with defining a threshold valuebased on some moving average of echosamples.

You can improve the module byadding multiple-echo-detection capabil-ity, which allows a single transmitted ul-trasonic pulse to recognize two or moreobjects at different distances (Figure 2).You can also incorporate this capabilityby having the program store the capturevalue for the first echo, at time t=5 msec,for example, and then re-enable the in-put-capture countdown and wait for thesecond capture at time t=9.4 msec, andso on. Another possible improvement isto add servo control to the circuit usingone of the internal timers in mode. Youcan control hobby servos that you com-monly find in radio-controlled toys witha 1- to 2-msec-wide positive pulse every20 msec. In PWM mode, the mC’s timersrequire the loading of only a high widthvalue and a low width value to generatethis type of output signal. If you add ser-vo control, you can use the sonar mod-ule to measure distance in a given direc-tion. (DI #2371)

Reference1. Ultrasonic Sensor Application Man-

ual, MuRata Electronics North AmericaInc, Smyrna, GA, www.murata.com.

By comparing the ECHO and REF signals, the range-finder circuit effectively inhibits the large-amplitude receive signal at time tt0.2 msec.

F igure 2

5

6

4

3

2

1

0

0.2 TIME (mSEC)

VOLT

AGE

(V)

9.4

REF

ECHO

CMPOUT


EHCO FROMNEAR OBJECT

REFERENCE

FALSE ECHO(DIRECT RX)

EHCO FROMFAR OBJECT


ideasdesign

Designing low-voltage, high-cur-rent converters with fast dynamicperformance places stringent de-

mands on a system designer. However, asimple technique reduces the peak volt-age deviation and decreases the responsetime for a transient load step (Figure 1).This circuit converts 48V dc to 1.5V at15A using a two-transistor forward con-verter with synchronous rectifiers. Q

1

and Q3are primary-side switches. Q

2and

Q4

are the secondary-side rectifiers. IC1

and IC2, a pair of dual MOSFET drivers,

provide the gate drive. The circuit derivesthe power for IC

2by rectifying the peak

secondary voltage. This feature, which al-lows IC

2to operate with a 6V supply in-

stead of a 12V supply, reduces gate-drivelosses without any significant increase inrectifier conduction losses. IC

3, a high-

power, synchronous switching-regulatorcontroller, is at the heart of the PWMcontrol. R

1and C

1set the oscillator fre-

quency to just under 200 kHz and limitthe maximum duty cycle to 50%.

IC4, a programmable reference, func-

tions as an error amplifier, overridingIC

3’s internal g

mamplifier. This design

feature allows for greater control in tai-loring the frequency-response character-istics and provides much greater accura-cy. You can implement an added featurefor output-voltage programming usingthe summing junction at the REF pin

node. Differential amplifier IC5A

allowsreal remote sensing of the output volt-age and makes it possible to produce out-put voltages well below the 2.5V refer-ence of IC

4.

The circuit configures C2, R

2, and C

3in

a classic Type 2 feedback-amplifier net-work. The center oscilloscope trace inFigure 2 shows the response to a 100-nsec load step of 5 to 15A (100A/msec).The peak-to-peak deviation is 96.8 mVwith a settling time of approximately 40msec.

Modifying the feedback network canproduce significant improvement. Short-ing C

2with S

1limits the dc gain of the

error amplifier, causing the output volt-

Simple technique improves transient dynamicsRobert Sheehan, Linear Technology Corp, Milpitas, CA

A two-transistor forward converter, Q1 and Q3, with synchronous rectifiers Q2 and Q4 converts 48V dc to 1.5V at 15A.

RUN/SD

VIN

VOUT1.5V15A

301k

10k

100

MBR0530S1 C2

680 pFC3

100 pF

BAS16

1.56k 30.1k

GAIN=3 30.1k

0.1 µF

IC5ALT1431

10k

10k

100

+SENSE

2SENSE1.96k 100

FOLDBACKILIM

12V

MMBT3906

R233.2k

ERRORAMP

S+

100

470 mF6.3V

+ 1.5 mF63V

1 mF 1 mF100

12VSUPPLIED

SEPARATELY MURS120

S2 12V IN BOOST

TG

BG

TS

VIN

12V

C1

R12.49k

IC3LT1339

1.8nF

0.1mF

0.1mF

0.1 mF

0.1mF

100pF

1 mF

Q1

Q3 Q4 Q2

LT1693-2

MURS12022

13:2

4.7 nF

MBR0530

LT1693-2

1.5 mH

470mF

6.3V28

+

5.1

48VDC

5VREF

CT

12V V+

GND-F GND-S

REF

COLL

LT1431IC4

SSVREF IAVG

VFBSGND

PGNDVC

IC2AIC2BIC1B

IC1A

+–

0.068

NOTES:Q1 AND Q3=MTD20N06.Q2 AND Q4=SI4420.

F igure 1


ideasdesign

age to deviate 615 mV around itsnominal value at half-load.This modification programsthe output voltage to move slightly inthe direction in which it already wantsto go when the load steps. This changealso removes the long tail in the set-tling response because there is no RCcharging in the error-amplifier feed-back path. The improvement is dra-matic, as the top trace in Figure 2shows. The peak-to-peak deviationdecreases by 30% to 66.4 mV. Thefull-load-to-light-load settling timedecreases to 20 msec. The light-load-to-full-load settling time is virtuallyinstantaneous. (DI #2370)

F iigguurree 11 shows a configurationthat implements a digitallyprogrammable resistor using

a quad op amp and a multiplying DAC.The circuit is equivalent to a voltage-con-trolled resistor. The simulated resistorhas a value that reflects the ratio of a fixedresistor (R

X) and a control voltage. Ap-

plications include generating precise re-sistance values for remotely controllingmonostable multivibrators and config-uring voltage-controlled loads in simu-lation circuits. The circuit provides lin-ear control of resistance using theAD7538 14-bit multiplying DAC. Youcan obtain logarithmic control of the re-sistance by using an AD7111A logarith-mic DAC as the voltage-control element.

Analysis of the circuit in Figure 1 re-veals the following:

where D is input code to the multiplyingDAC.

If R1=R

2=R

3, then

The circuit in Figure 1 operates as a

voltage-controlled current source. Youcan adapt it for use as a basic functionalblock in the design of a biquad filter. Inthe adaptation, you modify the circuit toprovide a voltage-controlled capacitorrather than a resistor. (DI #2384).

Multiplying DAC makes programmable resistorAlbert O’Grady, Analog Devices Inc, Limerick, Ireland

A multiplying DAC implements a linear, digitally programmable resistor.

The peak-to-peak deviation with S1 open is 96.8 mV (center trace). Closing S1 to short C2 decreasesthis deviation to 66.4 mV (top trace.)

F igure 2

+

+

2

2

+

2

+

2

IC4

IC3

IC1 IC2AD7538

R3

V2

V1

V3

IIN

VIN

VIN

RX

10k

R210k

R410k

R110k

2DVIN

F igure 1



TRANSIENT RESPONSE

WITH S1 CLOSED (40 mV/DIV)

TRANSIENT RESPONSE

WITH S1 OPEN (40 mV/DIV)

LOAD STEP (10A/DIV)

OUTPUT-VOLTAGE TRANSIENT RESPONSE

66.4 mV

96.8 mV

20 mSEC/DIV

( ), DVVRR

RVV ININ

21

2IN1 +

+= 1

.RR

RV1V

43

312

++= .

D

R

R/DV

VR

and ,R

DV

R

VVI

,DVVV

X

XIN

ININ

X

IN

X

2ININ

ININ2

==

==

=1

1

ideasdesign

Overcurrent protection is usual-ly a necessary design feature of aswitch-mode power supply to safe-

guard both the switcher and the load.Most PWM control ICs have internalovercurrent-protection circuits, and youcan typically add auxiliary circuitsaround the IC to enhance this protection.For example, simple circuits enhance theoperation of the common family ofUC3842/3/4/5 (Unitrode Corp, www.unitrode.com) PWM-control ICs (Fig-ure 1). These circuits allow the switcherto respond to an overcurrent fault con-dition by latching off if the overcurrentcondition persists for more than somedefined time interval or by cycling off andthen on again at a low duty cycle until thefault clears. When the fault clears, theswitcher then resumes normal operationon the next restart cycle. You can addthese circuits without affecting other de-sirable features that the PWM IC may al-ready include, such as soft start and max-imum current-limit clamping.

In most switcher designs, operation incurrent limit imposes the greatest stresson the power devices. Therefore, de-creasing the time that the switcher mustoperate in current-limit mode can en-hance the reliability of the switcher. Insome cases, decreasing this time may evenresult in reduced heat-sinking require-ments for the power devices. A designthat doesn’t permit sustained operationin current-limit mode can have a loweraverage power dissipation than a designthat permits a longer time in current-lim-it mode.

The circuits function solely by manip-ulating Pin 1 of the PWM IC; theschematics omit all other details of thePWM IC because the remainder of theIC’s operation stays the same. In theUC384x family of control ICs, Pin 1 is theoutput of the internal error amplifier.The voltage at Pin 1 controls and is di-rectly proportional to the peak currentlevel in the main power-switching tran-sistor. Therefore, Pin 1 is a logical place

to exert control of the switching current.The circuit in Figure 1a is a common-

ly used network that adds a slow-startfeature as well as maximum current-lim-it clamping to the PWM- control circuit.The IC’s internal error amplifier sourcesonly a limited amount of current, typi-cally 0.8 mA. Therefore, pnp transistor Q

1

easily clamps the voltage at Pin 1 to 0.6Vhigher than the voltage at its base by di-verting the current from Pin 1 through itscollector to ground. Thus, the voltage di-vider of R

1and R

2determines the clamp-

ing voltage at Pin 1. This voltage sets themaximum current limit of the mainpower-switching transistor.

A logical conclusion is that adding acapacitor, C

1, from the base of Q

1to

ground will allow a ramp-up character-istic for the clamped voltage at Pin 1 and,therefore, will allow an analogous ramp-up characteristic for the power-switchcurrent. This ramp-up characteristic isusually a desirable feature for initialswitcher start-up because it allows the

5V REF8

2N3906

1IC1

Q1

C1

R1

UC3842/3/4/5-BASED SWITCHER10k

R247k 1 mF

(a)

5V REF8

2N3906

1IC1

Q1

C1

R1A

UC3842/3/4/5-BASED SWITCHER

4.7k

R1B4.7k

R247k 1 mF

C2

R4

IC2BIC2A

R6R3 1 mF

(b)

1.5M

1.5M

CYCLING

LATCHING1.5M

100k

R7

R8

R5 1.5M5

2

34

81 6

7

390+

2

+

2

390 1k

33k

LM393

F igure 1

Equip switchers with overcurrent protectionRobert N Buono, Buono Consulting, Ringwood, NJ

Manipulating Pin 1 of a UC384x switcher allows you to add more overcurrent protection (a). A dual-comparator circuit allows for cycling or latching offwhen the switcher is in current-limit mode (b).



ideasdesign

switcher’s output voltage toramp up in a con-trolled manner, re-ducing output-voltage over-shoot. The 5V REF supplyin Figure 1 is a precisionvoltage reference that IC

1

develops internally. This 5VREF is commonly used topower auxiliary circuits; thisoutput delivers as much as20 mA. The circuits in Fig-ure 1 are very low-power,and draw only a small frac-tion of that available cur-rent.

The design in Figure 1badds a low-cost, dual-com-parator circuit to the net-work at Pin 1. R

2and C

1re-

main the same, but thiscircuit splits R

1into R

1Aand

R1B

. R3is an additional com-

ponent in the collector legof Q

1. Whenever Q

1clamps

the output of IC1’s Pin 1, a

voltage develops across R3.

This voltage indicates theonset of current limiting. R

3

does not interfere with thesoft-start and maximum-current-limit clamp per-formance.

Cycling occurs when youinstall R

4and remove R

5.

When the switcher is in cur-rent-limit mode, a voltageof approximately 400 mVdevelops across R

3. When

the voltage across R3exceeds

the voltage at IC2A

’s Pin 2,which is approximately 150mV, the output at IC

2A’s Pin

1 becomes an open-collec-tor output and allows C

2to charge

through R4. The time it takes for C

2to

charge from approximately 0V to thethreshold established at IC

2B’s Pin 5 is the

“fault-delay time.” During fault-delaytime, the switcher remains on and in cur-rent-limit mode. IC

2Bfunctions as a low-

frequency oscillator with low duty cycle.When the voltage on C

2exceeds the volt-

age on IC2B

’s Pin 5, the open-collectoroutput of IC

2Bswitches low. This low lev-

el pulls the base of Q1

to ground throughR

1B, and the voltage at Pin 1 of IC

1clamps

to approximately 0.6V. When Pin 1 of IC1

is less than approximately 1.1V, currentthrough the power-switching transistoris 0A, and the switcher is off.

The resistor ratios of R6, R

7, and R

8de-

fine the duty cycle of the low-frequencyoscillator. For the values shown, the dutycycle is approximately 12%; the switcheris off for 1.4 sec and on for 200 msec.Each time the switcher restarts, it does sowith soft start because the output of IC

2B

fully discharges C1through R

1B.When the

circuit pulls the base of Q1

low, collector

current continues toflow; the circuit main-tains the voltage acrossR

3even when the switch-

er is off. IC2B

continuesto cycle until the over-current fault clears.When the fault clears, thecircuit reestablishes thenominal output voltageof the switcher, and thevoltage at IC

1Pin 1 drops

below the clamp level.The voltage across R

3

drops to 0V and ensuresan open-collector outputat IC

2B’s oscillator out-

put.Removing R

4and

adding R5

causes theswitcher to latch off andnot restart, in responseto current limit. You canadjust the ratios of R

6, R

7,

and R8

to optimize thefault-delay time. Increas-ing the threshold voltageat IC

2B’s Pin 5 increases

the fault-delay time be-fore latch-off.

Oscilloscope wave-forms (Figure 2) showthe power-switch cur-rent cycling on and offwhen the switcher is incurrent-limit mode (Fig-ure 2a). A time expan-sion of the ramp-charac-teristic of the power-switch current for eachrestart event shows thateach restart benefitsfrom the soft-start char-acteristic (Figure 2b).

These waveforms are the result of meas-uring the voltage across a current-sens-ing resistor; the waveforms represent thecurrent through the main power-switch-ing transistor switching at 50 kHz.(DI#2369)

The power-switch current cycles on and off when the switcher is in current limit(a). Each restart benefits from soft start (b).


F igure 2

TIME (5 mSEC/DIV)

TIME (0.5 SEC/DIV)

VOLT

AGE

ACRO

SS C

URR

ENT-

SEN

SERE

SIST

OR (

1V/

DIV

)VO

LTAG

E AC

ROSS

CU

RREN

T-SE

NSE

RESI

STOR

(1

V/D

IV)

(a)

(b)




Name

Title

Phone

E-mail Fax

Company

Address

Country ZIP

Design Idea Title





Signed

Date



ideasdesign

Entry blank must accompany all entries. $100 Cash Award for all published Design Ideas. An additional $100 Cash Award forthe winning design of each issue, determined by vote of readers. Additional $1500 Cash Award for annual Grand Prize Design,selected among biweekly winners by vote of editors.


www.ednmag.com July 8, 1999 | edn 93

ideasdesignEdited by Bill Travis and Anne Watson Swager

O ccasionally, a system needs sev-eral digitally programmable volt-age-output channels.

Such output channels typi-cally provide the control for robot posi-tioning, industrial processes, and evenhome automation. The circuit in Figure1 (pg 94) controls 32 voltage-outputchannels from the parallel port of a PC.The circuit comprises eight DAC7615quad voltage-output, serial-data pro-grammable, 12-bit DACs. The control-ling PC individually programs each of the32 DAC channels, and all DAC outputssimultaneously update.

The parallel port’s eight data-outputlines provide serial data into each of theeight quad DAC7615s. The remainingfour control lines of the parallel port pro-vide the serial-data clock, input-registerclock, DAC-register clock, and DAC-re-set functions. Each DAC7615 has a ref-erence high and low input, which the cir-cuit connects to external referencevoltages of 2.5V and 22.5V, respectively.Two OPA4277 quad op amps buffer the±2.5V DAC reference voltages. Becauseall of the DACs use the same ±2.5V ref-erence voltages, all DAC outputs track to-

gether as a function of these references.The resulting DAC output-voltage rangefor all 32 channels is 22.5V to +2.5V.

The circuit programs each of the eightDAC7615s by shifting in a serial 16-bitword comprising two address bits, twodummy bits, and the DAC 12-bit dataword. The serial data for the V

OUTAchan-

nel of each DAC7615 shifts in first, fol-lowed by the V

OUTB, V

OUTC, and V

OUTD

channels. The DAC7615s have a double-buffered data input, so the circuit canload the programmed data for all DACchannels into input registers withoutchanging the previously set DAC outputvoltage. After each 16-bit word shifts intothe corresponding DAC7615, the DACcontrol line LOADREG momentarilypulses low to latch the shifted data intoeach DAC’s internal input register. Final-ly, when the circuit has programmed allDAC input registers, the signal LOAD-DACS pulses low to update the internalDAC registers and change all DAC out-puts.

To use the parallel port for simultane-ous serial data transmission to allDAC7615s, the software must first ma-nipulate the digital output data to placeit in a form that can stream out the par-allel port. The controlling software trans-poses a group of eight 16-bit words, rep-resenting the codes to shift into each

DAC7615, into a group of 16 8-bit words(Figure 2). The resulting vector of 16 8-bit words represents the 16-bit serial datastream, which the circuit simultaneouslyshifts into the selected one-of-four reg-isters of the DAC7615s. This transposi-tion repeats four times to program allfour channels of each DAC7615.

The accompanying program “Write-DAC32,”which is written in Borland Tur-bo Pascal, accepts an array of 32 12-bitcodes for programming each of the DACchannels. WriteDAC32 uses an assembly-language procedure to repeatedly left-shift the leading bit of each 12-bit DACcode and then reconstruct 12 8-bit wordsrepresenting the stream data that the PCoutputs on all eight of the parallel port’sdata lines. To program all 32 DAC chan-nels, 4216 data-clock cycles are neces-sary. If you daisy-chain the DACs, thenumber of necessary clock cycles is428216. You can download the pro-gram from EDN’s Web site, www.ednmag.com. Click on “Search Databas-es/Links Page” and then enter the Soft-ware Center to download the file fromDI-SIG, #2347. (DI #2347)

Control 32 DAC channels via a parallel port ..........................................93

Comparator has programmablelimits ..................................................................96

DAA circuit emulates central-office operation ..............................................98

Speedy logic translator uses little power ..........................................100

Parallel port replaces embedded mC..............................................102

Transimpedance amp covers dc to gigahertz range ................................104

Simple scheme detects shorts ..................106 To Vote For This Design,Circle No. 346

Control 32 DAC channels via a parallel portMark A Shill, Burr-Brown Corp, Tucson, AZ

A series of eight quad-output voltage DACs provide 32 channels that you can individually program.All of the DACs simultaneously update.

A11 A01 A02 A03 A07 A08A01 0 0 C1,11 C1,10 C1,9

A02 0 0 C2,11 C2,10 C2,9

A03 0 0 C3,11 C3,10 C3,9

C1,1 C1,0

A12

A13

A07 0 0 C7,11 C7,10 C7,9A17

A08 0 0 C8,11 C8,10 C8,9

C7,1 C7,0

C8,1 C8,0A18

C1,11 C2,11 C3,11 C7,11 C8,11

C1,10 C2,10 C3,10 C7,10 C8,10

C1,1 C2,1 C3,1 C7,1 C8,0

C1,0 C2,0 C3,0 C7,0 C8,0

0 0 0 0 0

0 0 0 0 0

A11 A12 A13 A17 A18

C2,1 C2,0

C3,1 C3,0

F igure 2

SDI

CLK

REFH REFL GND VSS VOUTA

VOUTB

VOUTC

VOUTD

VOUTA

VOUTB

VOUTC

VOUTD

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

DAC7615

5 4 9

LOADDACS

LOADREG

RESET

RESETSEL

CS

++

SDI

CLK

REFH REFL GND VSSCHANNEL 5

CHANNEL 6

CHANNEL 7

CHANNEL 8

DAC7615

5 4 9

LOADDACS

LOADREG

RESET

RESETSEL

CS

++

SDI

CLK


CHANNEL 10

CHANNEL 11

CHANNEL 12

DAC7615

5 4 9

LOADDACS

LOADREG

RESET

RESETSEL

CS

++

SDI

CLK


CHANNEL 14

CHANNEL 15

CHANNEL 16

DAC7615

5 4 9

LOADDACS

LOADREG

RESET

RESETSEL

CS

++

G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8

G1 A1 A2 A3 A4 A5 A6 A7 A874HC541

13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1

1 2 3 4 5 6 7 8 9

19 18 17 16 15 14 13 12 11

2

+ 13

2

4

11

5V

25V

0.01

2

+ 75

6

0.01

2

+ 810

9

0.01

2

+ 1412

13

0.01

100

100

74HC04

0PA4277

5V

10

11

12

13

14

15

16

10

11

12

13

14

15

16

10

11

12

13

14

15

16

10

11

12

13

14

15

16

7

6

3

2

7

6

3

2

7

6

3

2

7

6

3

2

11

VDD

1 8

+

+5V

25V

1

1

VDD

1 8

+

+5V

25V

1

1

VOUTA

VOUTB

VOUTC

VOUTD

VDD

1 8

+

+5V

25V

1

1

VOUTA

VOUTB

VOUTC

VOUTD

VDD

1 8

+

+5V

25V

1

1

11

5V

5V

5V

11

11

22.5VSYSTEMREF LOW

2.5VSYSTEM

REF HIGH

100

100

F igure 1

94 edn | July 8, 1999 www.ednmag.com

ideasdesign

SDI

CLK


CHANNEL 18

CHANNEL 19

CHANNEL 20

DAC7615

5 4 9

LOADDACS

LOADREG

RESET

RESETSEL

CS

++

SDI

CLK


CHANNEL 22

CHANNEL 23

CHANNEL 24

DAC7615

5 4 9

LOADDACS

LOADREG

RESET

RESETSEL

CS

++

SDI

CLK


CHANNEL 26

CHANNEL 27

CHANNEL 28

DAC7615

5 4 9

LOADDACS

LOADREG

RESET

RESETSEL

CS

++

SDI

CLK


CHANNEL 30

CHANNEL 31

CHANNEL 32

DAC7615

5 4 9

LOADDACS

LOADREG

RESET

RESETSEL

CS

++

2

+ 13

2

4

5V

25V

0.01

2

+ 75

6

0.01

2

+ 810

9

0.01

2

+ 1412

13

0.01

100

100

100

100

7

6

3

2

7

6

3

2

7

6

3

2

7

6

3

2

VOUTA

VOUTB

VOUTC

VOUTD

10

11

12

13

14

15

16

10

11

12

13

14

15

16

VDD

1 8

+

+5V

25V

1

1

VOUTA

VOUTB

VOUTC

VOUTD

VDD

1 8

+

+5V

25V

1

1

VOUTA

VOUTB

VOUTC

VOUTD

VDD

1 8

+

+5V

25V

1

1

VOUTA

VOUTB

VOUTC

VOUTD

VDD

1 8

+

+5V

25V

1

1

5V

5V

10

11

12

13

14

15

16

10

11

12

13

14

15

16

5V

5V

11

11

1 1

1 1

0PA4277

NOTE: ALL CAPACITORS ARE IN MICROFARADS.

The controlling software transposes eight 16-bit words into a vector of 16 8-bit words.



ideasdesign

The circuit in Figure 1 combines adual buffered D/A converter and dualfour-input comparator to configure

a comparator circuit with a digitally pro-grammable window center and width.The circuit has three outputs that sepa-rately indicate the comparisonstates: within the window, overthe upper limit, or below the lower lim-it. With the component values shown,you can program the center voltage of thewindow from 1110.24 to +10.235V in 5-mV steps, and the width of the windowfrom 0 to 20.47V, also in 5-mV steps. Theprogrammed values are fully independ-ent of each other and of the input volt-age. The dual buffered DAC-8222, to-gether with three op amps from anOP-400, generates the voltages V

X(center

voltage for the LTC1040) and VY

(half thewindow width) from binary data stored

in the DAC’s latches. Whereas DAC A ofthe DAC-8222 operates in a bipolar con-figuration, DAC B operates in unipolarmode. A mP’s address bus generates theDAC’s control signals DAC-A/DAC B,

LDAC, and WR. The reference voltage forthe V

REFAand V

REFBinputs of the DAC-

8222 comes from the REF08, configuredfor a S10.24V output. The LTC1040 con-tains two sampling-mode comparators

Comparator has programmable limitsMichele Frantisek, Brno, Czech Republic

DB0 VDD

12 17

6

5

18

19

20

24 23 2 3

21

4

22

15V

1 mF

215V

215V

215V15V

15V

(210.24V)DB11

DGND

DAC-8222

DAC2A/DAC2B

LDAC

WR

IOUTB RFBB IOUTA

VREFA

VREFB

VIN

AGND

RFBA

VOUT VIN

REF08

OP400

10k, 0.1% 20k, 0.1%

20k0.1%

4

1

6

5 34 11 10

5k1%

7 2 1 9

8

1

7

5

SELECT GND

9 1

10 18

16

100k

3

15

6

14

5

13

8

11

7

12

4

2+

2+

2+

2AIN2

VX

VY

BIN1

LTC1040

OSC

OUT 1

10 nF

OUT 2

OUT 3

GND STROBE

AIN1

2BIN2

2AIN4

2BIN4

AIN3

BIN3

AOUT

BOUT

A+B

F igure 1

FORM OF WINDOWLATCHED INPUTDATA IN DAC A

LATCHED INPUTDATA IN DAC B

VX VY

0V 1V

1V

1V

2V

2V

0V1V

21V

24V

21V

3V

1000 0000 0000DECIMAL 2048

0111 0011 1000DECIMAL 1848

1000 1100 1000DECIMAL 2248

0001 1001 0000DECIMAL 400

0001 1001 0000DECIMAL 400

0100 1011 0000DECIMAL 1200

A precision comparator uses a D/A converter to provide precise, noninteractive control of the upper and lower thresholds.

Examples of VX and VY and their digital equivalents are stored in the DAC’s latches.

F igure 2


ideasdesign

that drive the three outputs of the circuit.Output Out 1 assumes a logic-high stateif the algebraic sum of the voltages at A

IN1,

AIN2

, AIN3

, and AIN4

is positive, as the fol-lowing equations show: V

IN2V

XL0;

therefore, VIN

LVX+V

Y. Out 1 thus as-

sumes a high state if VIN

is greater thanthe upper limit of the window (V

X+V

Y).

Similarly, Out 2 assumes a high state ifthe sum of voltages B

IN1, B

IN2, B

IN3, and

BIN4

is positive: VX

2VIN

2VYL0; there-

fore, VIN

lVX2V

Y. Thus, Out 2 goes high

if the value of VIN

is lower than the bot-tom limit of the window (V

X2V

Y). Fi-

nally, Out 3 assumes a high state if bothOutput 1 and Output 2 are low:V

X2V

YYlV

INlV

X+V

Y. Thus, Output 3

goes high if the value of VIN

is greaterthan the lower limit and lower than theupper limit of the window. The RC com-bination at Pin 16 of the LTC1040 deter-mines the sampling rate; in this case, ap-

proximately 1000 samples/sec. Figure 2gives some examples of V

Xand V

Yand

their digital equivalents stored in theDAC’s latches. The circuit needs no cali-bration and produces maximum errorsof 510 mV over the full range. (DI#2377)


The Mitel MH88422 data-accessarrangement (DAA), a thick-film hy-brid module, contains a

complete interface between du-plex voice- or data-transmission equip-ment and an analog telephone line. Itprovides transformerless, optoisolatedtwo-to-four-wire conversion with trans-hybrid loss cancellation and operatesfrom a 5V supply. The DAA also con-sumes low on-hook power. Figure 1agives Mitel’s typical application circuit.The Tip and Ring lines connect to a cen-tral-office or private-branch-exchangeline, and the interface mimics the oper-ation of a telephone set. The modifica-tion in Figure 1b changes the function ofthe interface such that an ordinary sin-gle-line telephone can connect directlyto such systems as a voice/touch-tone pe-ripheral device.

In this configuration, line-control(LC) input is always active. When thetelephone goes off-hook, the path frombattery to ground closes. Line currentflowing in the sense resistor in theMH88422 activates ring voltage/line cur-rent (RVLC), thereby signaling the off-hook state to the system controller. Ana-log functions are as in the originalconfiguration; that is, you can transmitand receive signals. The modified system

provides no ring signal and thus can serveonly incoming calls; nevertheless, the in-terface operates much like a central-of-fice arrangement. (DI #2376).

DAA circuit emulates central-office operationJerzy Chrzaszcz, Warsaw University of Technology, Poland

(a)

654321

TIP

RLS RVLC

LC

TF

TXIN

RING

VX

VR

RJ 11

14

MH88422

13

11

10

9

3

4

6

7

LINE CONTROL

CURRENT SENSE

VOICE OUTPUT

VOICE INPUT

(b)

654321

TIP

RLS RVLC

LC

TF

TXIN

RING

VX

VR

RJ 11

14

MH88422

13

11

10

9

3

4

6

7

LINE CONTROL

CURRENT SENSE

VOICE OUTPUT

VOICE INPUT

VBAT

F igure 1

A modification (b) of a DAA’s recommended interface (a) provides central-office-like operation forsingle-line telephones.



ideasdesign

In handheld equipment, componentcount and power consumption arecritical considerations. This Design

Idea uses only a few transistors to con-figure a high-speed outputstage of an RS-232Clink while drainingfew precious milliamperesfrom the batteries. In gener-al, the data to transmit comesfrom an IC (for example, anADC or a mC) connected to5V and ground. The RS-232C protocol requiresW12V transmission levels.You can derive the voltagesdirectly from the RS-232Cline of a computer with asimple diode circuit. Youneed a charge pump only inthe case of a direct connec-tion to a printer because the12 and S12V may not beavailable simultaneously.

The translation fromW12V to 0/5V of the signalscoming from the RS-232C

link is easy to implement with a standardSchmitt trigger, such as a CD40106 orCD4584, with protection resistors in se-ries with the inputs. The circuit in Figure

1 translates in the other direction. Thecircuit has some shortcomings: It wastespower through R

1and R

2turning off Q

1

while Q2

is on. Also, the time constants

Speedy logic translator uses little powerDavis Magliocco, CDPI, Scientrier, France

Input-output delay and rise and fall times are all approximately 2 msec in Figure 2’s circuit.

This circuit provides TTL-to-RS-232C translation but suffers from highpower consumption and dissimilar rise and fall times.

A simple logic gate cuts power drain and provides high-speed operationwith symmetrical rise and fall times.

10k

51.1k

51.1k

51.1k

+Q2BC857

Q1BC846

Q3BC846

R2

R1

VCC12V

VOUT

51.1k

300

2.87k

3k

300

DC

+VIN5VDC

+VEE12VDC

12V

5V

212V

51.1k

300

VOUTVIN

300

Q2BC807-25

Q1BC817-25

Q4BC857B

Q3BC847B

51.1k

100k

100k

100k

100k

R1

R2

IC1

F igure 3

VIN

VOUT

F igure 1 F igure 2


ideasdesign

differ in turning Q1

and Q2

on; the out-put rise time can be 50% longer than thefall time. To obtain high speed and avoidtransmission errors stemming fromwrong bit length, you must lower all theresistor values, thereby raising powerconsumption.

The circuit in Figure 2 draws currentonly when turning Q

1or Q

2on.When the

output of IC1

is low, Q3

is on, and the re-verse-biased Q

4is off; no current flows

in R1and R

2. When the output of IC

1goes

high, Q3

turns off while Q4

turns on. Be-cause the two branches are symmetrical,the time constants are similar, and theoutput exhibits similar rise and fall times(Figure 3). With one-tenth the powerconsumption of the circuit in Figure 1,

the circuit achieves the same transmis-sion speed without risk of bit-length er-ror from asymmetrical rise and fall times.(DI #2378)


Many applications use an embed-ded processor, which has certainneeds: software, RAM, ROM,

board space, and others. Frequently, an-other host computer, usually a PC, con-trols the application. Using a singleCPLD, you can dispense with the em-bedded processor and let the PC directlycontrol your system via the PC’s parallelport (Figure 1). The CPLD mimics theaddress, data, and control buses of a stan-dard mC, such as an 8052, so you can usestandard mC interfaces and peripherals inyour system. The advantages you gleanfrom this arrangement are:

● You need no special develop-ment software for your embeddedprocessor. You can use standard PCsoftware. Thus, you need not devel-op software for two systems.

● You can dispense with the embeddedmC; its ancillary RAM, ROM, andcrystal oscillator; and other compo-nents.

● You free up space on your system’s pcboard.

● You can benefit from the PC’s com-puting power and its huge base ofready-made software.

The circuit in Figure 1 uses a standardparallel-port interface, which has 12 dig-ital outputs and five digital inputs, whichyou access via three successive 8-bit portsin the PC’s I/O space: Data Port—eightoutput pins: D(7:0); the Control Port—four outputs (three inverted): C3, C2, C1,and C0; and the Status Port—five inputs(one inverted): S7, S6, S5, S4, and S3.

The design fits in a small CPLD: Xil-

inx’s XC9536. The CPLD has three inter-nal 8-bit registers. One latches the high-address bus—A(15:8). The other twolatch the multiplexed low-address/Writedata, and the Read data—AD(7:0). ThePC writes address and data via the DataPort and reads data via the Status Port.Status Pin S6 provides an interrupt. TheControl Port generates the control signalsof the emulated processor, as well as theinternal control signals of the CPLD. Toimplement a write cycle, the PC issuesthree successive bytes on the Data Port:

the low-order address byte, the high-or-der address byte, and the data byte. TheControl Port generates the needed con-trol signals (Figure 2a). The system im-plements the read cycle by issuing the ad-dress in the same order and then readsthe data byte in two cycles: low-orderdata nybble and high-order data nybble(Figure 2b).

Note that, although the procedure isrelatively slow, it’s fast enough for mostapplications, because total I/O access isonly a fraction of the application-soft-

D(7:0)CK

CK

8-BIT REGISTER

XC9536 CPLDC1

C0LSWR

DSTRB

1k

5V

PARALLEL PORT

5V

DATA(7:4)

42100

8210k

AD(7:0)

A(15:0)

ALE

READ DATA

WRITE DATA

RDEN

INTERRUPT

MULTI-PLEXER

DATA(3:0)

C3

RD

WR

S6

C2

S7, S5,S4, S3

8-BIT REGISTER

8-BIT REGISTER

CKS

1k

1k

100

5V

1k

5VF igure 1

Parallel port replaces embedded mCEli Kohav and Leonid Grossman, ECI Telecom, Petah-Tikva, Israel

A CPLD and a PC’s parallel port save component count and board space by replacing an embeddedprocessor.


ideasdesign

ware time budget. The serially connect-ed 100V resistors degrade the slew rateof the signals routed to the PC to preventtransmission-line effects on the parallelport’s cable. The 1-kV pullup resistorsconnect to the open-collector signals onthe Control Port. The 10-kV pullup re-sistors eliminate floating conditions onthe AD(7:0) bus. This application needsno Reset signal. If your design needs one,you can generate it by using a memory-mapped port or an unused combinationof the control signals (Figures 2c and 3).In this case, you need a larger CPLD. (DI#2374)

RESETRDEN

ALE

(OPTIONAL)

A PC takes over a mC’s job in controlling the write (a) and read (b) cycles in an application; anoptional Reset generator (c) requires a somewhat larger CPLD.


You can exploit otherwise unused control sig-nals in Figure 1’s configuration to generate aReset signal.

F igure 3F igure 2

(a)

(b)

(c)

Transimpedance amp covers dc to gigahertz rangeLukasz Sliwczynski and Przemysaw Krehlik,University of Mining and Metallurgy, Kraków, Poland

To convert the weak, broadbandsignal from a fiber-optic transmis-sion channel into electrical form, you

can use a high-impedance receiver or atransimpedance amplifier. Either meth-od provides the desired gain and band-width but removes any dc and low-fre-quency components of the signal,because both methods require ac cou-pling. In a situation in which you need toalso amplify the dc component, neithermethod is satisfactory. The feedforwardcompensation scheme in Figure 1 solvesthe problem. The circuit exploits an ERA

5 monolithic-microwave IC (MMIC)from Mini-Circuits (Brooklyn, NY,www.minicircuits.com) as the RF ampli-fier. It’s easier to use such an off-the-shelfpart than to configure your own giga-hertz-region amplifier.

You can consider the approach in Fig-ure 1 as a sort of transimpedance ampli-fier with addition of a feedforward com-pensation path. The circuit processessignals from 0 Hz to the high-frequencycutoff of the MMIC (approximately 4GHz for the ERA 5). Current from the re-verse-biased photodiode, D

P, an InGaAs

C 30617BQC PIN diode from EG&GCanada (www.egginc.com), enters theMMIC at 50V input impedance, virtu-ally a short circuit for the photodiode.The MMIC converts the current to a volt-age, which appears on the load resistor,R

L. The MMIC exhibits an output-offset

voltage of approximately 5V, referred tothe MMIC’s common pin. IC

2closes a

feedback path around the MMIC, thusremoving any offset voltage between theMMIC and circuit ground.You could saythat IC

2substitutes for an output capac-

itor.


ideasdesign

Exchanging the feedbackcircuit for an output ca-pacitor provides a sum-ming point, convenientfor introducing the compen-sating signal. This signal com-prises the current flowing intothe second photodiode termi-nal (normally used only forpolarization) and the transim-pedance amplifier made up ofamplifier IC

1and resistor R

F.

The signal routes next throughR

Bto the summing point at the

inverting input of amplifierIC

2. Because the voltage at the

summing point must be con-stant, any dc current from thephotodiode must influence theMMIC’s output voltage, tocompensate the voltage at theoutput of amplifier IC

1. R

Cand

CC

cancel the pole resulting from the de-coupling filter, R

4-C

4, thus guaranteeing

stability.Assuming that R

Aequals R

B, R

A9equals

RB9 and the condition RFtZ

TO/2 is ful-

filled, the transimpedance gain of the en-tire circuit is ktS(S

PZ

TO)/2, where Z

TOis

the transimpedance of the MMIC and SP

is the photodiode responsivity (typically0.85A/W at 1310 nm). You can obtainZ

TOfrom the scattering parameters of the

MMIC: ZTO

Q2s21

ZO, where Z

Ois the ter-

mination resistance for the scatteringmatrix, usually 50V. Z

TOfor the ERA 5

MMIC is approximately 1 kV. If youdon’t fulfil the foregoing conditions, the

frequency characteristics ofthe circuit will not be flat inthe low-frequency region.

Because you don’t know theexact value of Z

TO, you should

trim RF

for the MMIC you use.You can perform the trim us-ing either a low-frequencyspectrum analyzer or a pulsegenerator with an oscillo-scope. With perfect compen-sation, the frequency responseof the amplifier should be flatand should display no over-shoot or undershoot. To getthe best results, you must takecare in designing the pc-boardlayout because of the circuit’shigh bandwidth. Especially,decouple the MMIC’s com-mon point using componentsas small as possible to reduce

parasitic inductance. You should accu-rately match resistors R

A-R

A9 and R

B-R

B9

to minimize offset voltages. (DI #2386).

Feedforward compensation allows you to preserve the dc and low-fre-quency components of fiber-optic transmissions.

+

2

DP

CPRF

RB1k

R41k

R'B1k

R'A1k

RA1k

RL50

ID

2

IC1LM358

+

ERA 5MMICCOMMON100 pF

1 nF

47 nF

C410 mF

R2

C6220 nF

R647k

47 nF200

12V

212V

OUTPUT

LM358IC2BD140

15047 nF

47 nF 3.3V

470 100

1k

Simple scheme detects shortsLuis Miguel Brugarolas, SIRE, Madrid, Spain

When you manually assemblecomplex boards, it’s commonto short-circuit adjacent com-

ponent or IC pins. Determiningwhich section of the circuit you haveshorted is not too difficult, but find-ing the precise point wherethe short exists can be aformidable task, because the shortmay be under a surface-mount com-ponent. The circuit in Figure 1 easesthe diagnosis. It uses off-the-shelfcomponents, and you can build it ina few minutes. The circuit uses aDMM set at its maximum voltage-sensitivity scale (typically, 200 mV full-scale with 0.1-mV resolution). TheDMM measures the voltage drop in thedivider comprising the 5V resistor and

the cable and short-circuit resistance.For the power source, you can use a

laboratory supply or a battery cell. Thelow power-source voltage guarantees thatno circuit damage can occur, even if you

probe the wrong circuit points. Fora 1V source, the circuit’s transferfunction is 0.5 mV/mV—enoughsensitivity for any practical situation.The accuracy of the DMM is not im-portant, but resolution is. Thescheme is simple to use: With the cir-cuit under test unpowered, connectthe probes in any area of suspectedshorted nets. Move one probe in adirection to minimize the voltagereading. Then, move the other probeto find the point that produces anabsolute minimum reading. The

short circuit is most likely between thepoints the two probes touch. (DI #2385)

POWERSUPPLY

ORBATTERY

10

10SHORT

PROBES

DMM

A do-it-yourself short-circuit detector makes it easy tofind solder bridges in pc board using surface-mountcomponents.

F igure 1



F igure 1




Name

Title

Phone

E-mail Fax

Company

Address

Country ZIP

Design Idea Title





Signed

Date


Design Idea Entry BlankEntry blank must accompany all entries. $100 Cash Award for all published Design Ideas. An additional $100 Cash Award forthe winning design of each issue, determined by vote of readers. Additional $1500 Cash Award for annual Grand Prize Design,selected among biweekly winners by vote of editors.

ideasdesign


The synchronous oscillator (SO)and the coherent phase-locked syn-chronous oscillator (CPSO) are uni-

versal multifunctional networks thattrack, synchronize, and amplify as muchas 80 dB; improve SNR by as much as 70dB; and modulate AM, FM, and FSK sig-nals. You can also use these networks asADCs, sampling networks, and dividersthat divide by rational integer numbers,such as 3/4, 5/7, and 7/8. Suitable appli-cations include wideband spread-spec-trum communications and binary-phase-shift-keying (BPSK) andquadrature-phase-shift-keying(QPSK) generation. A CPSO retains allthe properties of the SO and provideszero phase error.

One SO application area is the conver-sion of audio and video to FM in a sin-gle process. Figure 1a shows a simple,one-stage SO oscillating at 94 MHz. Thisfrequency is a good choice for testing theaudio-to-FM conversion on an FMbroadcast receiver. The audio or video in-put to this SO should not exceed S5dBm; any signal above this level may in-duce amplitude modulation. C

4’s decou-

pling capacitor passes the audio or videoto the SO and eliminates dc bias at the in-

put. R1

biases the SO. Because the oscil-lator’s load is a combination of resistance,inductance, and capacitance, the load lineis a combination of a straight line and anellipse (Figure 1b). The linear load lineindicates the dc bias, and you must locatethe load line away from the nonlinearcharacteristics of the transistor.

C3

and the connection between pointsA and B each provide positive feedback.High positive feedback is essential to the

optimum operation of the SO. The val-ue of C

3should range from 2000 to 5000

pF. RF

in parallel with C5

has numerousfunctions. The presence of this networkallows positive feedback within the SO,but looking from the input, R

Fand C

5

also provide negative feedback. This neg-ative feedback adds frequency stability.Finally, R

Fand C

5divert the input audio

or video to the oscillator, not to ground.R

Fand C

5are approximately 15V and 20


ideasdesign

Synchronous oscillator convertsaudio, video to FM ......................................125

High-isolation converters use off-the-shelf magnetics ..............................126

Autoranging circuit simplifies hardware and software..............................128

Simple technique speeds Microstrip breadboarding..........................130

Comparator has independent trip voltages ..................................................132

Modem-access adapter reduces interference....................................134


1k

C520 pF

RF15

0.5 mF

C4

R1180k

AUDIOINPUT

Q12N5031

C2

L1

5V

L20.1 mH

OSCILLATOR

1.2k

OUTPUT

BUFFER

100 pFQ2

A

C

B

SD201

C1C32000 pF

AC LOAD LINE

DC LOAD LINE

IB

IC

V=5V

(a)

(b)

1 TO10 pF100 pF

b>150

F igure 1

A single-stage synchronous oscillator converts audio or video to FM (a). The load line is a combi-nation of a straight line and an ellipse (b).

Synchronous oscillator converts audio, video to FMVasil Uzunoglu, Synchtrack, Gaithersburg, MD


ideasdesign

High-isolation converters useoff-the-shelf magneticsMitchell Lee, Linear Technology Corp, Milpitas, CA

pF, respectively, and these values dependon the b of the transistor. L

2is an RF

choke that diverts the collector feedbackto the base of the transistor. You shouldtune the tank circuit, which comprises L

1,

C1, and C

2, to approximately 95 MHz to

be within the FM broadcast band. A2N5031 for Q

1works well for this appli-

cation because it has high gain and lownoise; any other transistor with the samecharacteristics is suitable. A 2- or 3-in.long wire attaches to the output and actsas an antenna.

The conversion from audio or video toFM takes place in the internal base-emit-ter junction capacitor by its parametric

action, and the changes of the junctioncapacitor due to audio-to-video varia-tions modulates the oscillations to pro-vide an audio- or video-to-FM conver-sion.

The SO also has high input-signal sen-sitivity and high noise rejection. It candetect signals as low as S100 dBm andsignals with SNRs as low as S40 dB. Fora PLL, these performance numbers areS25 dBm and 3 dB, respectively. The SOis frequency-stable and has low phase jit-ter because the tank circuit has a high Qthat can reach 33106. The SO has threeindependent internal filters. With a 200-Hz noise-rejection filter, the SO exhibits

a data bandwidth or tracking range ofseveral megahertz. For input signals withhigh noise, a two-transistor cascoded SOis preferable.

The output buffer, Q2, provides pro-

tection between the oscillator and theoutput world. However, if you want tosimplify the circuit, you can remove Q

2

and its 1.2-kV pullup resistor and con-nect the 100-pF capacitor at the outputdirectly to Point C. (DI #2379)

Isolated flyback converters usual-ly evoke thoughts—or bitter memo-ries—of custom transformers, slipped

delivery schedules, and agency-approvalproblems. Off-the-shelf flyback trans-

formers carry isolation ratings of only300 to 500V and rarely of as much as 1kV. Gate-drive transformers are readilyavailable from stock with high isolationratings and low cost, but they are wound

on ungapped cores, have high inductance(500 mH to 2 mH), and quickly saturatein a normal flyback-converter circuit.Thus, high isolation calls for an abnor-mal flyback converter (Figure 1).

Based on the uncoupled SEPIC (sin-gle-ended primary-inductance-convert-er) topology, the converter operates froma 12V battery-backed input supply andoutputs 24V at 200 mA. The key featureis the second “coil,”which is not a coil butrather an off-the-shelf gate-drive trans-former, T

1. This component offers 3750V

rms isolation and full VDE approval; itfunctions flawlessly in SEPIC service. Theoutput is completely isolated from theinput.

The converter derives feedback fromthe primary winding through D

1. The

transformer winding is 1-to-1. C1

peakdetects a voltage roughly equal to theoutput. A minimum load of 3.6 kV pre-vents the output from rising uncontrol-lably at zero load (Figure 1). (DI #2380)

The second “coil” of this unusual flyback converter is not a coil but rather an off-the-shelf gate-drive transformer. This component offers 3750V rms isolation and full VDE approval.



VIN SW

VCGND

LT1172

FB

100 nF

10 nFC11k

18k

200

+100 mF50V

T1

MUR120

3.6k(6.7 mA

MINIMUM LOAD)

24V/200-mAOUTPUT

+

+10 TO 15V

INPUT 100 mF50V

P6KE36AD1

MUR120L1

100 mH

100 mF50V

NOTES: L1=PE53829 (PULSE ENGINEERING, WWW.PULSEENG.COM). T1=PE-63387.

1N4148

F igure 1


ideasdesign

Anatural approach to autorangingis to use an inverting op amp andswitch in one of N feedback

resistors at a time for a gain ofA=2R

F/R

O(Figure 1). However, the in-

verting configuration suffers from lowinput impedance of Z

IN=R

Obecause the

negative input is at virtual ground. Also,another inverter is necessary to providepositive voltage ranges because of posi-tive signals at the input.

An alternative approach is to use anoninverting op amp that has a high in-put impedance and a gain equation ofAt1RR

F/R

O(Figure 2). This circuit aug-

ments the typical 0 to 5V input range ofa mC with ranges of 0 to 1V and 0 to 10V.The circuit in Figure 2 uses a 68HC16mC, but the results generally apply to anymC with an ADC. The unusualarrangement of circuit compo-nents provides three input ranges that useonly a single op amp, two spdt relays, andresistors with standard values. Also, thecircuit simplifies the autoranging soft-ware because after K

2switches, the status

of K1

is irrelevant.With the relays in the positions that

Figure 2 indicates, RF

equals R1, which

in turn equals RO. Thus, the amplifier

gain is 2. Combined with the voltage di-vider of R

4/R

5, the overall circuit gain is

1/2, which is the gain necessary for a 0 to10V input at V

INto provide 0 to 5V at

VAD

.When K

1switches, R

Fbecomes

R2+R

1=2R

O+R

O=3R

Ofor a gain of

1+3RO/R

O=4. Dividing by 4 gives an

overall gain of 1, which is suitable for a 0to 5V range at V

IN. At this point, it be-

comes obvious why the voltage dividersits before the amplifier: With V

INnear

5V, multiplying by 4 would saturate theop amp.

When K2switches, the position of K

1is

irrelevant, and RF

equals R3+R

1=18R

O+

RO=19R

O. Thus, A=1+19R

O/R

O=20.

Now, the overall gain is 20/4=5, or exact-ly the value necessary for a V

INrange of

0 to 1V to produce an output of 0 to 5V.Although the gain calculation works

out exactly with standard 5% resistor val-ues, for greater accuracy, you can switchthe resistors to the nearest 1% values. Or,even better, sort through a batch of 5%resistors and use a good multimeter to

find resistors that are within 1% of nom-inal. (DI #2381)

+

1VIN

RO

RFN

RF1

VAD

F igure 1

VIN

R4100k 3

2

R220k

R3180k

RO10k

R533k

68HC16

K2

R110k

VADAN0

PF1

PF2

2

5V

+

14

115V

K1

1

1LF3578

15VVIN/4

F igure 2

Autoranging circuit simplifies hardware and softwareDana Romero, Phonex, Midvale, UT


A single noninverting op amp, two spdt relays, and standard-value resistors can produce a 0 to 5Voutput from input ranges of 0 to 10V, 0 to 5V, and 0 to 1V.

An obvious autoranging circuit suffers from low input impedance and needs an inverter to producepositive output-voltage ranges.


ideasdesign

Superglue and some thin, shearedpieces of Teflon copper-clad materi-al are all you need to easily produce

Microstrip-type structures for bread-boarding high-frequency analog or RFcircuits. By gluing properly shearedwidths of copper-material to the pc-board material, you can build an RF-cir-cuit prototype in less than one-tenth ofthe time it takes to carve and clean a Mi-crostrip on the top surface of a prototypepc board. Also, this method allows you toeasily move or add Microstrip lines asprototyping progresses.

High-frequency prototyping of analogcircuits demands that you build every-thing on a ground plane to limit the in-ductance in the ground returns. Fur-thermore, RF-circuit design demandsthat all interconnections be 50V trans-mission lines, or 75V transmission linesif you are a TV type. The most commonway to make a 50V transmission line ona pc board is to use a Microstrip struc-ture. A Microstrip transmission line is atrace on the top of the board, and theground return is the backside copper ofthe board. This type of structureis easy to make when you are lay-ing out a board for production, but itpresents formidable problems when youare prototyping. For one thing, it is in-convenient to use the backside of theprototype pc board as the ground plane.For every node that must connect toground, you must drill a via through theboard to reach the ground. Also, makingthe Microstrip line requires that you usea razor or power tool to carve out thetop-side copper. This technique is messyand error-prone, especially if you arebuilding the circuit piece by piece.

The sheared-copper method exhibitsthe necessary 50V-impedance charac-teristics and eliminates the ground-plane-attachment problems for the oth-er components. The key is to get yourhands on a 0.026-in.-thick Teflon pc-board material called RT/duroid 5870(Rogers Corp, www.rogers-corp.com).

This material has a relative dielectric con-stant (e

r) of about 2.33. Using any elec-

trical-engineering text, you can findequations that state that for an e

rof 2.33,

the width-to-height ratio of a Microstripstructure is about 3.3 to 1 for a 50V im-pedance. So, when using 0.026-in.-thickpc-board material, you should shear the

RT/duroid board in approximately0.086-in.-wide strips.

You can attach the strips to the copper-clad prototype board using dabs ofcyanoacrylate, or instant, adhesive alongthe length of the strips to form the Mi-crostrip structure. The RT/duroid mate-rial is soft and makes it easy to place andbend the strips as necessary; it exhibits anexcellent 50V match to around 3 GHz orhigher. Also, you can easily cut the re-sulting Microstrip structure to allow forplacement of series-matching or passive-lumped elements for dc decoupling. Thismethod also makes it easy to place par-allel components and to place compo-nents from the Microstrip line to theground plane; you simply solder from thetop of the Microstrip line to the adjacentground plane without drilling vias.

For measurement purposes, the photoin Figure 1 shows two Microstrip lines ona prototype pc board. You glue the up-per line to the prototype board to forma straight transmission line. The lower

Simple technique speeds Microstrip breadboardingSteve Hageman, Hewlett-Packard Co, Santa Rosa, CA

A return-loss (S11) measurement of the bent Microstrip-line in Figure 1 exhibits an excellentmatch—>215 dB or VSWR<1.4 to 1—to nearly 3 GHz.

Gluing strips ofRT/duroid material on

top of normal FR4 pc-board material makes avery quick Microstrip structure. Make sure thatthe line lies flat and is firmly glued in placeagainst the board to maximize the return lossof the line.

215 dB

RETURNLOSS(5 dB/DIV)

F igure 2

F igure 1


ideasdesign

For an inverting amplifier withhysteresis, resistors R

A, R

B, and R

F

determine the crossover voltages(Figure 1). Unfortunately, using three re-sistors to set the upper and lower tripvoltages creates a dependence betweenthe two trip voltages: It’s impossible to setone voltage without affecting the other.However, you can achieve the same out-put-voltage response with two inde-pendent trip voltages by using a com-parator with an open-collector output,such as the LM393 or LM339. In Figure2, the resistor divider of R

1, R

2, and R

3de-

termines the upper trip voltage, V1. R

4

and R5

determine the lower trip voltage,V

2.When V

INis between 0 and V

1, V

OUTis

high and prohibits any current flowingthrough R

4and R

5, which sets V

2to V

CC

and thus keeps the output of Compara-tor B high. When the output of Com-parator B is high, V

1tV

CC3R

3/(R

1+

R2+R

3). When V

INexceeds V

1, V

OUTgoes

low, to 0.7V, allowing current to flowthrough the resistor divider. V

2then

changes from VCC

to 0.7V+VCC

R5/(R

4+

R5). On this change, the output of Com-

parator B also goes low, bringing V1

to0.73R

3/(R

2+R

3). V

1is now lower than

VIN

, so VOUT

goes low. VOUT

stays low un-til V

INdrops below V

2. When V

INdrops

below V2, V

OUTgoes high again; V

2tV

CC;

and R1, R

2, and R

3set V

1.

You can easily set either trip voltagewithout affecting the other. However, V

1

must be greater than V2or both trip volt-

ages will be equal to V1. A disadvantage

of this circuit is that it requires two com-parators, but comparators usually comein dual packages. (DI #2383)

Comparator has independent trip voltagesGregory Billiard, Fike Corp, Blue Springs, MO

line, which easily bends around corners,is bent 90-. Measurements of the bentline show that the return loss of the lineexceeds 15 dB to almost 3 GHz and thatthe straight Microstrip line has a betterthan 20-dB return loss all the way to 3GHz (Figure 2).

Alternative methods of breadboardingyield poorer results. The use of common

wire-wrap wire placed above a groundplane yields an impedance of about 100Vand is usable only to the 100-MHz regionfor short lengths. The use of miniaturecoax is not only time consuming, but theshield pigtails at the ends of the coax,which are necessary to access the centerconductor, add enough inductance tocause power holes of 5 to 10 dB in the

range of 100 MHz to 3 GHz. Also, bothof these methods preclude the easy at-tachment of components anywherealong the transmission line. (DI #2382)

RB

RA RL

1

+

VCC

1

LM393NE

RF

VIN8

4

VOUT

VOUT

3

2

(a)

(b) VIN

V2 V1

0

F igure 1

A+

1

B+

1

VOUT

4

RL

7

VCCVCC

8R4

R5

3

2

V2

VIN6

5

R2

R1

R3

VCC

VCC

1

F igure 2

Three resistors determine the trip voltages of an inverting comparator(a) with hysteresis (b), but the trip voltages are not independent.

Using a dual comparator with open-collector outputs allows you to seteither trip voltage without affecting the other.




ideasdesign

The modem-access adapter (MAA)in Figure 1 has features that reduceproblems when modems and phones

share the same line. The design also over-comes the shortcomings of modem in-terference protectors. The design elimi-

nates mutual interference betweenphones and modems, is compatible withthe line-usage indicators on multiline

Modem-access adapter reduces interferenceThomas Schmidt, Schmidt Consulting, Milford, NH

A low-cost mC with flash memory controls the connection of phone lines L1 and L2 to the modem (a). Electromechanical relays switch the phone lineswhile providing an isolated data path (b).

OSC1

RA3

S1

VCC

VCC

VCC

S2

VCC

VCC

VCC

RA2

RA0

RB7

RB6

RB2

RB1

RB0

MCLR

1A

2A

S

1Y

2Y

CLMP

1A

2A

S

1Y

2Y

CLMP

L2_CNTL

L1_CNTL

MODEM_CNTL

L1_OH

L2_OH

HUNT_SW

L2>L1_SW

MODEM_OH

2

1

17

3

12

8

7

6

RESET 4

14

GND5

16

10k10k

10k

VCC

VCC

VCC

VCC

10k

4.7k

SN75447

SN75447

2

7

1

3

6

5

3

5

2

7

1

470

L2L1

VCC

470

PHONEL2L1

MODEM

VCC

470

VCC

470

L1_CNTL

L2_CNTL

L1_ON_HOOK

L2_ON_HOOK

M_ON_HOOK

L1_ON_HOOK

L2_ON_HOOK

M_ON_HOOK

M_CNTL

M_CNTL

L1_CNTL

L2_CNTL

100 pF

PIC16F84IC1

2

3

4

5

L2 TIP

L1 RING

L1 TIP

L2 RING

RJ14

P1

R1, 1M

R2, 1M

R3, 1M

R4, 1M

TO TELEPHONE

LINE

1113

4

9

68

11

9

6

8

119

68

1

13

4

1

16

1613

4

1

16

+

+IN OUT

COMMON

320.1 mFTL780-05

100 mF25V

100 mF25V

1 3

2

100

5

1

2

5

1

2

5

1

2

643

643

643

2345

K4

K1

K2 K3

J1

K5

K6

PH L2 TIP

PH L1 RINGPH L1 TIP

PH L2 RING

TOPHONES

34

J2

TOMODEM

MODEM RING

MODEM TIP

GREENGREEN

RED

RED

BLACKBLACK

YELLOWYELLOW

GREEN

RED

10V POWER

GND

RJ14

RJ14

(a)

(b)

MODEM MODE HUNT ORDERHUNT

NO HUNT

OFF

L1>L2

L2>L1F igure 1


ideasdesign

phones, can search for an idle phone linein multiline installations, draws mini-mum power, and requires no changes toa PC modem’s hardware or software.

Most residential PC users connect tothe Internet using a dial-up modem. Inmost cases, the modem and voice callsmust share one phone line. This sharingpresents a problem because you can’t usethe modem and the phone at the sametime; picking up an extension discon-nects the modem. Many sites have morethan one phone line. A computer has abetter chance of connecting to a phoneline if it can search multiple lines to findone that is idle.

Vendors of modem interference pro-tectors claim the devices eliminate inter-ference between extension phones andcomputer modems. The devices functionby monitoring the voltage between thephone line’s tip and ring leads. When allphones are on their hooks, this voltageis typically >48V. Picking up a phonecloses the tip-and-ring circuit, whichdrops the voltage to approximately 7V.The protector monitors the line voltage.When the voltage drops below a certainthreshold, the protector disconnects thephones that are connected to it. This ac-tion prevents an active phone from in-terference when you pick up an exten-sion.

Unfortunately, these protectors havetwo serious shortcomings. First, the de-vice needs to be in series with the phonesand modems it is protecting, which re-quires one device per phone. When youuse the device in this manner, you can-not use more than one extension at atime. This situation prevents you fromplacing a call on hold and picking it upon another extension. Second, you cansplit the wiring into two circuits: one forphones and one for the modem. Thissplit wiring minimizes the number ofprotectors you need and allows multipleextensions to pick up the same call. Un-fortunately, regardless of how you wirethe protectors, the voltage drop across theprotector confuses the line-busy indica-tors on most multiline phones. Multiline

phones no longer indicate when a line isin use.

The MAA in Figure 1 does not sufferfrom these problems. You must connectthe MAA in series between the tele-phone-company central office and thephones and modem the adapter is pro-tecting. The most convenient location forthe MAA is in proximity to the phone-company network’s interface demarca-tion point. Simply disconnect the insidephone wiring from the demarcationpoint and plug this wiring into the MAA.Then run a dedicated phone line betweenthe MAA and computer modem.

The MAA consists of control (Figure1a) and data-path (Figure 1b) subsys-tems. Phone lines source high voltagesand are balanced with respect to ground.The design uses electromechanical relaysto switch the phone lines while provid-ing an isolated control path.

The heart of the control circuit is IC1,

a PIC16F84 (Microchip Technology,www.microchip.com) low-cost RISC mCwith flash memory. Flash memory makesthis part ideal for development. TheMAA program is approximately 100words long. The accompanying sourcecode is available for downloading fromEDN’s Web site, www.ednmag.com.Click on “Search Databases”and then en-ter the Software Center to download thefile for Design Idea #2389.

When the modem is idle, relay K3

sup-plies power to the modem local loop(Figure 1b). When the modem goes “offhook” to place a call, relay K

6senses cur-

rent flow and wakes the CPU. The CPUreads the state of the hunt-order switch,S

2, which is a physical switch that allows

the user to select the phone-line searchorder.

Relay K4

monitors Line 1 (L1), and K5

monitors Line 2 (L2). When a phone isoff hook, loop current causes the appro-priate line-sense relay contact to close.The CPU uses this information to deter-mine if the line is in use. Assuming thehunt-order switch is in the search-L1-be-fore-L2 position, the CPU reads the stateof L1. If L1 is idle, the CPU energizes K

1

using the L1_CNTL signal. Energizing K1

disconnects the extension phones fromL1 and routes L1 to the normally opencontacts on K

3. Then the CPU energizes

K3, which connects the modem to L1.If L1 is busy, the CPU reads the mo-

dem-mode switch. If the setting of S1

en-ables the hunt mode, the CPU checks theother line for availability. If L2 is idle, theCPU energizes K

2using the L2_CNTL

signal. Energizing K2

disconnects the ex-tension phones from L2 and routes L2 tothe contacts on K

3. The CPU then ener-

gizes K3

to connect the modem to L2. Ifboth lines are busy, the modem nevergets a dial tone and eventually discon-nects.

The telephone central office typicallydisconnects the phone line for a shorttime at the beginning of the dial tone. Af-ter the circuit establishes the connection,the CPU enters a long delay loop. Duringthis time, the CPU ignores changes in thestate of the line. At the end of the delay,the CPU checks to see if the line is in theexpected condition. If it is, the CPU goesback to sleep. If it is not, the CPUprocesses the new state.

When the modem hangs up, relay K6

deenergizes, which also wakes the CPU.When the CPU detects hang-up, it tearsdown the modem connection and re-turns the lines to their default state forvoice.

The bleeder resistors R1

through R4

discharge the phone capacitance and im-press the line voltage on all of the exten-sion phones to ensure that the telephone-busy indicators function normally. RelaysK

4through K

6(Teltone, www.teltone.

com) are specially designed to monitortelephone loop current.

The MAA device connects directly tothe phone line and therefore must meetFCC CFR 47 Part 68 for protection of thepublic switched telephone network. Res-idential devices must meet FCC CFR 47Part 15 Class B for limitation on unin-tended radiation. (DI #2389)





Name

Title

Phone

E-mail Fax

Company

Address

Country ZIP

Design Idea Title





Signed

Date



ideasdesign


Circle 10 or visit www.ednmag.com/InfoAccess Circle 11 or visit www.ednmag.com/InfoAccess

Direct-digital-synthesis (DDS)devices find wide use in in-strumentation and commu-

nications applications. Rather than usinga baseband converter to modulate data ina communications system, you can use aDDS device. Such a device has onboardphase registers that accommodate phase-shift keying (PSK). In communicationsapplications, the phase shifting is in stepsof 458 (p/4 differential-quadrature PSK)or 908 (quadrature PSK). The device hasenough resolution to generate thesephase shifts. In instrumentation applica-tions, the required phase shifts vary, de-pending on the system under develop-ment. Some applications require ex-tremely accurate phase shifts. The phaseregisters in a DDS device are typically 12bits wide, resulting in a phase resolutionof 3608/4096, or 0.0888. However, by us-ing the frequency register as in Figure 1to perform the phase-shifting, you canincrease the phase-shifting resolution to32 bits.

If the DDS device has two frequencyregisters, you can use one to generate theoutput signal and the other to generatethe phase shifts. By using the frequencyregister to perform phase-shifting, the

phase-shifting resolution becomes 3608/2N, where N is the resolution of the fre-quency register. Many DSS devices have32-bit-wide frequency registers. You cantherefore phase-shift the output signalwith a resolution of (83.8231029)8. Forexample, if register FREQ0 contains theoutput-frequency value, then you can setFREQ1 to FREQ0+Q, thus phase-shift-ing the output signal by Q. Under normalconditions, FREQ0 supplies the phase ac-cumulator of the DDS device. Duringphase-shifting, you select FREQ1 for oneMCLK cycle, resulting in phase shiftingthe output signal by Q.

You can phase-shift the output signalby 0 to 3608. However, the frequency reg-isters should not contain a value equal toor greater than 1808. Thus, to performphase shifts greater than 1808, you mustuse the phase register along with the fre-quency register. You can set the phaseregister to 1808 while using the frequen-cy register to obtain the fine phase-shiftresolution. The phase register andFREQ1 register serve as coarse and finetuners, respectively. You use both regis-ters in unison to perform the phase shift.For example, for Q phase shift in the out-

put signal, PHASE+FREQ1tQ+FREQ0.You set PHASE to 1808 and FREQ1 to Q+FREQ021808.

A DDS device has associated pipelinedelays. When you select a frequency orphase register, a pipeline delay exists be-fore you see a change at the DAC’s out-put. In some devices, the latency from thephase register to the DAC’s output is dif-ferent from the latency from the fre-quency register to the DAC’s output.With such devices, an intermediate phaseshift occurs because the phase shift fromeither the FREQ1 or PHASE register oc-curs before the phase shift from the oth-er register. In other DDS devices, such asthe AD9830 and AD9831, the latencyfrom the frequency and phase registers tothe DAC’s output is the same. Therefore,no intermediate phase shift occurs. Theplot in Figure 2 shows the performanceof the circuit in Figure 1, using theAD9830/9831 DDS device.

The master clock to the DDS deviceruns at 5 MHz. The device generates a312.5-kHz output signal. The phase shiftof the output signal is 2708 at points b,d, and f in the plot. Because the PHASEregister in the DDS device comes after

www.ednmag.com August 5, 1999 | edn 117

ideasdesign

Scheme extends DDS phase-shift resolution ..................................117

Single mC pin makes half-duplex RS-232C....................................118

Binary counter uses LSB feedforward ..................................................120

Simple logic reduces EMI ..........................122

Emergency strobe flasher generates 250V ............................................126

3.3V lithium-cell supply requires one inductor..................................128


Scheme extends DDS phase-shift resolutionMary McCarthy, Analog Devices Inc, Limerick, Ireland

By using both the phase and frequency registers in a DDS device, you can increase the phase-shift-ing resolution from 12 to 32 bits.

MULTIPLEXER

FREQ0 REGISTER

FREQ1 REGISTER

FSELECT

MCLKFINE TUNER

(83.8231019)8RESOLUTION

INTERFACE

PHASE REGISTER

32-BITPHASE

ACCUMULATOR

COARSE TUNER0.0888

RESOLUTION

S ROM 10-BIT DAC

AD9830AD9831

12OUTPUT

F igure 1

118 edn | August 5, 1999 www.ednmag.com

ideasdesign

the numerically controlled oscillator(NCO), you must keep this register se-lected until the next phase shifttakes place. The FREQ1 registercomes before the NCO, so you need to se-lect it for only one MCLK signal. TheAD9830/9831 has four phase registers, soyou can use two of them to perform thephase-shifting. For the plot in Figure 2,PHASE0 and PHASE1 are the selectedregisters. At Point b, the output phaseshift is 2708 PHASE0’s setting is 2048—1808, whereas FREQ1’s setting is 1.5625MHz (equivalent to 312.5 kHzR908). Se-lection of FREQ1 and PHASE0 occurs atPoint a, with FREQ1’s selection lastingone MCLK cycle, and PHASE0’s selectiona continuous one.

At b, the phase and frequency valueshave propagated through the DDS de-vice, causing an output phase shift of180R90t270-. At c, FREQ1’s selectionlasts one MCLK cycle, and PHASE1 be-comes selected, with a value of zero.PHASE1 causes an output phase shift of

S1808 (PHASE1SPHASE0t021808).At d, the output signal’s phase shift isS180R90tS90tR270-. At e, FREQ1becomes selected for one MCLK cyclewhile PHASE0 is again selected. This se-

lection produces an output (f) phase shiftof 180+90t2708. (DI #2387).


Points b and c show the output waveform shifting in phase by 270-.

F igure 2

In many mC designs, nearly all the I/Opins are occupied. If only one I/O pinis available, the circuit in Figure 1 can

help you implement a serial RS-232C interface. For many purpos-es, half-duplex operation using a soft-ware-driven RS-232C interface providesa good communications link. Many mCshave open-drain I/O pins, as shown onthe left of the figure. In the idle state, theRS-232C lines Rx and Tx both assume anegative voltage; their TTL counterpartsassume a high level. The I/O pin is alsoat a high level, and neither D

1nor Q

1con-

duct. If a mark signal on the Rx line pullsthe Rx line high, D

1conducts, the I/O pin

goes low, and the mC reads this low lev-el. Because the base of Q

1is negative with

respect to its emitter, Q1

does not con-duct and Tx does not retransmit themark level. If the mC wants to transmit amark, it pulls the I/O pin low (by settingpower to low).

Single mC pin makes half-duplex RS-232CBy Marin Ossman, University of Applied Sciences, Aachen, Germany

An unused I/O pin in a mC provides a convenient way to implement an RS-232C communicationslink.

MAX232

Tx

Rx

Q12N2222

R310k

D1BAT41

R210k

VCC

VCC

I/O PIN

PRD

PWR

mC

R1100k

F igure 1


ideasdesign

Atypical synchronous binarycounter contains a series of flip-flops, each of which changes state

when all least significant bits (LSBs) arelogic 1. This repeated AND function isthe Achilles’ heel of the binary counter.A designer has two choices: Use a rippleAND function (Figure 1), or a parallelAND function (Figure 2). The rippleAND function is slow, but the parallelAND function is hugely wasteful of gatesand places a large fan-out burden on theLSBs of the counter. Note that, in typicalCMOS gate-array technology, AND gates

with more than four inputs are made upof combinations of gates. The configura-tion in Figure 3 combines the best fea-tures of both approaches.

The key to combining the two meth-ods is to recognize that an AND function,not including the LSB of the counter, hastwo whole clock cycles to complete andthen simply bring in the LSB in parallelwith a further two-input AND gate. Theapproach in Figure 3 is generally benefi-cial when the counter is wider than 6 bits.This application is for a 32-bit errorcounter using 2-mm CMOS or a 140-

Mbps plesiochronous-digital-hierarchytest set. You can extend the technique (tomore than 15 bits or so) to propagate theLSBs in parallel; this extension wouldgive the ripple path four clock cycles tosettle. The downside of this method isthat next-state errors would occur if youneeded a resettable counter, though youcan usually design out the requirementfor such a counter at the system level. (DI#2388)

Binary counter uses LSB feedforwardRobert Carter, Siemens PLC, Congleton, Cheshire, UK

The ripple AND architecture is slow but eco-nomical of gates.

The parallel AND configuration is faster thanthe ripple AND technique but is wasteful ofgates.

An LSB-feedforward technique combines thebest features of the ripple- and parallel-ANDmethods.

D Q

T Q

T Q

T Q

T Q

C0

C1

C2

C3

C4

F igure 1

D Q

T Q

T Q

T Q

T Q

C0

C1

C2

C3

C4

F igure 2D Q

T Q

T Q

T Q

C0

C2

T Q C1

C3

C4

F igure 3

Now the emitter of Q1is at ground lev-

el, and the high level on the Rx interfaceoutput supplies base current to Q

1via R

3.

Q1

conducts, and the RS-232C Tx driverinput goes low. The MAX232 drivertransmits a high-level mark signal. In thisway, Q

1and D

1simply provide a route

from Rx to the I/O pin when the circuitreceives characters without echoing

them, and the mC itself also transmitscharacters. R

1is necessary only if no in-

ternal pullup resistor is available.You canuse this type of circuit for service pur-poses in many designs, such as to connecta PC to a pin of a mC. At startup, the mCsends a short message to the PC. Then,the PC sends initialization or debuggingparameters to the mC. During normal

operation, the mC reports its actions tothe PC by transmitting the appropriatedata. If the circuit has a pin with edge-triggered interrupt capability, you caneven implement interrupt-driven I/O.(DI #2397).




ideasdesign

Acurrent-input ADC whose pri-mary use is measuring low-level sig-nals from photodetectors can also

measure a range of voltages using the cir-cuit in Figure 1. The main component isa dual-input current-integratingADC, IC

1. IC

2and IC

3provide the

buffered 4.096V referencefor IC

1. The figure does not

include a mC, which typically over-sees the digital control and data re-trieval.

When you use IC1

with photode-tectors, this ADC integrates the cur-rents at input pins 1 and 28 for auser-controlled integration period,T

INT. IC

1then digitizes the output

voltages of the integrators into 20-

bit digital words that are ready for re-trieval over the serial interface. The onlymodifications necessary to enable IC

1to

measure voltages are resistors in serieswith the inputs. IC

1’s integrators hold the

input at a virtual ground, so the appliedvoltages produce currents through theresistors, which by Ohm’s law equalV

IN/R

INPUT. The full-scale voltage input

for the circuit in Figure 1 is

where IFS

is the full-scale inputcurrent; Q

FSis the full-scale

range of IC1

in coulombs, set bypins RANGE

0to RANGE

2; and

TINT

is the user-controlled inte-gration period. R

INPUT’s value

should be large, preferablygreater than 10 MV. Avoid usingresistors with poor voltage co-

Simple logic reduces EMIEugene Palatnik, BCI International, Waukesha, WI

IN1AGNDCX1BNCX1BPCX1ANCX1APAVDDTESTCONVCLKDCLKDXMITDINDVDD

IN2AGND

CX2BNCX2BPCXA2NCXA2P

VREFAGND

RANGE0RANGE1RANGE2DVALID

DOUTDGND

NOTES: C1 TO C4=250 pF

=ANALOG GROUND.

=DIGITAL GROUND.

IC1DDC112

VIN1-2 VIN2 VIN2-2VIN1

RINPUT1RINPUT1-2 RINPUT2 RINPUT2-2

TO DIGITAL CONTROL TO DIGITAL CONTROL

+

DVDD

DGND

0.1 mF

12345678

91011121314 15

16171819202122232425262728

C1

C2

AGND

AVDD

+10 mF

0.1 mF

C3

C4

OPA340+

1

+

2

30.1 mF

10 mF

6

AVDD

1 mF

7

4

AVDD

4.99k

+

LM4040-4.1

10k

10 mFIC2

IC3

10 mF

R

(a) (b)

RSv(f)=4KTR

Si(f)=4KTR

F igure 1

F igure 2

Series input resistors allow a current-input ADC to measure a wide range of voltages.

The spectral density of the voltage noise, Sv(f), is proportionalto the value of resistance (a), but the spectral density of thecurrent noise, Si(f), is inversely proportional to the value ofresistance (b).

,RT

QRIVin INPUT

INT

FSINPUTFSFS ==

efficients and excess noise. Caddock Elec-tronics Inc (www.caddock.com) offers avariety of high-value resistors with goodperformance.

Eight full-scale ranges areavailable in IC

1. Seven of these ranges are

internal ranges of 50 to 350 pC in stepsof 50 pC. The eighth range uses externalcapacitors C

1to C

4to establish a full-scale

range of approximately 0.963V

REF3C

EXT. For the 250-pF capacitors in

Figure 1, this external range is approxi-mately 866 pC. Surface-mount COG ca-pacitors are a good choice for C

1to C

4.

The CONV Pin of IC1sets the integration

time. In a typical configuration, the min-imum integration period for continuousoperation is 500 msec, and the maximumperiod is 1 sec.

The circuit exhibits a number of use-ful features. First, the dynamic range ofthe circuit is large: IC

1outputs 20-bit

words. Adjusting QFS

and TINT

providesadditional dynamic range. The circuitcan measure voltages that span morethan seven orders of magnitude using afixed value of R

INPUT. Second, the virtual

ground at IC1’s inputs allows you to place

additional resistors in parallel, such asR

INPUT1-2and R

INPUT2-2, to measure the

sum of the applied voltages.And, becauseIC

1is a dual-input ADC, the circuit can

simultaneously make two independentvoltage measurements. Finally, the large-value resistors in series with IC

1’s inputs

allow the circuit to measure large volt-ages. For example, if R

INPUT=100 MV,

then a voltage of 100V produces only a 1-mA current, which IC

1can easily meas-

ure.When using large voltages, make surethat the resistors are rated to handle thevoltages and that the pc-board layoutprovides the proper spacing for insulat-ing the high-voltage lines.

At first glance, you might think thatthe large resistors in series with IC

1’s in-

puts contribute a lot of thermal noise.Fortunately, the noise that these resistorsproduce is usually low and decreases asthe resistor values increase. To see whythis surprising behavior occurs, consid-er two identical noise models of a resis-tor (Figure 2). The model in Figure 2ais probably more familiar and shows the

resistor modeled as a voltage source in se-ries with a noiseless resistor. The spectraldensity of the voltage noise, S

v(f), is pro-

portional to the value of resistance. TheThevenin-equivalent model in Figure 2bcomprises a current source in parallelwith a noiseless resistor. In this case, thespectral density of the current noise,S

i(f), is inversely proportional to the val-

ue of resistance. The bigger the resist-ance, the smaller the current noise. IC

1

measures current. The current-noisecontribution of the resistor is important,so bigger resistors reduce the noise. Also,the thermal noise power is independentof resistance. (For a detailed explanationof the physics behind thermal and othernoise phenomenon, see Reference 1.)

You can use the following expressionto calculate the rms thermal noise, whereV

FSis the integrator’s full-scale voltage,

not the input signal’s full-scale voltage,V

inFS, in the previous equation:

You must add this thermal noise toIC

1’s inherent noise to calculate the total

rms noise. Figure 3 shows noise per-formance versus R

INPUTfor values of T

INT

and QFS

. The figure includes measure-ment points for comparison with the cal-culated noise performance.

IC1’s inputs have very high input im-

pedances and can be susceptible to noisepickup unless you use care in laying outthe circuit. Try to keep R

INPUTas close to

the inputs as possible to minimize thelength of the input traces. Also, shield theinput leads and IC

1with grounds wher-

ever possible. If noise pickup is still aproblem, adjusting the integration peri-od can notch out specific frequencies. Forexample, setting the integration period to16.666 msec places a notch in the fre-quency response at 60 Hz. (DI #2392)

Reference1. Van der Ziel, Aldert, Noise in Solid

State Devices and Circuits, John Wileyand Sons, 1986.


ideasdesign

This plot of noise performance versus RINPUT for different values of TINT and QFS includes both meas-ured and calculated results.

F igure 3


MEASUREDDATA

QFS=50 pCTINT=5000 mSEC

CALCULATEDCURVE

QFS=350 pCTINT=500mSEC

QFS=350 pCTINT=5000

mSEC

QFS=50 pC

TINT=5000mSEC

RINPUT (MV)

NOISE(PPM, RMS)

.Q

TR

KT2

10

V

v10)ppm(NOISE

FS

INT6

FS

6 ==


ideasdesign

Figure 1 shows a complete circuitfor an emergency lamp that operatesfrom a 12V automotive battery. The

xenon flash tube requires a 250V-dc an-ode voltage and a 4-kV trigger pulse. Togenerate the 250V dc, IC

1, a switching

regulator controller, and T1, a standard

Versa-PAC transformer, operate in thediscontinuous-flyback mode. With thisconfiguration, circuit efficiency is typi-cally 75 to 80%. R

1and IC

1’s internal-

sense-threshold voltage limit the peakprimary current to 1.6A. The R

2/R

3di-

vider and IC1’s internal 1.25V reference

at the VFB Pin determine the maximum-voltage setpoint. To generate the 4-kVtrigger pulse, a standard cold-cathode-fluorescent-lamp (CCFL) backlight

transformer, T2, operates in the forward

mode. IC2, a dual MOSFET driver, func-

tions as a 1-Hz oscillator and a one-shotfor the trigger pulse for Q

2. Additionally,

Q3

blanks out the operation of the 250Vsupply during this time. This feature isimportant because the circuit must re-duce the flash tube’s anode current to alow level, allowing the tube to reset andwait for the next cycle. Otherwise, theXenon flash tube may burn out.

The selected flash tube has a maxi-mum flash energy of 4W/sec (joules) anda maximum frequency of 60 flashes/min.Using a 68-mF capacitor for C

1, the avail-

able flash energy, 1/2CV2, is 2 joules, anda flash frequency greater than 1 Hz is pos-sible.

If input voltages below 8V are desir-able—for example, when you use a 6Vlantern battery—it is important to limitthe flash frequency to less than 1 Hz. Thislimit allows sufficient time for C

1to

charge. The peak primary current, con-verter switching frequency, and trans-former primary inductance determinethe charge time: t=(1/2CV2)/(1/2LI2f). Youcan omit Q

4, D

1, and R

4and use V

INto

power IC2. (DI #2393)

Emergency strobe flasher generates 250VRobert Sheehan, Linear Technology Corp, Milpitas, Corp

A complete circuit for an emergency lamp operates from a 12V automotive battery and generates a 250V-dc anode voltage and a 4-kV trigger pulse forthe Xenon flash tube.

NOTES: Q1, Q2=FAIRCHILD NDT410EL. FLASH TUBE=RADIO SHACK 272-1145. FOR T1, CONNECT PINS 3 AND 11, 4 AND 10, 5 AND 9, AND 6 AND 8.

XENON FLASH TUBE

T

K

A

4-kV PULSE

33 nF250V

3M

1M

+C1

68 mF400V

74

92

COILTRONICSCTX110655

1:67

71

12 2

MUR160 250V DC

R22.49M

R312.4k

4.3 mH

COILTRONICSVP3-0138

1:5

T1

R1

11.2 mH

33

220 pF

VIN

100

Q181

234

765

VINS1

BOOSTITHTGVFBSWGND

IC1

LTC1624CSB

470 pF

1 nF

FSW=200 kHz 100 nF 100 nF

2.2 nF

Q32N7002

4-mSEC PULSE

102

7

8

1

2.2 nF

1M

1M 1M

6.8k

6

5

4

3

IC2B IC2A

0.75 TO 1.5 Hz1 mF

LTC1693CS8-2

MMBT3904

+

D17.5V

470 mF25V

1 mF

R410k

Q4

8 TO 16V DC

10

T2

Q2

0.1001/2W

F igure 1



ideasdesign

Because of the growing popular-ity of lithium-ion (Li-ion) batter-ies and 3.3V power supplies,

portable-equipment designers must of-ten create a 3.3V supply that a single Li-ion cell can power. The fact that theoutput of a Li-ion battery ranges aboveand below 3.3V during its discharge cy-cle complicates the design.

This situation calls for a buck/boostconverter, which can perform both step-up and step-down conversions. This re-quirement is not new; for years, portable-equipment designers have faced thesimilar problem of deriving 5V from theoutput of four NiCd cells.

Using a flyback converter is tempting,but the size and expense of a transformerand the extra noise that this convertertype creates prompt the search for an al-ternative. For example, the single-endedprimary-inductance converter (SEPIC)is quieter, but this converter’s buck/boostcircuit has a maximum limited efficien-

cy of 85%. This converter also requires ei-ther a transformer or two inductors inplace of the single inductor that mostdc/dc converters require.

You might overlook an alternative ap-proach because the converter uses a lin-ear regulator and takes an efficiency hitwhen you fully charge the Li-ion batteryto about 4.2V (Figure 1). Nevertheless,this approach offers a longer battery lifethan the other two buck/boost circuits .For a large portion of the Li-ion battery’sdischarge cycle, battery voltage is withina range that allows the converter to ex-hibit excellent efficiency.

The operation of the circuit is straight-forward. When the input voltage is above3.3V, the IC stops switching. A linear reg-ulator comprising Q

1, R

1, R

2, R

3, and an

op amp internal to the IC step down theinput voltage to 3.3V. When the input isbelow 3.3V, the IC operates as a step-upswitching regulator and boosts the out-put to 3.3V. For this condition, the MOS-

FET is fully on, offering a virtual shortfrom drain to source.

Efficiency is a function of the inputvoltage and the output current. As ex-pected, the efficiency is a minimum ofapproximately 78.5% for a peak batteryvoltage of 4.2V. However, with a 3.6V in-put and an output current of less than500 mA, the efficiency is above 89%. Thisbehavior is significant because the out-put of a Li-ion cell is nearly 3.6V for mostof its discharge cycle. For inputs of 3.3 to3.6V and the same output-current con-ditions, the efficiency is even higher. Ef-ficiency is also in the same range whenthe IC operates as a step-up switchingconverter, which it does for battery volt-ages below 3.3V. The efficiency gradual-ly decreases as the output current exceeds500 mA.(DI #2390)

3.3V lithium-cell supply requires one inductorMatt Schindler and Jay Scolio, Maxim Integrated Products, Sunnyvale, CA

MAX1701

LBN AIN

AO

GND PGND

REF

ONA

FB

OUT

LBP

CLK/SEL

ONB

POUT

LX

100k1%

174k1%

0.22 mF

INPUT2.7 TO

5.5V

MBRS130

10 mHCDR74B-100

+

100k1%R2

165k1%R1

0.22 mF

0.22 mF

47 mF16V

3.3V AT800 mA

Q1NDC632P

20k5%R3

105%

220 mF10V

+

10 mF, 6.3V (CERAMIC)

3.3VON/OFF

F igure 1

This buck/boost circuit assumes the buck, or linear-regulator, mode for inputs above 3.3V and the boost, or switching-regulator, mode for inputsbelow 3.3V.





Name

Title

Phone

E-mail Fax

Company

Address

Country ZIP

Design Idea Title





Signed

Date



ideasdesign


Circle 7 or visit www.ednmag.com/InfoAccess Circle 8 or visit www.ednmag.com/InfoAccess

Many modern systems operatewith multiple power supplies thatmust meet tight tolerances to ac-

commodate high-end mPs and peripher-als. For instance, PCI applications mayuse as many as four supplies: 5V, 3.3V,and 612V. The circuit in Figure 1 canmonitor all these voltages for an under-voltage condition and can also monitorthe three positive voltages for an over-voltage condition. The LTC1536 has abuilt-in ability to monitor the 3.3 and 5V

levels and one adjustable level for under-voltage conditions. The adjustable inputof the IC monitors the 12V supply. TheLTC1536 also acts as the logic input forthe open-drain outputs of the LTC1444quad comparator.

Comparators A, B, and C of theLTC1444, along with resistors R

1through

R6, monitor the 3.3, 5, and 12V positive

supplies, respectively, for an overvoltagecondition. The nominal overvoltage trippoints are 3.61, 5.28, and 12.6V. Com-

parator D, aided by resistors R7

and R8,

monitors the 212V supply for an under-voltage condition. The nominal trippoint for the 212V supply is 10.8V. Theopen-drain outputs of all the compara-tors, tied together, connect to the ad-justable input of the LTC1536. The resis-tor divider comprising R

9and R

10

provides a pull-up function for the open-drain outputs. The divider also sets upthe 12V undervoltage trip point, which isnominally 11.3V. A Schottky diode tied

to the LTC1536’s adjustableinput can provide anotherlogic input, such as a Power-Good signal. If any under-voltage or overvoltage faultconditions occur, the LTC-1536 issues a reset until 200msec after the fault conditiongoes away. (DI #2403).

www.ednmag.com August 19, 1999 | edn 129

ideasdesignEdited by Bill Travis and Anne Watson Swager

_

+D

_

+C

_

+B

_

+A

LTC1444

3

2

1

16

15

4

5

6

7

10

11

12

13

14

8 9

REF1.221V

HYST

1.21M1%

R810.7M

1%

R7

1M1%

R6

1.21M1%

R4

9.31M1%

R5

4.02M1%

R3

1.21M1%

R2

2.37M1%

R1

12V

1.05M1%

R9

102k1%

R10

0.1 mF

PWR GOOD

OPTIONAL

VCC3

VCC5

VCCA

GND RST

RST

SRST

PBR

LTC1536

100kR11

8

7

6

5 SYSTEMRESET

1

2

3

4

5V

3.3V50.3V

112V510%

5V55%

12V55%

F igure 1

Circuit monitors quad supply for PCI systemsRoger Zemke, Linear Technology Corp, Milpitas, CA

Two ICs monitor PCI-system quad supplies for undervoltage and overvoltage fault conditions.


Circuit monitors quad supplyfor PCI systems ............................................129

Circuit controls multiple thermoelectric coolers ............................................................130

Current-input ADC measures voltages ..........................................................132

You’ve got mail ............................................134

Circuit provides brownout control of 80C31 ........................................................136

Circuit emulates mechanical metronome....................................................138

PC controls light dimmer ..........................140


ideasdesign

Optoelectronic and other com-ponents sometimes use a thermo-electric cooler and a thermistor for

temperature control. A typical thermo-electric cooler has 1A maximum currentand 1V impedance. These parametersmake simple series-pass drive circuits in-efficient, given the typical available sup-ply voltages (5, 12, or 15V). Often, sever-al thermoelectric coolers exist in a singlecircuit (for example, a multiple-wave-length optical transmitter). In this case,you can obtain improved efficiency byusing the circuit in Figure 1. This circuithas three devices to cool, so it containsthree coolers and three thermistors. Onthe sensor side, each thermistor connectsto a standard proportional-integral-dif-ferential op-amp or mP-based-controllercircuit. Each controller produces a com-mand voltage that is proportional to thecurrent its respective cooler requires.

The command voltages drive precisionrectifier circuits (op amps IC

1 to IC

3) that

generate the maximum control VMAX

. Op

amp IC4

limits VMAX

, thus allowing youto control the maximum current deliv-ered to the coolers. This limited output,V

LIM, is the input to the main transistor-

driver amplifier, IC8.V

LIMcommands the

main transistor to pass a current corre-sponding to the largest demand, subjectto the limit constraint. The thermoelec-tric coolers connect in series, and thischain receives its current via the main se-ries-pass transistor Q

4. IC

8drives this

transistor such that the voltage dropacross R

SENSEequals V

LIM. You choose

RSENSE

to equal the impedance of onecooler. The coolers have shunt transistors(Q

1through Q

3) that divert any excess

current around the individual coolers.The shunt transistors receive their drivefrom op amps IC

5through IC

7, which are

connected as difference amplifiers. Theop amps drive the shunt transistors suchthat the voltage across each thermoelec-tric cooler equals the command voltagefor that cooler.

Because the sense resistance equals that

of the coolers, the current passingthrough each cooler assumes the correctvalue. The actual values of the difference-amplifier resistors, R, and the transistor-base resistors depend on the type of opamps and transistors you select. In mostcases, the desired cooler currents have anaverage value, I

MEAN, and a maximum val-

ue, IMAX

, that are almost equal. If you coolN coolers using separate circuits, thesupply needs to deliver N3I

MEANA. Using

the series-connected circuit, the supplycurrent reduces to just I

MEAN. Even in the

case in which you an optimize the sup-ply voltage for either circuit, the powerdissipation for the series-connected cir-cuit is lower because it drops a smallerfraction of the supply voltage through theseries-pass transistor. (DI #2395).

Circuit controls multiple thermoelectric coolersBy Frank Effenberger, Bellcore, Morristown, NJ

PIDCONTROLLER

T1

+ +1

1

IC1

IC5

RB

VCC

D1

PIDCONTROLLER

T2

+ 1IC2

D2

PIDCONTROLLER

T3

VREF

+ 1IC3 VMAX

D3

D4 VLIM

+

1IC6

+

1IC7

+

1IC4 +

1IC8

R

R R

R

R

RSENSE

R

R

R R

R

R R

R

R

Q1 TEC1

RBQ2 TEC2

RB

RB

Q3

Q4

TEC3

NOTES:R=10 kV, RB=1 kV, RSENSE=1V.IC1 THROUGH IC8=¼ TL084 QUAD OP AMP.Q1 THROUGH Q4=TIP120 DARLINGTON TRANSISTOR.D1 THROUGH D4=1N914. T1 THROUGH T3=10k AT 208C.TEC1 THROUGH TEC3=1A AT 1V FULL RATING.PID BLOCK IS A GENERIC RESISTANCE- INPUT AND VOLTAGE-OUTPUT ANALOG CONTROL CIRCUIT.

F igure 1

A series connection of thermoelectric coolers provides more efficient temperature control and fewer supply-current requirements than circuits usingindividual cooler controllers.



ideasdesign

Current-input ADC measures voltagesJim Todsen, Burr-Brown Corp, Tuscon, AZ

A practical realization of aspread-spectrum techniquelowers a mP’s clock-related

EMI by approximately 4 dB without thedrawbacks associated with modulation(Figure 1). The spread-spectrum tech-nique is a popular method to reduce mP-clock-related EMI (Reference 1). Usingthis method, the mP’s clock frequencyconstantly shifts around and creates amoving target for quasipeak EMI detec-tion. Although this method dramatical-ly reduces measured EMI, it has a fewdrawbacks.

The first drawback is an unpredictableclock frequency. Peripheral devices thatshare the same clock with the mPand rely on a stable clock fre-quency might suffer. One example is anADC that relies on direct mP control todefine the sampling time. The seconddrawback is the periodic nature of thefrequency shift. The technique essential-ly modulates the clock frequency with anapproximately 50-kHz frequency. Thisfrequency is slightly higher than the au-dio band to prevent audio “hum.” Insome systems, however, this 50-kHzmodulation frequency may be in bandwith data-acquisition or other sensitiveanalog circuitry. Under these circum-stances, separate nonmodulated digital-control and clock signals are necessary toprevent demodulation of 50-kHz fre-quency and to prevent analog noise.

Consider the product of two squaresignals with unity amplitude, x

1(t) and

x2(t), where x

1(t) is a square signal with

frequency v1

and x2(t) is a square signal

with frequency v2in radians (Figure 2a).

The Fourier transforms of square wavesx

1(t) and x

2(t) are:

The Fourier transform of the productof x

1t and x

2t is: You can limit the series to the first term

Simple logic gates implement a spread-spectrum technique that produces predictable clock behav-ior and introduces no unwanted modulation frequencies.

Multiplying x1(t) by x2(t) produces x(t) (a). In the frequency domain, the multiplication causes theoriginal main frequency component, v1, to split into two equal components (b).

x2(t)

x1(t)x(t)

D

CLK Q5

IC1 IC2

IC3A IC3B

CRYSTALOSCILLATOR

F igure 1

+1

21

+1

21

+1

21

x1(t)

x2(t)

x(t)

(a)

(b)

v1

v12v2 v1+v2

F igure 2

and

5

)5sin(3

)3sin()sin(

4)t(x

1

11

1

+ω

+ω+ω

π=

L

.

5

)5sin(3

)3sin()sin(

4)t(x

2

22

2

+ω

+ω+ω

π=

L.

3

)sin()3sin(3

)sin()3sin()sin()sin(

4

)t(x)t(x)t(x

12

2121

21

+ωω

+

+ωω+ωω

π

==

LL,


ideasdesign

for simplification:

If v1

is the frequency of the crystal os-cillator and v

2is the result of the fre-

quency division of v1

by 128, for exam-ple, then you can rewrite the previousequation as follows:

In other words, the frequency peak ofx

1(t) multiplied by x

1(t)/128 splits into

two frequency peaks separated by 23v

1/128. Each peak has half of the energy

of the original v1

peak. Figure 2b showsa Matlab-generated spectrum of x

1(t)

and x(t).Multiplying the nth harmonic of the

original x1(t) signal by x

2t splits the nth

harmonic into two major frequencycomponents with frequencies n3v

1+v

1/

128 and n3v11v

1/128. (These product

terms are the most significant.) If x2(t) is

purely sinusoidal and the frequency an-alyzer has an unlimited narrow frequen-cy bandwidth, the initial x

1(t) nth har-

monic splits into two frequency spikes.Each of these spikes is approximately 6dBmV, or two times, lower than the ini-tial frequency spike. In practice, you canobtain a 4-dBmV reduction. In many cas-es, this reduction is a lifesaver because ithelps the circuit pass an EMI test, partic-ularly when bulky ferrites on each cableturn your portable electronic device intoa boat anchor.

Figure 1’s circuit realizes this tech-nique using a few simple logic gates. Youcan obtain x

2(t) from the mP timer or the

counter by dividing x1(t) by any num-

ber—in this example, 128. Flip-flop IC1

locks x2(t) to the crystal oscillator’s phase.

The XOR gate, IC2, is the key element. Al-

gebraic multiplication of signals x1(t)

and x2(t) in Figure 2a is equivalent to the

XOR function of x1(t) and x

2(t) when

they are “logic” signals. IC3A

and IC3B

compensate for IC1’s propagation delay.

The output of IC2

routes directly to theclock input of the mP. The resulting sig-nal x(t) experiences two phase shifts overone period of x

2(t) (Figure 2a). The first

shift of 180° occurs during x2(t)’s tran-

sient from logic 0 to logic 1; the secondshift of 2180° occurs during the tran-sient from logic 1 to logic 0.

From the mP’s perspective, the clocksignal loses one full period of x

1(t) over

one full period of x2(t). In this example,

if you program the mP’s internal timer to127 cycles, the clock counts 128 cycles ofthe original crystal frequency.

If you use this technique, you can eas-ily predict the mP’s clock behavior. Forexample, sampling with every period ofx

2(t) introduces no noise into the ADC’s

reading. The frequency content of thedigital clock and other digital signalscontains no low frequencies, such as 50kHz, so the digital clock does not causeany noise in the analog sections. (DI#2391)

Reference1. Bolger, Steve, and Samer Omar Dar-

wish, “Use spread-spectrum techniquesto reduce EMI,” EDN, May 21, 1998, pg141.

Many e-mail programs provide a“beep” or a pop-up message boxsignaling the user that a new e-mail

message has arrived. If the you are too farfrom the computer to hear the audiblesignal or if the monitor is turned off, thenyou miss the new-mail audible and visu-al signals. The simple circuit in Figure 1(see pg 136) latches on an LED and an au-dio sounder when an appropriate newaudible e-mail signal occurs. The meth-od replaces the normal e-mail sound.wavfile with a .wav file of any valid recordeddual-tone multifrequency (DTMF)sound. The circuit listens for the DTMF

tone and latches on LED D1

and thepiezoelectric buzzer, P

1. R

1biases the mi-

crophone’s FET, and C1couples the audio

to the M-8870 DTMF-receiver, IC1

(Tel-tone Corp, www.teltone.com). IC

1inte-

grates both bandsplit-filter and decoderfunctions into an 18-pin DIP.

Resistors R2

and R3

configure the on-chip differential amplifier for a gain of 47.The 3.579545-MHz crystal, X

1, provides

a precise clock generator for IC1’s digital-

counting decoding circuitry. R4

and C2

provide an RC guard time to place acceptand reject limits on tone duration. IC

1’s

STD output switches to logic high for the

duration of any valid DTMF tone. TheNAND gate, IC

2A, inverts this logic sig-

nal and then directs it to a latch config-ured with NAND gates IC

2Band IC

2C.

Pushbutton switch S1

resets the latch.IC

2Dbuffers and inverts the latch’s output

and drives a 2N2222 transistor, Q1, there-

by turning on the LED and the piezobuzzer. The circuit latches for any validDTMF tone. You can add additional cir-cuitry to use the M-8870’s 4-bit binaryoutputs, Q

1to Q

4if you need to discrim-

inate between DTMF tones. (DI #2399).

You’ve got mailby Gary Kath and Craig Bishop, Scotch Plains, NJ


.)cos(2

1)cos(

2

14

)sin()sin(4

)t(x

2121

21

ωωωωπ

=ωωπ=

111

.128

cos2

1

128cos

2

14

128sin)sin(

4)t(x

11

11

11

ω+ω

ωω

π

=

ωω

π=

11


In the reset and watchdog-timer cir-cuit in Figure 1, IC

1is a 74HC14

Schmitt-trigger inverter that, with R1

and C1, acts as an astable oscillator. The

circuit provides an active-high reset foran 80C31 mC. The watchdog trigger(WDT) consists of watchdog-triggerpulses from a port line. At power-on, the voltage on C

1is 0V, and re-

sett1. As C1

charges, reset goes low, andthe mC generates watchdog-trigger sig-nals. These ac-coupled pulses periodical-ly turn on Q

1and charge C

1to V

CC. This

action prevents C1

from dischargingthrough R

1when reset is low. If the

watchdog-trigger pulses stop, Q1turns off

and C1

discharges through R1. reset goes

high, resetting the mC. Now, C1

chargesthrough R

1, and reset goes low after the

reset period. D1

prevents charge-pumpaction, and D

2provides a fast discharge

path for C1

when the supply goes down.The Q

2-Q

3combination acts as a low-

voltage reset circuit. When VCC

decreases

to less than approximately 4.5V, Q2

turnsoff and Q

3turns on, discharging C

1; re-

set then goes high. The circuit works withvoltages as low as 1.5V. During power-upand -down, hysteresis of the inverter pro-

vides a clean reset signal. (DI #2400).


ideasdesign

WATCHDOGTRIGGER

16IC1

0.1 mF

10 mF

10k

4.7k 1k

Q1

Q3

VZ

Q2

C1

D2

2N3906

D1

RESET1N4148

100kR1

+100

4.7k

4.7k

1k

4.7k

5V

74HC14

5V

2N2222

2N2222

16IC1

F igure 1

An 80C31 mC receives a clean reset signal from this circuit, which monitors power-up andbrownout conditions on the power supply.

Circuit provides brownout control of 80C31By N Kannan, Mediatronix, Pappanamcode, India

IC1M-8870DTMF

RECEIVER(TELTONE

CORP)

IN+

IN1

GS

VREF

IC

IC

OSC1

OSC2

VSS

VDD

ST/GT

EST

STD

Q4

Q3

Q2

Q1

OE

18

17

16

15

14

13

12

11

10

1

2

3

4

5

6

7

8

9

R3470k

R4330k

R61k

R7220

D1

R51k

R110k

R210k

5V

C10.1 mF

C20.1 mF

IC2A4011

DTMF.WAV

"BEEP"

COMPUTER'SSOUND-CARD

SPEAKER

MICROPHONESHIELD

+

MICROPHONEINPUT

ELECTRET MICROPHONE(PANASONIC, WM-62A)

3.579545 MHzX1

5V

5V

1

2 IC2B4011

3 12 11

14

13

IC2C4011

5IC2D4011

46

7

5

PUSH TORESET

S1

8

910

2N2222

Q1

5V 5V

+P1

PIEZO BUZZER(RADIO SHACK,

273-065)

F igure 1

Tired of missing incoming e-mail? This circuit provides a permanent indication of incoming messages.



ideasdesign

The circuit in Figure 1 producestiming signals with a sound like thatof a mechanical metronome. IC

1 is a

555 timer that oscillates at approximate-ly 3200 Hz. The two 3-kV resistors andthe 0.047-mF capacitor set the frequen-cy. IC

2 divides the frequency of IC

1’s out-

put by 2. IC2 produces a square wave with

an exact 50% duty cycle. The frequencyof the output of IC

2determines the

sound of each beat. A higher frequencyyields a sharper sound, like beating on asmall drum; a lower frequency producesa deeper sound, like beating on a largedrum. You can adjust the sound bychanging the values of the 3-kV resistorsor the 0.047-mF capacitor. The squarewave from IC

2 is always present on Pin 1

of IC5. IC

3is a low-frequency oscillator

that runs from approximately 0.5 to 3 Hz.This oscillator determines the rate orspeed of the beat. The two 100-kV resis-tors, the 1-MV potentiometer/resistorpair, and the 1-mF capacitor determinethe oscillator frequency.

For every rising edge from IC3, the IC

4

one-shot produces one low-to-high-to-low output pulse. The 30-kV resistor andthe 0.15-mF capacitor determine thelength of IC

4’s output pulse. This pulse

is approximately 2 msec long with thevalues shown. The output from IC

4al-

lows three to four pulses from IC2

to passthrough to the output of IC

5. When IC

5’s

Pin 2 is high, the pulses from IC2

appearat IC

5’s Pin 3; when Pin 2 is low, no puls-

es appear at Pin 3. From IC5’s Pin 3, the

series of pulses routes to the volume con-trol and then to the power audio ampli-fier. All the circuitry except IC

6uses a 5V

supply. IC6 needs a 12V supply to drive

the speaker loud enough to hear over thesound of an instrument. If you want a vi-sual indication of the beat, you can con-nect an npn transistor, with a 470V seriesbase resistor, to IC

4’s Pin 6. An LED in se-

ries with a 470V resistor from the collec-tor to 5V produces the visual indication.(DI #2404).

IC1LM555

IC27490

IC57400

IC3LM555 IC4

74121

7812

7805

IC6LM386N-1

5V

5V

0V

0V

1600 Hz

3200 Hz

0.5 TO 3 Hz

0.5 TO 3Hz5V

0V

5V

0V

1600-Hz BURST

5V

0V

0.33 mF

0.33 mF

0.1 mF

250 mF/25V DC

5V

12V

1

23

7

14

14 12

5

2

2

3

3

3

3 4 7

6 7

7

7

10

0.15 mF

0.33 mF

0.33 mF 0.33 mF

1 mF

0.047 mF

0.33 mF

30k

14 10 11

5 6

RATE

1M

1M

100k

100k

2 6 1

1

5V

5V5V

5V

4

4 8

8

6

15V

3 6

4

2

100k

10k5

10

2-IN.SPEAKER

+

VOLUME

12V SOURCE

5V SOURCE

3k

3k

F igure 1

Circuit emulates mechanical metronomeJim Kocsis, Allied Aerospace, South Bend, IN

Sounding just like an old-fashioned metronome, this circuit sets the cadence for your music practice.



ideasdesign

Using the simple circuit in Figure 1,you can control the light intensity inyour room or work area from your

PC. The heart of the circuit is a low-pow-er D/A converter that converts digitalwords from a computer’s parallel port toanalog-voltage signals. To isolate the dclow-voltage part of the circuit from thehigh-voltage part, the circuit uses an op-toisolator, which prevents any direct elec-trical connection between the two sec-tions. The optoisolator triggers triac T

1,

which behaves like a switch. In each pow-er cycle, T

1switches on, the ac supply

voltage connects to the load (lamps), andcurrent starts flowing in the triac. At theend of a half-period, when the currentdrops to zero, T

1turns off and awaits an-

other trigger in the opposite direction.This additional trigger occurs in the sec-

ond half-period of the power cycle. Alower triggering voltage makes T

1con-

duct at an earlier point in and stay on fora larger fraction of the cycle. The largerfraction corresponds with transferringmore power to the lamp, resulting in ahigher intensity.

The output voltage of the D/A con-verter sets the triggering point. The DAC,after one stage of buffering, providesenough current to drive the optoisolator.IC

3generates a 2.5V reference; the crys-

tal oscillator and capacitors C1

throughC

4set the DAC’s timing characteristics.

The DAC1220 (Burr-Brown Corp,www.burr-brown.com) connects to theparallel port with three wires for serialtransfer of the digital codes. The Pascalprogram of Listing 1 (pg 142) reads thePC’s keyboard; when you press Q or W,

the routine increments or decrements adigital code and sends it to the DAC. TheDAC then controls the lamp’s intensity.Upon power-up, the DAC receives a dig-ital code of zero, which corresponds to a2.5V output (the reference voltage). Youthen adjust potentiometer R

3such that

the lamp is half on. Using the keyboard,you can change the light intensity to thedesired level. The dc part of the circuitconsumes only approximately 5 mA.Listing 1 is available for downloadingfrom EDN’s Web site, www.ednmag.com.Click on “Search Databases”and then en-ter the Software Center to download thefile for Design Idea 2401. (DI #2401).

PC controls light dimmerAfshin Mellati, Burr-Brown Corp, Tucson, AZ

14

162 3 4 13 12 9

8 7 6 5

1 2 3 4

10

11

1515

PIN 6

PIN 7

PIN 8

PARALLELPORT

22

+3

7

46

VDD

VDD

VDD

VDD

R41k

R24k

R527k

IC2OPA340

IC4MOC3010

IC3REF1004

D21N4001

C5100 nF400V

C15.6 pF

C25.6 pF

C310 nF

C43.3 nF

IC1DAC1220

R124.9k

T1NTE5629(OR ANY 400V, 4A TRIAC)

D11N4001

R31k POTENTIOMETER

LOAD

ACLINE

CRYSTALECS-V2.5-S

F igure 1

Set your computer area’s lighting intensity from the comfort of your swivel chair, using keyboard commands. A simple Pascal routine and some low-cost components do the trick.



ideasdesign

LISTING 1—PC-CONTROLLED LIGHT DIMMER

Circle 10 or visit www.ednmag.com/infoaccess.asp

Many applications require ananalog output to assume differentamplitudes, but many direct-digi-

tal-synthesis (DDS) devices do not ac-commodate amplitude variations. Testequipment uses DDS devices to generatesignals of different frequencies. Howev-er, the amplitude of these signals oftenmust be variable, too. In communicationsystems, such as base stations, it is essen-tial that the system does not deliver sig-nals until data is ready to trans-mit. Between transmissions, theamplitude of the DDS-device outputmust decrease to near zero. In addition,many applications require AM. SomeDDS devices have onboard amplituderegisters that allow you to vary the mag-nitude of the analog output. However,you can also use DDS devices that do nothave AM registers (Figure 1). Themethod involves varying the onboardDAC’s current.

The onboard DAC for many DDS de-vices is a current-source type. The refer-ence current to the DAC is a function ofthe reference voltage, V

REF, and an exter-

nal resistor, which you normally tie from

the DAC to ground. The reference cur-rent is V

REF/R

SET. The full-scale current

from the DAC is a multiple of the refer-ence current; the multiple is a function ofthe size of the transistors in the DAC. Forexample, the full-scale current of anAD9830 is 163V

REF/R

SET. If you do not

tie RSET

to ground but tie it instead tosome varying voltage, V, the full-scalecurrent is 163(V

REF1V)/R

SET.Varying V

varies the full-scale current and, there-fore, the voltage output from the DDSdevice. You can provide the varying volt-age by using a voltage-output DAC.

In Figure 1, an AD5310 provides avariable voltage to the AD9830. With theDAC output at 0V, the DDS device hasmaximum full-scale current. Increasingthe voltage output from the AD5310 reduces the full-scale current of the AD-

www.ednmag.com September 2, 1999 | edn 133

ideasdesign

DDS device providesamplitude modulation................................133

Charge pump convertsVIN to 5VOUT ................................................134

Electronic SPDT controls two PCs ............136

GMR sensors manage batteries ............138

Driver thermally compensates LED ........140

Program turns PC sound card into a function generator ..........................142

Li-ion battery charger adaptsto different chemistries ..............................146


DDS device provides amplitude modulationMary McCarthy, Analog Devices, Limerick, Ireland

INTERFACE

FREQ0 REGISTER

FREQ1 REGISTERMULTIPLEXER

FOUR PHASE REGISTERS

D0 TO D15 A0 TO A2 WR PSEL0 PSEL1

32-BITPHASE

ACCUMU-LATOR

FSELECT

MCLK

IOUTROM

AD9830

10-BITDAC

FULL-SCALECONTROL

REFINFULL-SCALE

ADJUST

RSET

AD5310

VOUTREF+ REF1

10-BITDAC

OUTPUTBUFFER

POWER-DOWNCONTROL

LOGIC

INPUT CONTROL LOGIC

DACREGISTER

POWER-ONRESET

SYNC SCLK DIN

VDD GND

RESISTORNETWORK

12S

F igure 1

By using a voltage-output DAC, you can obtain amplitude modulation in a DDS device that does notprovide for variable output voltages.

9830. The AD9830 uses a 1-kV RSET

anda nominal V

REFof 1.21V, yielding

a 19.36-mA full-scale current. Fig-ure 2 shows the output spectrum of theDDS device with this full-scale current.The master clock to the DDS device runsat 50 MHz, and the DDS device producesa 1-MHz output signal. The spurious-free dynamic range (SFDR) is typically60 dB. Loading code 223 into the DACgenerates a 1.089V output voltage. Thisvoltage results in 1.936-mA full-scalecurrent (reduced by a factor of 10) fromthe AD9830. With this full-scale currentand the same clock and frequency con-ditions as above, the SFDR remains un-changed.

The AD5310 is a 10-bit DAC with in-tegral nonlinearity of 52 LSB. It is suit-able for use with the AD9830 in testequipment or for amplitude-rampingapplications. If you need high-resolutionamplitude modulation of the DDS de-vice’s output, you need a more accurate

DAC. The AD8300, for example, is a 12-bit DAC with integral nonlinearity of 52LSB, representing a fourfold improve-ment over the AD5310. The increased ac-curacy makes this DAC more suitable forsystems in which you need finer control

over the amplitude variations. BothDACs have a serial interface, so you needonly three connections to talk to theDAC. (DI #2396).

134 edn | September 2, 1999 www.ednmag.com

ideasdesign

F igure 2

The spurious-free dynamic range for the amplitude-modulation system is 60 dB.


Acharge-pump IC’s ability to pro-duce both V

INand 2V

IN

outputs allows the circuit inFigure 1 to generate separate positive andnegative outputs from a single input volt-age, regardless of the input-voltage po-larity. For example, the circuit allows anRS-232C interface to generate a dual sup-ply for low-power data-acquisition sys-tems (if you use TxD as V

IN, and you lim-

it VIN

to the 66V maximum that IC1 can

accommodate). Consider a positive VIN

:The positive V

OUTappears via D

1and

supplies power to the IC via Pin 8. D2and

R1

pull Pin 7 high, which is a condition(along with other connections) for set-ting the chip in its inverter mode. As a re-sult, the circuit produces 2V

OUTat Pin 5.

For a negative VIN

, 2VOUT

appears viaD

3. D

2 and R

1pull Pin 7 to ground, which,

along with the Pin-5-to-Pin-6 connec-tion, is a condition for setting the chip toits doubler mode. Thus, doubling 2V

IN

produces VOUT

at Pin 8. The MAX860 (orMAX861) operates at its minimum fre-

quency of 6 kHz (13 kHz for theMAX861) with Pin 1 unconnected and atits maximum frequency of 130 kHz (250kHz for the MAX861) with Pin 1 con-nected to Pin 5. To reduce the voltagedrops associated with D

1and D

3, you can

replace the two Schottky diodes withMOSFETs. (DI #2402).

Charge pump converts VIN to 6VOUTIoan Ciasci, Rei Data, Cluj-Napoca, Romania

A charge-pump circuit produces simultaneous VOUT and 2VOUT outputs when you drive it witheither polarity of VIN.

FC

C1+

GND

C11

VDD

SHDN

LV

OUT

1

2

3

4

8

7

6

5

IC1MAX860C2

2.2 mF

D11N5818

D21N4148

D31N5818

VIN1

1VOUT1

R122k

C14.7 mF

C34.7 mF

+VOUT1F igure 1



ideasdesign

The circuit in Figure 1 is a switchthat allows you to use one VGA mon-itor, one mouse, and one keyboard

with two PCs. The switch has fourpushbuttons. One switches the mon-itor between the two PCs, a sec-ond switches the mouse, a thirdswitches the keyboard, and a fourthconnects all the devices to the PCthat’s inactive at the moment. The ac-tive portion of the circuit uses aPIC16F84 mC, IC

1, from Microchip

Technology (www.microchip.com)and MAX395 (IC

2, IC

3, and IC

4) and

MAX392 (IC5) electronic switches

from Maxim Integrated Systems(www.maxim.com). The mC is thecore of the system; with a simple pro-gram, it checks the pushbuttons andselects the proper switches to imple-ment the desired connection. You candownload the program from EDN’sWeb site, www.ednmag.com. Click on“Search Databases/Links Page” andthen enter the Software Center todownload the file for Design Idea#2375. The mC also drives three LEDsthat indicate the PC each peripheraldevice connects to.

The circuit derives its power fromthe keyboard connector. If both PCsare initially off, and one switches on,the circuit connects all devices to thatone. R

1detects the switched-on PC

and communicates the switched-onstatus to the RB2 input of IC

1. The

circuit receives its power through D1

and D2. These diodes decrease the 5V

supply by approximately 0.7V. TheMAX682 step-up regulator, IC

6, re-

stores the 5V for the more criticalparts of the circuit. The MAX238, IC

7,

provides TTL-to-RS-232C conversionand vice versa for the serial ports. Theprogram initializes the mC’s registersand connects the devices to one of thecomputers, depending on the level atthe RB2 input. It then executes a loop,which ends when you press a push-button.

The system detects the newlypressed key and changes the corre-sponding bit or bits of a register,

PC_SEL (PC Select) in the mC (Table 1).The routine then changes the signals, ifnecessary, to the MAX392, IC

5, for the

keyboard selection, and issues a group ofbits to configure the MAX395s for themonitor and mouse control. Finally, be-

Electronic SPDT controls two PCsLuis Angulo, Barakaldo, Spain

1

2

3

4

5

KEYBOARD

12

3

4

5

PC1KEYBOARD

1

2

3

4

5

PC0KEYBOARD

IC5MAX392VTT

VCC

V2 V+

NCGND

IN1

COM1NO1

IN2

COM2NC2

IN4COM4

NO4

IN3COM3

NC3

4

12

3

16

1514

5

IC2MAX395

V+ SCLKCS

RESET

DOUT

NO7

COM7

GNDV2

DIN

VCCVTT

VCC

NO0

COM0

NO1

COM1NO2COM2

NO3COM3

NO6

COM6

NO5COM5

NO4COM4

13

1287

6

1011

9

KCLOCK

KCLOCK1

KCLOCK0

KDATA1

KDATA

KDATA

KDATA0

KCLOCK

KDATA1

KCLOCK1

KDATA0

KCLOCK0

+ RED0

RED

RED1

GREEN0

GREEN

GREEN1

DATA

SCLK

REDG0

REDG

REDG0

BLUE1

BLUE

BLUE0

1

24

23

22

20

1918

17

16

15

1413

2

4

21

3

5

6

7

8

9

10

1112

VCC VCC

IN OUT

GND

PGND

CXP

SKIP

SHDN

CXN

IC6MAX682

D21N4007

R110k

D11N4007

3

1

2

6

8

4

5

7

1N4007 27k

C622 nF

RESET

22 mF

1 mF

+22 mF

180k

RESET

DATA

SCLK

CS

RE

D1

GR

EE

N1

BLU

E1

MG

ND

1

RE

DG

1

GR

EE

NG

1

BLU

EG

1

LGN

D

HO

RI1

VER

T1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

PC1 VGA

RE

D0

GR

EE

N0

BLU

E0

MG

ND

0

RE

DG

0

GR

EE

NG

0

BLU

EG

0

LGN

D

HO

RI0

VER

TO

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15PC0 VGA

27 pF

27 pF

4 MHz

CS

RESET

F igure 1

An electronic switch allows you to use a single monitor, mouse, and keyboard to control two PCs.

fore returning to the main program loop,the software updates the LEDs, which in-

dicate which PC each device connects to.(DI #2375).


TABLE 1—PC_SEL REGISTERBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Mouse Keyboard Monitor

VCC

VCC

IC3MAX395

IC1PIC16F84

V+ SCLKCS

RESET

DOUT

NO7

COM7

GNDV2

NO0

COM0

NO1

COM1NO2COM2

NO3COM3

NO6

COM6

NO5COM5

NO4COM4

GREENG0

GREENG1

GREENG

BLUOG0

BLUEG

BLUEG1

SCLK

HORI1

HORI

HORI0

VERT1

VERT

VERT0

1

24

23

22

20

1918

17

16

15

1413

2

4

21

3

5

6

7

8

9

10

1112

IC4MAX395

V+ SCLKCS

RESET

DOUT

NO7

COM7

GNDV2

NO0

COM0

NO1

COM1NO2COM2

NO3COM3

NO6

COM6

NO5COM5

NO4

COM4

MGND0

MGND

MGND1

SCLK

RTS1T

RTST

RTS0T

RX1T

RXT

RX0T

1

24

23

22

20

1918

17

16

15

1413

2

4

21

3

5

6

7

8

9

10

1112

VCC

VCC

VCC

VCC

DIN DIN

1C7MAX238

C1+

V+

VCC

GND

C12

V2

C22

C2+

T1INT2INT3INT4IN

R1OUT

R2OUT

R3OUT

R4OUT

T1OUTT2OUTT3OUTT4OUT

R1INR2IN

R3IN

R4IN

OSC1 VDD

VTT

VSS

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0/INTRA4/TOCK1

OSC2

MCLK

RA0

RA1

RA2

RA3

ALL VGAMOUSE KEY-

BOARD

16 14

515

4

17

13

1211109

8

7

6

18

1

2

3

100k

100k

100k

VGA MOUSEKEY-

BOARD

3.3k 3.3k 3.3k

+

+

1 mF

1 mF

1 mF

1 mF

1 mF

10k 10k 10k 10k

10k

RTS1

RTS0

RX1

RX0RTS

RX1T

RX0TRTST

RX

RTS1T

RTS0T

RXTTX

7

3

2316

2

1

24

20

9

1115

8

10

12

13

14

5

18

1921

6

4

2217

1

2

3

4

5

6

7

8

9

RTS1

RTS

RTS0

RX0

RXTX

RX1

MOUSE

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

PC1SERIALPORT

PC0SERIALPORT

RE

D

GR

EE

N

BLU

E

MG

ND

LGN

D

RE

DG

GR

EE

NG

BLU

EG

LGN

D

LGN

D

HO

RI

VER

T

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

MONITOR

CS

RESET

CS

RESET



ideasdesign

The past few decades have seen re-markable progress in magnetic-sen-sor technology. Early and current

sensors exploit the Hall effect; more re-cent devices use an effect called giantmagnetoresistance (GMR). GMR sensorsuse semiconductor processing of materi-als such as indium-antimony. The GMRsensor in Figure 1 comprises four GMRresistors in a Wheatstone-bridge config-uration. Two arms of the bridge have ac-tive resistors; the other two resis-tors are shielded against magneticfields. When a magnetic field impingeson the sensor, the GMR effect decreasesthe resistance of the active pair of resis-tors, and the values of the shielded pairremain constant. GMR-based semicon-ductors are suitable for current meas-urement because they respond to themagnetic field rising from the current.However, in this application, the Wheat-stone-bridge topology allows you tomeasure and control power.

All you need to do is connect the pow-er pins of the GMR sensor to the voltageterminal,V+, and place the cable or tracethe battery current traverses near the sen-sor. The output voltage of the bridge thenrelates to the power, which is the productof V+ and the current. The circuit in Fig-ure 1 provides a way to check a battery’scondition. Measuring a battery’svoltage is not the best way tocheck its condition; it’s better to measurethe power that the battery delivers in adischarge process to evaluate the battery’senergy capacity and life. The circuit inFigure 1 discharges a battery in a con-stant-power mode.You can select the lev-el of discharge power. The GMR sensor’soutput signal is related to the dischargepower. The power stage uses a bipolarDarlington transistor, which draws littlepower from its op-amp driver. You placethe GMR sensor over the pc-board tracethat connects the Darlington’s emitter toground.

Using the GMR sensor in a negative-feedback closed loop, the circuit controlsthe battery discharge in constant-power

mode. The difference amplifier (IC1)

converts the sensor’s differential outputsignal to a unipolar signal; the op amp,

IC2, supplies the appropriate loop gain

and compares the difference-amplifieroutput with the externally selected ref-

_

_

+

+

_

+

15V

15V

15V

115V115V

115V

R1100k

IC2

IC1

VREF

VOUT+VOUT1

Q1

82k

R2100k

R310k

1k

100k

C1100 mF

10k 3

2

V+

V1

7

4 80441

V+SENSE

V+

V1REF

V1

41

OUT

6

7

6

5

INA105/88

2

3

NVEAC004-01

+

1

BATTERY12V, 6 AHR

+

TL081

F igure 1

F igure 2

GMR sensors manage batteriesD Ramirez and J Pelegri, University of Valencia, Spain

A GMR sensor and a closed-loop regulation circuit provide a constant-power discharge process formeasuring a battery’s energy capacity and life.

Sampling shows constant-power discharge profiles at 25, 40, and 45W for Figure 1’s battery-man-agement circuit.

POWER (W)

SAMPLES

Optical power of popular types of LEDs decreases withtemperature. Optical-pow-

er measurements into a typical multi-mode fiber at 62.5/125 mm for a GCA1A194 LED indicate a temperature coef-ficient of approximately 20.4%/-C. Inbipolar analog drivers for short- andmedium-distance fiber links with a dccomponent, you frequently place an LEDin the collector of a differential pair. Forzero-input signals, the LED emits half itsmaximum power (zero reference), andthe bipolar input signal modulates thatpower from zero to maximum. Temper-ature changes cause decreased power ofzero reference and decreased slope effi-ciency of optical power versus input volt-age.

The circuit in Figure 1 allows you tocompensate for both of these tempera-ture-dependent problems, using only theTSF-102 sensor from Texas Instruments(www.ti.com). The device is a tempera-ture-dependent positive-temperature-coefficient resistor with a linear temper-ature coefficient of approximately0.7%/-C at 25-C. For the circuit in Fig-ure 1, you must thermally couple the sen-sor with the LED. IC

2is a summing am-

plifier for the input voltage and thereference voltage from IC

3. The gain is

S1 and increases with temperature. Thetemperature-independent SV

REFdrives

the base of transistor Q2. The thermally

stable current source, Q3, via the differ-

ential pair Q1-Q

2, supplies the LED. Note

that you should mount Q3, D, and D

Zon

a common heat sink.With V

INt0V, temperature changes

unbalance the Q1-Q

2pair, such that the

optical power remains constant. Empir-


ideasdesign

NOTES: LED=GCA 1A194 ST. TSF-102=TI PTC SILICON SENSOR. Q1 THROUGH Q3=BSX95. IC1=LM 158.

IC2=HA 5020. IC3=TL431.

* REFERENCE VOLTAGE. D=SI DIODE.

DZ=5.6V ZENER.

.

5101.5k

IC3

12V

3k

1.5k

1.5k

+

_

+

_

500 TSF-102

+

_

IC2

IC1

112V

3k

3k

*

LED

1k

Q1 Q2

Q3

47

1k

1.8k

DZ

D

10 10

12V

112V

12V

112V

430

F igure 1

Driver thermally compensates LEDAndrzej Wolczko, University of Mining and Metallurgy, Krakow, Poland

A positive-temperature-coefficient sensor and a closed-loop amplifier circuit allow a LED to deliverconstant optical power over temperature.

erence voltage. IC2provides the base cur-

rent for the Darlington transistor,which discharges the battery at aconstant-power rate. Figure 2 shows pro-files of the constant-power battery dis-charge. Figure 3 shows current, voltage,and power profiles of the constant-pow-er discharge process. When the batteryvoltage decreases, the current dischargeincreases, and the power remains con-stant. (DI #2394).

F igure 3

To provide constant-power discharge, the battery’s voltage and current profiles have reciprocal,mirror-image slopes.


POWER (W)

POWER

IDISCH

VBAT

TIME(SEC)

VBAT(V) IDISCH(A)


ideasdesign

ical measurements show that the com-pensation is optimal with V

REFt1.1V. IC

2

amplifies the input signal by a tempera-ture-dependent factor. You obtainmatching of the temperature coefficientof the sensor to the coefficient of the LEDby inserting the additional 500V resistor

in the feedback loop of IC2. Figure 2

shows the LED current (Figure 2a) andthe optical power (Figure 2b) in thefiber-versus-input voltage for 10 and 50-C. The circuit provides an approximatetenfold decrease in the thermal coeffi-cient. The improvement comes at the

cost of a limited input-signal range forlinear operation. The circuit has a band-width of 0 Hz to more than 10 MHz. (DI#2398).

Using the circuit in Figure 1, an LED uses temperature-dependent operating current (a) to produce nearly constant optical power (b) at 10 and 50-C.

1.2

21.5 21 20.5 0 0.5 1 1.521.5 21 20.5 0 0.5 1 1.5

1

0.8

0.6

0.4

0.2

0

120

100

80

60

40

20

0

VIN (V)VIN (V)

PLED (RELPWR)ILED (mA)

108C

508C108C

508C

(b)(a)

F igure 2


Program turns PC sound card into a function generatorDavid Sherman, David Sherman Engineering Co, Everett, WA

You can use a low-cost PC soundcard as an analog-function genera-tor by controlling the PC with the

program “SoundArb.”The program gen-erates standard waveforms, noise, and ar-bitrary waveforms. The program readsarbitrary waveforms from simpleASCII text files consisting of white-space-separated numbers.You can usea program such as Mathcad to createsuch files. SoundArb provides com-mon triggering modes, such as con-tinuous, one-shot, burst, and toggled.An on-screen “button” serves as thetrigger input. The program’s user in-terface is a dialogue-box-style control-panel window. (You can download theself-extracting installation programfrom EDN’s Web site, www.ednmag.com. Click on “Search Databases” andthen enter the Software Center todownload the file for Design Idea#2409.)

The main advantages of using a

sound card as a standard and arbitrarywaveform generator is its low cost andready availability. The typical 16-bit res-olution is better than many arbitrary-waveform generators, the output drivecapability is generally good, and you can’t

beat the price: as low as $10.The disadvantages include poor wave-

form quality, including distortion, noise,and ringing; ac-coupled output only;limited triggering modes, including noexternal trigger; imprecise amplitude ad-

justment; and the possibility of inter-ruptions in the waveform due to oth-er system demands. All in all, thequality of the generated waveformsdepends directly on the quality of thesound card, and the cheapest cardsgenerate the worst waveforms. An os-cilloscope photo (Figure 1) shows a 1-kHz triangle wave such as those gen-erated by cheap sound cards. Thephoto shows rounding of the points ofthe triangle wave due to limited high-frequency bandwidth.

SoundArb is a 32-bit applicationthat runs under 32-bit Windows. Theprogram communicates with thesound card through the Windowsmultimedia application-program-

Using a cheap sound card, the SoundArb programproduces a 1-kHz triangle wave. Limited high-fre-quency bandwidth produces the rounding at thepoints of the triangle wave.

F igure 1


ideasdesign

ming interface, so it should work withmost sound cards. SoundArb places rel-atively light demands on the system, so afast CPU and large amounts of memoryare usually unnecessary. Long arbitrarywaveforms may require more memory.Low-cost sound cards rely on the com-puter’s main memory for waveform stor-age, which means that, if the system isslow or busy, the waveform may be in-terrupted. The sound card must supportthe pulse-code-modulation, audio-waveformat; must have 16 bits of resolution;and must have a maximum sample rateof at least 44.1 kHz. Although standardsample rates are 10.25, 20.5, and 44.1kHz, many sound cards support any in-teger sample rate within a much widerrange. Such a card is a more versatilefunction generator than one that sup-ports only the standard sample rates.

The resolution and full-scale range ofthe amplitude adjustment depend on thedesign of the sound card. Unfor-tunately, no way exists to set theamplitude to a known voltageother than by observing the waveform onan oscilloscope. Many sound cards haverelatively few amplitude levels, and theselevels do not necessarily follow either lin-ear or logarithmic curves. One card test-ed provided 16 amplitude steps, includ-ing “zero.” The remaining 15 stepsfollowed a two-part piecewise-logarith-mic curve.

If you have a stereo sound card,SoundArb allows you to use the “right”channel as a “sync” output to mark thestart of the analog waveform. Note thata sound card reproduces only audio fre-quencies. Most provide no dc-coupledoutput. The output bandwidth typicallyapproximates the 20 Hz to 20 kHz audioband.A good first test of your sound cardis to generate square waves of various fre-quencies and lengths while monitoringthe output with an oscilloscope. Low-fre-quency square waves may show a pro-nounced droop due to an ac-coupledoutput, and ringing on the edges may besevere. The amplitude and frequency ofthe ringing may depend more on thesample rate than on the waveform repe-tition rate. Much of this depends uponthe analog-to-digital-conversion tech-nique that the sound card uses. Take the

time to familiarize yourself with the ana-log limitations of your sound card beforerelying upon it for important work. Formore information on this, search the on-line help index for the keyword “Distor-tion.”

To use the sound card for electronictesting, you probably need to make anadapter cable (Figure 2). A convenientway to make the cable is to obtain twomale BNC-to-cable connectors, a stereominiphone plug, and a short shieldedwire. Because of the low frequencies in-volved, you need no coaxial cable. Youthen connect your normal BNC-to-clip-lead test cables to the male BNCs. Alter-natively, you can make a longer cable byterminating the right channel in a femaleBNC, which you can connect to the syncinput of your oscilloscope. You can ter-minate the left channel in an alligator clipor a minigrabber. If you don’t use the

right-channel sync output, you can get bywith one BNC and one piece of cable be-cause the program supports only “right-channel-sync”mode. The tip of the mini-phone plug carries the left-channelsignal, the first ring carries the right-channel signal, and the main ring pro-vides the ground. Separate shielded ca-bles, rather than a shielded twisted pair,between each BNC and the phone plugare recommended because with thetwisted pair the sync pulse edges capaci-tively couple into the waveform andcause glitches. As an alternative to usinga miniphone plug, most sound cardshave an internal waveform output com-prising a pin header on the card. Somecards also have jumpers that you can useto select between “line out” and “speak-er out,” the difference being the outputimpedance or voltage.

Grounding may be less than optimumbecause no good way exists to connectthe PC’s ground to the ground of the de-vice under test. If glitches from the syncline are a problem, you may be able todisconnect that line’s shield from its BNCshell, assuming that the waveform line’sshield remains connected to its BNC’sshell. If necessary, you can break a badground loop by isolating, or floating, thePC and its monitor from the power-lineground. You cannot use a “cheater” plugbecause it defeats the safety aspects ofgrounding and can allow the PC chassisand peripherals to become hot. To isolatethe PC from the power line and itsground, use a medical-grade isolationtransformer that includes a Faradayshield between the primary and second-ary windings. This transformer often re-duces interference from noisy powerlines and may reduce conducted EMI, es-

pecially if used with an RF-line-filterblock.

Never float the PC or any other testequipment as a way to connect theground to a high voltage, for example, toconnect an oscilloscope probe across acurrent-sensing resistor in a hot ac pow-er line. Doing so could kill you, and youcould destroy expensive test equipmentwhose power supply was not designed fora ground-to-neutral voltage of morethan 30V. If you need to connect testequipment to a high voltage, use opticalor magnetic isolation in the signal wires,not in the equipment’s power supply.Small, modular isolation amplifiers withlow distortion are readily available at rea-sonable prices.(DI #2409)

A convenient adapter cable comprises two male BNC-to-cable connectors, a stereo miniphoneplug, and a short length of shielded wire.

RIGHT CHANNELLEFT CHANNEL

GROUND

SHIELDED CABLE

FEMALE BNC-SYNC OUTPUT

MALE BNC-WAVEFORM OUTPUT

1/8-IN. STEREO MINIPHONE PLUG

F igure 2



ideasdesign

Li-ion battery charger adapts to different chemistriesFran Hoffart, Linear Technology Corp, Milpitas, CA

Rechargeable lithium-ion (Li-on) cells require a precise chargingvoltage for maximum performance.

The battery chemistry, of which there aremany, determines the optimum chargevoltage. Two of the more common charg-ing voltages are 4.1V650 mV and4.2V650 mV per cell.

Consider the following situation: Youhave thousands of three-cell Li-ion bat-tery chargers with an output voltage of12.6V61%. However, because of a bat-tery-chemistry change, your chargersnow need 12.3V61%. The 12.6V outputis well-regulated and has current limit-ing, but the voltage is 300 mV too high,and you cannot easily adjust it.

The circuit in Figure 1 can solve thisproblem by providing a constant 300-mV drop between V

INand V

OUTat cur-

rents as high as 3A. The accuracy of the300-mV drop is nearly as good as the ac-curacy of the input voltage, which in thiscase is approximately 1%. This circuit re-

quires an input voltage that is fixed, reg-ulated, and preferably current-limited. Aprecision voltage divider across the reg-ulated input derives the 300 mV neces-sary for the circuit to operate, thus elim-inating the need for an external voltagereference. The circuit also includes a log-ic-level low-quiescent-current shut-down. In shutdown, the series MOSFET,Q

1, is off, and the total circuit current

drops to approximately 8 mA.The circuit operates by developing a

300-mV reference voltage across R1

andapplying this voltage to the invertinginput of the op amp. The noninvertinginput connects to the output side of thep-channel MOSFET. The resultant feed-back loop forces the voltage across Q

1to

equal the voltage across R1, which is 300

mV. In normal operation, the voltagedrop across R

1and Q

1are equal in val-

ue but opposite in polarity, thus forcingthe voltage between the two op-amp in-puts to be 0V. C

1provides stability, and

C2

and C3

bypass the supply.Although this circuit was intended to

solve a Li-ion-charger problem, you canuse the circuit for any application thatneeds to drop a constant voltage. Chang-ing the appropriate resistor values allowsthe circuit to accommodate other inputvoltages or voltage drops. The voltagedrop across R

1determines the voltage

drop between VIN

and VOUT

. For low in-put voltages of 5V, reduce R

2to 470V to

ensure adequate gate drive for Q1. Q

1has

a low RDS(ON)

and comes in an SO-8 sur-face-mount package. Allow a minimumof 1 sq in. of pc-board copper around theeight leads for heat sinking. Higher volt-age drops require additional copper area.For even higher power levels or highercurrents, select a MOSFET in a TO-220package and mount it to an appropriateheat sink. (DI #2408)

A feedback loop comprising the op amp and Q1 produces a constant voltage drop between VIN and VOUT, thereby providing a low-voltage, series-zenertype of function.

+_

+

LT1636

3

2

NOTES:Q1=35-mV P-CHANNEL MOSFET, Si4435 (SILICONIX).SCHEMATIC SHOWS BODY DIODE.

VIN VOUT

Q1

12.6V 61%AT 2A

12.3V'61%AT 2A

C34.7 mF

16V

R24.7k

C10.02 mF

R112.1k0.5%

499k0.5%

300 mV

300 mV

+ 1

+

1

+ C20.1 mF

25V

10k

7

6

SHUTDOWNINPUT

ON SHUTDOWN

45

F igure 1





Name

Title

Phone

E-mail Fax

Company

Address

Country ZIP

Design Idea Title



Exclusive publishing rights remain with Cahners Publish-ing Co unless entry is returned to author, or editor gives writ-ten permission for publication elsewhere.In submitting my entry, I agree to abide by the rules of the


Signed

Date



ideasdesign



Several integrated high-side cur-rent-sense amplifiers, suchas the MAX4172 (Maxim In-

tegrated Products, maxim-ic.com), makeit easy to measure the current from apositive power supply. With a couple ofresistors, these devices provide a ground-referenced voltage output that is pro-portional to the delivered current (Fig-ure 1a).

Unfortunately, no equivalent devicesimplement a true low-side current sensefor negative supplies. You can use thehigh-side devices to measure currentfrom negative supplies, but this approachhas drawbacks. The sense resistor mustbe in the load’s ground lead, which ef-fectively floats the load off ground by thesense resistor voltage, and the outputvoltage, V

OUT, is referred to the negative

supply and not to ground (Figure 1b).Both of these characteristics are unde-sirable.

The circuit in Figure 2 implements atrue low-side, precision current-senseamplifier that provides a ground-refer-enced voltage proportional to thenegative supply current and thatdoes not float the load off ground. Thiscircuit is similar to the circuit in the

MAX4172 but is reconfigured fora negative supply. When currentflows through the load, a propor-tional voltage, V

SENSE, develops

across the current-sense resistorR

SENSE: V

SENSE5I

LOAD•R

SENSE. To stay

balanced, the op amp raises itsoutput until V

SENSE also appears

across R1. The current through R

1

equals VSENSE

/R1, which is identical

to the current through R2, which

scales VOUT

. The equation for VOUT

is then as follows:


ideasdesign

Current-sense amplifier precisely measures low side ......................................193

Connect a modem to a Basic Stamp ............................................................194

Bias supply provides short-circuit protection ....................................................196

Analog multiplier works over large frequency range ..........................................200

5V logic pulser is battery-powered..........204


Current-sense amplifier precisely measures low sideJohn Ursoleo, Silicon Mountain Design, Colorado Springs, CO

High-side current-sense amplifier ICs, such as the MAX4172, make it easy to measure positive-power-supply current (a). Although you can also use these devices to measure current from nega-tive supplies (b), the resultant circuit has undesirable characteristics.

(a)

(b)

MAX4172

LOAD

POSITIVE SUPPLY

RSENSE

ILOAD

SCALINGRESISTOR

VOUT=kI

MAX4172

LOAD

RSENSEILOAD

SCALINGRESISTOR

VOUT

NOTE: k IS A CONSTANT.

NOTE: LOAD IS NOT GROUNDED, AND VOUT IS REFERRED TO THE NEGATIVE SUPPLY.

NEGATIVE SUPPLY

F igure 1

.R

RRI

RR

VV

1

2SENSELOAD

21

SENSEOUT

••

=•=1A true low-side, precision current-sense amplifier pro-vides a ground-referenced voltage that is proportionalto the negative supply current and does not float theload off ground.

_

+

1/2LT1490

LOAD115V

115V

ILOADNEGATIVE SUPPLY

(13 TO 144V)

1 mF RSENSE 0.033

1VSENSE+

1VSENSE+

R1 1003

2

8

1

4

Q12N930

47 pF

VOUT

R25.00k

10kCALIBRATEDF igure 2


ideasdesign

To minimize the effects of the op amp’soffset voltage, the voltage developedacross the sense resistor should be largerthan this offset value. The circuit in Fig-ure 2 develops a 0 to 25V output for loadcurrents of 0 to 3A and is accurate toabout 1%.

You must adhere to the following com-ponent restrictions: The op amp needs to

have an input common-mode range thatincludes the negative rail. The op-ampoutput needs to be a rail-to-rail type. Q

1

should have a high beta at low currentsto minimize errors due to base current.Keep R

1small so that op-amp bias cur-

rents are insignificant. For greater accu-racy, you can replace Q

1with an en-

hancement-mode n-channel MOSFET

to eliminate base-current errors; howev-er, operation as low as 3V is then unlike-ly. You can also replace the op amp witha lower offset device at the expense ofhigh-voltage operation to 244V. (DI#2410)

The 2400-bps modem in Figure 1makes it easy to connect a Ba-sic Stamp (Parallax Inc, www.

parallaxinc.com) to a telephone modem.Using this circuit, you can call home viayour PC and find out if the house is stillthere. The Basic Stamp2, BS2-IC, has thenecessary programming space, and a 64-kbyte StampMEM memory-storageboard enhances site data collection.

In the setup configuration of Figure 1,the Basic Stamp can read data from sen-sors and store the result on the Stamp-MEM board. When the modem receivesa call, the Basic Stamp reads the Stamp-MEM board and transfers the stored datadirectly to the modem, which in turnsends it to the remote PC or Basic Stampterminal that has a modem interface andstandard communication software.

Simple software code performs datamovement to and from the modem. Thesoftware collects sensor data and placesthe modem in an auto-answer mode fora short time and loops back to collectmore data. When a remote terminalsends a phone call, the looping stops, andthe Basic Stamp answers the phone callby requesting the terminal to type “start.”After receiving the typed input from theremote terminal, the Basic Stamp readsthe StampMEM data-storage board andtransfers the entire stored data to the re-mote terminal. (You can download theprogram from EDN’s Web site, www.ednmag.com. Click on “Search Databas-

es”and then enter the Software Center todownload the file for Design Idea #2411.)

After data transfer is complete, the Ba-sic Stamp hangs up the phone call, re-turns to collecting sensor data, and awaitsanother phone call. The software com-munications between the Basic Stamp,modem, and memory data storage arethrough the “serin” and “serout” com-mands. This approach allows the BasicStamp to use just a few I/O pins, leavingat least 11 pins for the sensors’ data in-put. The program includes no sensor in-puts; doing so would complicate the soft-

ware. The StampMEM memory datastorage is unnecessary if you intend to re-tain the data within the available mem-ory on the Basic Stamp. You can easilyconnect many data-storage devices andEEPROM chips to the circuit. Sensor anddata-storage-device software codes areavailable for free on the Parallax Web site.(DI #2411)

Connect a modem to a Basic StampKen Gracey, Parallax Inc, Rocklin, CA

REMOTE PC OR BASICSTAMP TERMINAL WITH

A MODEM

STAMPMEM(OPTIONAL)

BASICSTAMPBS2-IC

GND

GND

5V

5V

5V

CEMETEKMODEMCH1786

TXD

RXD

DTR

RST

TIP

RING

P1

P2

P3

P4

P0

P5 THROUGHP15 TO

SENSORS

GND

RJ11PHONEPLUG

The 2400-bps modem allows you to connect a modem to a Basic Stamp.



F igure 1


ideasdesign

Bias supply provides short-circuit protectionDave Kim, Linear Technology Corp, Milpitas, CA

Most power-supply designs re-quire protection from a short-cir-cuit fault condition. One of the

methods of short-circuit protection is cy-cling, or the “hiccup-mode” method.This method is an effective way of con-trolling a short-circuit fault conditionwhile minimizing power loss in the cir-cuit. Figure 1 shows a trickle-chargedbias supply that uses an LT1431 pro-grammable reference, IC

1, to start an

LT1680 high-power dc/dc step-up con-troller, IC

2, which operates here in a for-

ward-converter topology. This circuit isuseful for applications with wide input-

voltage ranges, such as telecommunica-tion applications with input ranges of 18to 72V.

IC2’s undervoltage-lockout (UVLO)

hysteresis, which you can adjust using theR

1/R

2voltage divider at the RUN/SHDN

pin, sets the short-circuit cycling. Anoverwinding, L

1, on L

2’s output inductor

provides a VCC

of 12V. When a short-cir-cuit fault at the output drags V

CC down to

IC2’s UVLO threshold, IC

2shuts down,

and a constant bias current starts tocharge the bias supply capacitor. IC

1con-

trols the scaled current mirror that gen-erates a constant current and continual-

ly adjusts itself to keep the input of thecurrent mirror at 3 mA. When this con-stant current charges the bias capacitorto the level of IC

2’s turn-on threshold

(approximately 12V), IC2

wakes up. Youcan calculate the turn-on delay using thefollowing equation:

With a constant charging current of 3mA, the turn-on delay for the circuit is

5VREF

SYNC

12VIN

GATE

PGND

RUN/SHDN

SENSE1

SENSE+

CT

IAVG

VC

SGND

VFB

VREF

IC2

16

152

3

5

6

7

8

14

13

12

11

10

9

LT1680CSW0.1 mF

0.1 mF

0.1 mF

220 mF 220 mF

3k

1500 pF

4.02k

R211.5k

MBRS120T3

++

MBR2060CT

MBR2060CT

0.001 mF

100 mF

10

L2

VOUT 5V AT 7A

330 mF32

3.74k

1.24k

10

1000.0332200

pF

2:1

IRF640

R1100k

L1

MUR120

+

VCC

BIAS CAPACITOR

50300

470 pF

33

COL V+REF

RMGSGF6 5 LT1431

IC1

7

8

1 3

24k

MMBTA56LT132

++

VIN 18 TO 72V

MMBTA06LT1

A programmable reference, IC1, and a bias-capacitor network control the on/off cycling of IC2’s step-up controller during a short-circuit fault condition.

.I

VC

T

CHARGE

THRESHOLD ONTURNBIAS

DELAY ONTURN

−

−

×=

F igure 1


ideasdesign

approximately 400 msec. You can pro-duce shorter turn-on delays byreducing the value of the bias ca-pacitor or increasing the bias current. Ifyou increase the bias current, you mustscale the transistors according to theirpower-dissipation ratings.

Figure 2a shows the bias-capacitorvoltage and the output of the forward-converter voltage during turn-on. Whenthe bias capacitor charges to the turn-onthreshold voltage of 12V set by IC

2, the

output turns on and the bias capacitor’svoltage dips to 11.5V, which is the levelthat the overwinding sets. Figure 2bshows the bias capacitor and output volt-age in cycling mode during a short-cir-cuit fault. IC

1sets the constant current,

which charges the bias capacitor to theturn-on threshold, and IC

2starts up.

However, the overwinding generates novoltage because of the short at the out-put. And because IC

2’s quiescent current

is greater than the charge current, thebias capacitor discharges. Dischargingthe bias capacitor to less than the UVLOthreshold shuts down IC

2. This charging

and discharging cycle repeats until youremove the fault.

You can calculate the restart time us-ing the following equation, where V

RUN

equals the turn-on threshold set byRUN/SHDN:

When implementing a cycling type ofshort-circuit protection, a constraint ison the maximum capacitive load forwhich the power supply starts. The ca-pacitive load depends on the short-cir-cuit current and the threshold voltage atwhich the overwinding back-feeds thebias supply. The output rise time of theLT1680 must be less than the holduptime that the hysteresis and the bias ca-pacitor provide.

You can calculate the start-up time us-ing:

where

You can calculate the hold-up time using:

where IRUN

is the current necessary tostart up IC

2. The start-up time must be

less than the hold-up time for the powersupply to start. (DI #2414)

The output turns on when the bias capacitor reaches 12V (a). During a short-circuit fault, the biascapacitor continually charges and discharges until you remove the fault (b).


.I

)VV(C

T

CHARGE

UVLORUNBIAS

RESTART

1×=

,II

VC

T

LOADSHORT

THRESHOLDOUT

RISE OUTPUT

1

×=

.V

VV

V

CC

OUTULVO

THRESHOLD

×=

,I

)VV(C

T

RUN

UVLORUNBIAS

HOLDUP

1×=

VBIAS CAP

(2V/DIV)

VOUT

(2V/DIV)

(a)

TIME (100 mSEC/DIV)

VBIAS CAP

(2V/DIV)

VOUT

(2V/DIV)

(b)TIME (50 mSEC/DIV)

F igure 2


ideasdesign

Schottky-diode double-balancedmixers are common elements inanalog and digital telecommuni

cations circuits that operateat radio and microwave fre-quencies. Transistor analogmultipliers, such as log-antilog,MOS, and variable-transconduc-tance types, are usually limited tofrequencies of much less than 1GHz. In the circuit in Figure 1,an MBD301 hot-carrier Schot-tky-diode bridge forms the coreof a four-quadrant analog multi-plier and, therefore, can operateover a much larger frequencyrange than can transistor analogmultipliers. This highly sensitivedouble-balanced modulator pro-vides a high-quality output withlow spurious-response level. Us-ing the proper high-frequencycircuit and IC techniques, you

can use this type of circuit for digital andanalog communications, radar, productdetection, AGC circuits, and phase de-

tectors in the radio and microwavebands.

Like many double-balanced mixersand analog multipliers, this circuit hasan amplifier, the MAX4223, for the IF.This differential amplifier is the onlyessential amplifier in the circuit; theMAX4224s are two 10-dB amplifierstages. If you use a balun transformerwith a center-tap-grounded secondaryin place of the dual AD8056, inputs Aand B can be radio or microwave fre-quencies. With the input amplifiersshown, however, the frequency rangefor Input A is limited to about 100MHz. You can use fast transistor am-plifiers for the input and the outputamplifiers to achieve system band-widths greater than 1 GHz. You canalso use a fast buffer amplifier—suchas the MAX4405, which has a 75V out-put—at Input B for improved port iso-lation.

Analog multiplier works over large frequency rangeHubert Houtman, Consultant, Blaine, WA

An MBD301 hot-carrier Schottky-diode bridge forms the core of a four-quadrant analog multiplier that performs continuous computations of the prod-uct of arbitrary input signals A and B.

1k 1k

B

+

1

+

1

+

1

+

1+

1

VOUT

50680

330

680330

150MAX4224

MAX4224

MAX4223

150

1k

1k

2.2k

2.2k

2.2k

2.2k

B (IN)

(A2B)2

2A

(A+B)2

A

3.9k3.9k

2N3904

15V

5V

A(IN) 680

680

AD8056(DUAL)

3.9k 3.9k

2N3906

3.3k

1k

MBD301

NOTE: ALTHOUGH NOT SHOWN, ALL OP AMPS HAVE MANUFACTURER-RECOMMENDED DECOUPLING CAPACITORS.

A quarter-squares multiplier test pattern on an X-Y oscillo-scope illustrates good linearity and balanced behavior inall four quadrants. (Horizontal = Input A at 10 mV/div; ver-tical = VOUT at 20 mV/div.)

F igure 2

F igure 1


ideasdesign

This four-quadrant analog multiplieris a quarter-squares multiplier based onthe identity:

(A1B)22(A2B)254AB.The MAX4223 differential amplifier,

which has a 1-GHz bandwidth, registers(A1B)2 from the left bridge while sub-tracting (A2B)2 from the right bridge toform the product:

VOUT

5AB/K,where the constant, K, is 12mV. You can add the carri-er at the differential ampli-fier’s input for amplitude mod-ulation as necessary.

The differential outputacross the 1-kV resistor of eachdiode bridge is a precisely sym-metric, even function of thevoltage across it: A1B for theleft bridge and A2B for theright bridge. Consequently, thebridge’s V

OUTcontains only

even terms of the combinedTaylor series due to the fourdiode currents. The constantterms cancel out because theMAX4223 subtracts the bridgeoutputs, so the dominant termis the square term. Higher or-der even terms do not con-tribute, provided that inputs Aand B stay at less than approx-imately 150 mV. For large in-puts, each bridge behaves as afull-wave rectifier; the diodesbecome forward-biased withresistance smaller than the 1-kV load, and the parabolicbranches ultimately degenerateinto straight lines that the loadresistor dominates. Therefore,the multiplier is unusable withsuch large inputs.

The circuit includes a bal-anced, double current-mirrornetwork that supplies the diodebridge with four bias currents.A single 1-kV potentiometercontrols the current, and four3.9-kV resistors accurately dis-tribute equal, balanced cur-rents to the two bridges whilepreventing crosstalk betweenthe bridges. These four resistorsalso isolate the diode bridges

from the transistors, thereby improvingsystem bandwidth.

Without this bias-current network, thebridge requires an approximately 5-MVload resistor for parabolic behavior. Thisvalue precludes this design’s use in high-frequency circuits because the currentsare extremely small and the time con-stants are very long when you connectthe bridge to an amplifier input of a few

picofarads. With the 1-kV load for thebridge and no bias network, the bridgeoutput has a pronounced flat bottomaround the origin. Fortunately, with thebias current of 1.08 mA in each 3.9-kVresistor, the Schottky diodes become for-ward-biased into partial conduction with340 mV for each path, and the bridgeyields an accurate and symmetric square-law output with a low source resistance.

You can use one such bridgewith the differential amplifieras a fast squarer for frequency-doubling and square-law de-tection, for example. Withslightly more current, you canmake the load resistor as littleas 50V.

The multiplier test patternin Figure 2 results from a 5-kHz sine wave on both Input Aand the horizontal input anda 20-kHz square wave from a100V source set at 0-, 6-, 12-,18-, and 24-mV amplitude lev-els at Input B. Over this rangeof inputs, this multiple expo-sure shows that the analogmultiplier exhibits linear be-havior with errors of less than1% of full scale. In Figure 3a,Trace A shows a double-side-band, suppressed-carrier out-put resulting from a 228 dBm,20-kHz square-wave carrier,and Trace B results from a 20-kHz sine-wave carrier. Trace Cshows the 2-kHz modulationsignal on Input A. Figure 3bshows double-sideband sup-pressed-carrier output signalsat Input B frequencies of 10MHz (Trace A), 25 MHz(Trace B), and 120 MHz (TraceC) using a 600-kHz sine-wavemodulator at Input A . Trace Dshows that same signal as TraceC but at 5 nsec/division, toshow that the rise time of themultiplier in this breadboardversion is just a few nanosec-onds. (DI #2413)

Example multiplier outputs include a double-sideband suppressed-car-rier with a 20-kHz square-wave carrier at Input B (a) and outputs withinput frequencies as large as 120 MHz (b).


(a)

A

(b)

B

C

A

B

C

D

VERTICAL SCALE=50 mV/DIVHORIZONTAL SCALE=100 mSEC/DIV

VERTICAL SCALE=10V/DIV

TRACE DESCRIPTION

MULTIPLIER OUTPUT WITH A 12-mV, 20-kHzSQUARE-WAVE CARRIER AT INPUT B

MULTIPLIER OUTPUT WITH A 12-mV, 20-kHzSINE-WAVE CARRIER AT INPUT B

2-kHz SINE-WAVE-MODULATION SIGNAL ATINPUT A

A

B

C

TRACE HORIZONTAL SCALE

500 NSEC/DIV

500 NSEC/DIV

500 NSEC/DIV

5 NSEC/DIV

DESCRIPTION

MULTIPLIER OUTPUT WITH A 10-MHz SIGNAL AT INPUT B



TRACE C WITH AN EXPANDED TIME SCALE

A

B

C

D

F igure 3

NOTE:INPUT A IS A 600-kHz SINE-WAVE-MODULATION SIGNAL.


ideasdesign

Abattery-powered, pushbutton-triggered TTL/CMOS-compatiblesource of debounced 5V logic puls-

es is a simple but handy piece of testequipment to have in any tool kit (Figure1). The circuit’s battery-powered opera-tion complicates what would otherwisebe a trivial exercise in switch-bounce andtiming-circuit design. The convenientuse of battery power simultaneously im-poses two requirements: near-zero qui-escent-current draw and input-varia-tion-tolerant voltage regulation. A near-zero quiescent-current draw minimizesthe likelihood that you will encounter adead battery when you need to use thelogic pulser, and input-variation-tolerantvoltage regulation accommodates the in-evitable voltage droop as the battery agesand traverses its service-life curve fromfresh to flat.

Of course, the unglamorous on/offswitch is a traditional and serviceableway to fulfill the first requirement. Un-fortunately, the effectiveness of an on/offswitch depends directly, and regrettably,on whether you remember to use it. Ne-glecting proper and timely operation ofon/off switches may result in batterydamage. Thus, a key feature of the logicpulser in Figure 1 is a satisfactory batterylife without dependence upon a separate,

manual on/off switch.The trick to this design feature is the

use of a single NO spst momentary-con-tact pushbutton switch to control boththe trigger logic and the voltage regula-tor. In the quiescent state, S

1is open,

which leaves the ground-reference pin ofthe 78L05 regulator floating and causesthe regulator’s output voltage to saturateabout 1V less than the input voltage fromthe battery. The circuit applies the re-sulting 7 to 8V to the V

DDpin of the

74C04 and, via R5, to the debounce time-

out circuit comprising R6, R

1, and C

1.

In this state, the 74C04 typically con-sumes less than 1 mA and is the onlypower demand on the battery. The regu-lator is floating and consumes no pow-er, despite its normally multimilliampquiescent current. This low power im-plies a battery-life expectancy that is lim-ited only by the self-discharge character-istics, or shelf life, of the battery. Thisexpectancy is typically 10 years for alka-line and much longer for lithium. Mean-while, the fact that the circuit applies V

DD

to the output gates of IC1B

and IC1C

whilethe steady state of timing circuit R

2, R

3,

R4, and C

2applies a logic 1 to the inputs

of these gates ensures a solid low-im-pedance logic low at the pulser’s output.

When you push the trigger button, the

sequence of events begins with thegrounding of the regulator’s referencepin and the consequent regulation—in-dependent of battery voltage—of the74C04’s V

DDto 5V. Simultaneously,

grounding one end of R6

starts the dis-charge of C

2. The resulting approximate

20-msec delay provides adequate timefor reliable debounce of the pushbutton,thus preventing the possibility of spuri-ous multiple pulses in response to a sin-gle button press.

When IC1E

’s input ramps to the ap-proximate 2.5V CMOS logic threshold,the positive feedback around the IC

1E-

IC1D

pair via C1causes the circuit to pres-

ent a clean logic transition to the C2/R

3

differentiator. The R2, R

3, and C

2network

combines with the IC1F

-IC1A

regenerativepair to convert the resulting edge into asingle, pristine, 100-msec pulse. The par-allel IC

1B-IC

1Cpair then inverts and

buffers this pulse to the output. Follow-ing the pulse, the circuit output returnsto a stable 0V level; the output remainslow until you release the pushbutton,which readies the trigger circuit for an-other cycle. (DI #2412)

5V logic pulser is battery-poweredW Stephen Woodward, University of North Carolina, Chapel Hill, NC

+9V

78L05

1N4001IN OUT

0.01 mF

0.1 mF

0.1 mF 0.01 mFGND

R515k

R115k

R315k R2

15kR4

330k

C1 C2R6330k

S1

270

TRIGGER

IC1E IC1D

IC1F

IC1B

IC1A11

7

1410

9

8

IC1C

13

12

1

2

3

56

4

20-mSEC DEBOUNCE 5V

0V100

mSEC

OUTPUT PULSEIMPEDANCE~150V

NOTES:QUIESCENT BATTERY DRAIN <<1 mA.NO POWER SWITCH NECESSARY.IC1A TO IC1F= 74C04 OR CD4069B.1/6

2

This battery-powered debounced pulse generator conserves battery life without using an on/off power switch.


F igure 1




Name

Title

Phone

E-mail Fax

Company

Address

Country ZIP

Design Idea Title



Exclusive publishing rights remain with CahnersPublishing Co unless entry is returned to author, or editorgives written permission for publication elsewhere.

In submitting my entry, I agree to abide by the rules of theDesign Ideas Program.

Signed

Date



ideasdesign


Circle 12 or visit www.ednmag.com/infoaccess.asp Circle 13 or visit www.ednmag.com/infoaccess.asp

Several integrated high-side cur-rent-sense amplifiers, suchas the MAX4172 (Maxim In-

tegrated Products, maxim-ic.com), makeit easy to measure the current from apositive power supply. With a couple ofresistors, these devices provide a ground-referenced voltage output that is pro-portional to the delivered current (Fig-ure 1a).

Unfortunately, no equivalent devicesimplement a true low-side current sensefor negative supplies. You can use thehigh-side devices to measure currentfrom negative supplies, but this approachhas drawbacks. The sense resistor mustbe in the load’s ground lead, which ef-fectively floats the load off ground by thesense resistor voltage, and the outputvoltage, V

OUT, is referred to the negative

supply and not to ground (Figure 1b).Both of these characteristics are unde-sirable.

The circuit in Figure 2 implements atrue low-side, precision current-senseamplifier that provides a ground-refer-enced voltage proportional to thenegative supply current and thatdoes not float the load off ground. Thiscircuit is similar to the circuit in the

MAX4172 but is reconfigured fora negative supply. When currentflows through the load, a propor-tional voltage, V

SENSE, develops

across the current-sense resistorR

SENSE: V

SENSE5I

LOAD•R

SENSE. To stay

balanced, the op amp raises itsoutput until V

SENSE also appears

across R1. The current through R

1

equals VSENSE

/R1, which is identical

to the current through R2, which

scales VOUT

. The equation for VOUT

is then as follows:


ideasdesign

Current-sense amplifier precisely measures low side ......................................193

Connect a modem to a Basic Stamp ............................................................194

Bias supply provides short-circuit protection ....................................................196

Analog multiplier works over large frequency range ..........................................200

5V logic pulser is battery-powered..........204


Current-sense amplifier precisely measures low sideJohn Ursoleo, Silicon Mountain Design, Colorado Springs, CO

High-side current-sense amplifier ICs, such as the MAX4172, make it easy to measure positive-power-supply current (a). Although you can also use these devices to measure current from nega-tive supplies (b), the resultant circuit has undesirable characteristics.

(a)

(b)

MAX4172

LOAD

POSITIVE SUPPLY

RSENSE

ILOAD

SCALINGRESISTOR

VOUT=kI

MAX4172

LOAD

RSENSEILOAD

SCALINGRESISTOR

VOUT

NOTE: k IS A CONSTANT.

NOTE: LOAD IS NOT GROUNDED, AND VOUT IS REFERRED TO THE NEGATIVE SUPPLY.

NEGATIVE SUPPLY

F igure 1

.R

RRI

RR

VV

1

2SENSELOAD

21

SENSEOUT

••

=•=1A true low-side, precision current-sense amplifier pro-vides a ground-referenced voltage that is proportionalto the negative supply current and does not float theload off ground.

_

+

1/2LT1490

LOAD115V

115V

ILOADNEGATIVE SUPPLY

(13 TO 144V)

1 mF RSENSE 0.033

1VSENSE+

1VSENSE+

R1 1003

2

8

1

4

Q12N930

47 pF

VOUT

R25.00k

10kCALIBRATEDF igure 2


ideasdesign

To minimize the effects of the op amp’soffset voltage, the voltage developedacross the sense resistor should be largerthan this offset value. The circuit in Fig-ure 2 develops a 0 to 25V output for loadcurrents of 0 to 3A and is accurate toabout 1%.

You must adhere to the following com-ponent restrictions: The op amp needs to

have an input common-mode range thatincludes the negative rail. The op-ampoutput needs to be a rail-to-rail type. Q

1

should have a high beta at low currentsto minimize errors due to base current.Keep R

1small so that op-amp bias cur-

rents are insignificant. For greater accu-racy, you can replace Q

1with an en-

hancement-mode n-channel MOSFET

to eliminate base-current errors; howev-er, operation as low as 3V is then unlike-ly. You can also replace the op amp witha lower offset device at the expense ofhigh-voltage operation to 244V. (DI#2410)

The 2400-bps modem in Figure 1makes it easy to connect a Ba-sic Stamp (Parallax Inc, www.

parallaxinc.com) to a telephone modem.Using this circuit, you can call home viayour PC and find out if the house is stillthere. The Basic Stamp2, BS2-IC, has thenecessary programming space, and a 64-kbyte StampMEM memory-storageboard enhances site data collection.

In the setup configuration of Figure 1,the Basic Stamp can read data from sen-sors and store the result on the Stamp-MEM board. When the modem receivesa call, the Basic Stamp reads the Stamp-MEM board and transfers the stored datadirectly to the modem, which in turnsends it to the remote PC or Basic Stampterminal that has a modem interface andstandard communication software.

Simple software code performs datamovement to and from the modem. Thesoftware collects sensor data and placesthe modem in an auto-answer mode fora short time and loops back to collectmore data. When a remote terminalsends a phone call, the looping stops, andthe Basic Stamp answers the phone callby requesting the terminal to type “start.”After receiving the typed input from theremote terminal, the Basic Stamp readsthe StampMEM data-storage board andtransfers the entire stored data to the re-mote terminal. (You can download theprogram from EDN’s Web site, www.ednmag.com. Click on “Search Databas-

es”and then enter the Software Center todownload the file for Design Idea #2411.)

After data transfer is complete, the Ba-sic Stamp hangs up the phone call, re-turns to collecting sensor data, and awaitsanother phone call. The software com-munications between the Basic Stamp,modem, and memory data storage arethrough the “serin” and “serout” com-mands. This approach allows the BasicStamp to use just a few I/O pins, leavingat least 11 pins for the sensors’ data in-put. The program includes no sensor in-puts; doing so would complicate the soft-

ware. The StampMEM memory datastorage is unnecessary if you intend to re-tain the data within the available mem-ory on the Basic Stamp. You can easilyconnect many data-storage devices andEEPROM chips to the circuit. Sensor anddata-storage-device software codes areavailable for free on the Parallax Web site.(DI #2411)

Connect a modem to a Basic StampKen Gracey, Parallax Inc, Rocklin, CA

REMOTE PC OR BASICSTAMP TERMINAL WITH

A MODEM

STAMPMEM(OPTIONAL)

BASICSTAMPBS2-IC

GND

GND

5V

5V

5V

CEMETEKMODEMCH1786

TXD

RXD

DTR

RST

TIP

RING

P1

P2

P3

P4

P0

P5 THROUGHP15 TO

SENSORS

GND

RJ11PHONEPLUG

The 2400-bps modem allows you to connect a modem to a Basic Stamp.



F igure 1


ideasdesign

Bias supply provides short-circuit protectionDave Kim, Linear Technology Corp, Milpitas, CA

Most power-supply designs re-quire protection from a short-cir-cuit fault condition. One of the

methods of short-circuit protection is cy-cling, or the “hiccup-mode” method.This method is an effective way of con-trolling a short-circuit fault conditionwhile minimizing power loss in the cir-cuit. Figure 1 shows a trickle-chargedbias supply that uses an LT1431 pro-grammable reference, IC

1, to start an

LT1680 high-power dc/dc step-up con-troller, IC

2, which operates here in a for-

ward-converter topology. This circuit isuseful for applications with wide input-

voltage ranges, such as telecommunica-tion applications with input ranges of 18to 72V.

IC2’s undervoltage-lockout (UVLO)

hysteresis, which you can adjust using theR

1/R

2voltage divider at the RUN/SHDN

pin, sets the short-circuit cycling. Anoverwinding, L

1, on L

2’s output inductor

provides a VCC

of 12V. When a short-cir-cuit fault at the output drags V

CC down to

IC2’s UVLO threshold, IC

2shuts down,

and a constant bias current starts tocharge the bias supply capacitor. IC

1con-

trols the scaled current mirror that gen-erates a constant current and continual-

ly adjusts itself to keep the input of thecurrent mirror at 3 mA. When this con-stant current charges the bias capacitorto the level of IC

2’s turn-on threshold

(approximately 12V), IC2

wakes up. Youcan calculate the turn-on delay using thefollowing equation:

With a constant charging current of 3mA, the turn-on delay for the circuit is

5VREF

SYNC

12VIN

GATE

PGND

RUN/SHDN

SENSE1

SENSE+

CT

IAVG

VC

SGND

VFB

VREF

IC2

16

152

3

5

6

7

8

14

13

12

11

10

9

LT1680CSW0.1 mF

0.1 mF

0.1 mF

220 mF 220 mF

3k

1500 pF

4.02k

R211.5k

MBRS120T3

++

MBR2060CT

MBR2060CT

0.001 mF

100 mF

10

L2

VOUT 5V AT 7A

330 mF32

3.74k

1.24k

10

1000.0332200

pF

2:1

IRF640

R1100k

L1

MUR120

+

VCC

BIAS CAPACITOR

50300

470 pF

33

COL V+REF

RMGSGF6 5 LT1431

IC1

7

8

1 3

24k

MMBTA56LT132

++

VIN 18 TO 72V

MMBTA06LT1

A programmable reference, IC1, and a bias-capacitor network control the on/off cycling of IC2’s step-up controller during a short-circuit fault condition.

.I

VC

T

CHARGE

THRESHOLD ONTURNBIAS

DELAY ONTURN

−

−

×=

F igure 1


ideasdesign

approximately 400 msec. You can pro-duce shorter turn-on delays byreducing the value of the bias ca-pacitor or increasing the bias current. Ifyou increase the bias current, you mustscale the transistors according to theirpower-dissipation ratings.

Figure 2a shows the bias-capacitorvoltage and the output of the forward-converter voltage during turn-on. Whenthe bias capacitor charges to the turn-onthreshold voltage of 12V set by IC

2, the

output turns on and the bias capacitor’svoltage dips to 11.5V, which is the levelthat the overwinding sets. Figure 2bshows the bias capacitor and output volt-age in cycling mode during a short-cir-cuit fault. IC

1sets the constant current,

which charges the bias capacitor to theturn-on threshold, and IC

2starts up.

However, the overwinding generates novoltage because of the short at the out-put. And because IC

2’s quiescent current

is greater than the charge current, thebias capacitor discharges. Dischargingthe bias capacitor to less than the UVLOthreshold shuts down IC

2. This charging

and discharging cycle repeats until youremove the fault.

You can calculate the restart time us-ing the following equation, where V

RUN

equals the turn-on threshold set byRUN/SHDN:

When implementing a cycling type ofshort-circuit protection, a constraint ison the maximum capacitive load forwhich the power supply starts. The ca-pacitive load depends on the short-cir-cuit current and the threshold voltage atwhich the overwinding back-feeds thebias supply. The output rise time of theLT1680 must be less than the holduptime that the hysteresis and the bias ca-pacitor provide.

You can calculate the start-up time us-ing:

where

You can calculate the hold-up time using:

where IRUN

is the current necessary tostart up IC

2. The start-up time must be

less than the hold-up time for the powersupply to start. (DI #2414)

The output turns on when the bias capacitor reaches 12V (a). During a short-circuit fault, the biascapacitor continually charges and discharges until you remove the fault (b).


.I

)VV(C

T

CHARGE

UVLORUNBIAS

RESTART

1×=

,II

VC

T

LOADSHORT

THRESHOLDOUT

RISE OUTPUT

1

×=

.V

VV

V

CC

OUTULVO

THRESHOLD

×=

,I

)VV(C

T

RUN

UVLORUNBIAS

HOLDUP

1×=

VBIAS CAP

(2V/DIV)

VOUT

(2V/DIV)

(a)

TIME (100 mSEC/DIV)

VBIAS CAP

(2V/DIV)

VOUT

(2V/DIV)

(b)TIME (50 mSEC/DIV)

F igure 2


ideasdesign

Perhaps the most elementary ruleof control-loop design theory is thatfeedback-loop performance is fun-

damentally linked to the careful choice —and stability—of loop gain. Insufficientloop gain leads to poor setpoint accura-cy. Too much gain can induce feedbackinstabilities, such as overshoot, ringing,and, ultimately, oscillation.Therefore, the greaterthe accuracy you expectfrom a control system, themore critical maintainingnear-optimal loop gain be-comes. Precision temperature-control loops are no exception.Given the aforementioned tru-isms, it’s surprising that the fol-lowing rule of designing high-precision thermostats receivesso little notice: The thermaloutput (which is power, theprimary feedback parameter)from a resistive heater is pro-portional to the currentsquared. In Figure 1, Curve Aillustrates this elementary rela-tionship. Therefore, the overallthermostat loop gain is notconstant but is instead propor-tional to heater input current. It conse-quently varies wildly in response tochanges in ambient temperature and oth-er factors that impact heat demand. The

result is that it becomes more difficult tochoose suitable loop parameters. The cir-cuit in Figure 2 (pg 114) remedies thesedifficulties by inserting an analog square-root circuit ahead of the heater-drive cir-cuit.

The circuit stabilizes the temperatureof liquid-nitrogen-cooled solid-state in-

frared lasers in an airborne spectrometer.The cryosensor diode, D

1 (2 mV/K), sens-

es laser temperature and drives the PI(proportional-integral) control circuitcomprising error amplifier IC

1Cand er-

ror integrator IC1B

. Q1

converts the re-sulting feedback correction voltage to acurrent-mode signal and applies the sig-nal to the LM3146 transistor array, IC

4.

The array generates the square-root func-tion. Analog aficionados will be quick topoint out that using IC

4is not the most

accurate way to approximate a square-root curve. However, this method is ade-quate for making the feedback linear andstabilizing loop-gain stabilizing the loopgain. In operation, array transistors IC

4A

through IC4C

combine the current, I1,

from Q1

with the reference current (IREF

)to produce a logarithmic control voltageproportional to log(I

1•I

REF)/25log

(=I1•I

REF). The inherent matching of

transistor parameters in the IC4

mono-lithic array results in an IC

4Ecollector

current of approximately =I1•I

REF. The

IC3B

-Q2

heater-driver cir-cuit subsequently ampli-fies IC

4E’s output current

by a factor of 8450 and ap-plies the amplified currentto the laser-cryostatheater.

Figure 1 shows five rel-evant curves. A is the un-compensated I2R heatertransfer function. B is theideal square-root func-tion. C is the square-rootapproximation from theIC

4 array, which you cal-

culate assuming transistorbetas of approximately100. D is the product of Aand B and represents theideal compensated (lin-ear) loop-gain lineariza-tion with constant loop

gain. E is the product of A and C and isthe achieved loop-gain linearization. Thenet result is a linear relationship betweenthe control circuit and heater outputsand a consequent optimization of thecryostat’s steady-state and dynamic sta-bilities over a range of ambient-heatloading. Without IC

4, a gain setting ade-

quate for setpoint stability at low heaterpowers is likely to be excessive and pro-duce overshoot or oscillation at highheater powers. (DI #2417).

HEAT

HEATER-CONTROL INPUT

D=IDEAL LINEAR RESPONSE.

E=A3C=ACHIEVED RESPONSE.

A=I2 R=UNCOMPENSATED R

ESPONSE.

B=IDEAL =

I.

C=IC4 APPROXIM

ATION TO =

I.

F igure 1

Square-root function improves thermostatW Stephen Woodward, University of North Carolina, Chapel Hill, NC

Multiplying the uncompensated square-law response (A) by the square-rootcurrent response (C) from IC4 yields a linear response of heat versus heater-control output.

Square-root function improves thermostat ..................................113

mC detects transmission rate of RS-232 interface ......................................114

Current sensor measures 0 to 500A........................................................118

Safely swap SCSI disk drives ....................120

SSB modulator covers HF band ..............122

Switched-capacitor IC forms notch filter..........................................124




ideasdesign

RS-232 is the most common serialinterface in the PC world. Most RS-232 interfaces communicate with

the receiver at a fixed transmission rate,such as 9600 baud. But what happens ifthe transmitter operates with differenttransmission rates? Different transmis-sion rates require the receiver to detectthe rate and adjust the software to thenew communication speed. The follow-

ing description of how a receiver detectsthe transmission rate of an RS-232 inter-face does not describe the implementa-tion of a receive-and-transmit routine.Instead, it describes a system consistingof a transmitter and a receiver. The trans-mitter (for example, a PC) transmits acharacter to the receiver. The receiver, alow-cost mC, detects the transmissionrate and adjusts its software according to

the new rate. The theory of implementa-tion is simple.

The transmitter sends a calibrationvalue to the receiver. The receiver meas-ures the time to receive the bits of the cal-ibration value. Based on this measure-ment, the receiver calculates thetransmission time of 1 bit. The methoduses this time for the baud-rate genera-tor. The trick is to measure the time of the

mmC detects transmission rate of RS-232 interfaceby Thomas Schmidt, Microchip Technology, Chandler, AZ

VHVH

2.49k*6.95V

100k*

14k*

12V

10k*

21

1

11

8

44

3

2

3

31

2 4

V2

LM399

LF4125k

5k

150k*

15V

GAIN RESET

4.7-mF METALLIZEDFILM

1M1M 1M* 75k

2N5087Q1

2k*

1.0k* 49.9k* 49.9k*

9

10 86

57

0.001 mF

0.01 mF0.01 mF

IC1B

13

1214

1.0k*

0.1 mF

+F

2F

+S

2S

0.1 mF

1.0k*

249k*33k

D1IC1A

IC1D

LT1004-2.5

HEAT~15V

0 TO 1.7A=0 TO 45W

VH

100 mF AT 35V

8.45k*8.45k*

6

57

Q2TIP127

13W

3.3kIC3B 11

9 8

6

12

11.3k*

5+14+2

1 mA(IREF)

3

714

1312

10

CA3146

1C4A,B

1C4D

1C4E

SQUARE-ROOTER

FUNCTION

7815T

OUT

GND

IN

VH

100 mF AT 35V100 mF AT 16V

15V28V AT 2A MAXIMUM

VHRETURN

THERMALCOUPLING

TEMPERATURE SET

FINE COARSE

1

2

1

2 1

2

1

2

1

2

1

2

CRYOSENSOR

80 mA TO 1.7A

I1

0.01 mF

IC4C

NOTES: *1% METAL FILM.IC1A THROUGH IC1D=LTC1053.

IC1C

IC3A

+

+

+

HEAT SINK 15W MINIMUM

F igure 2

The logarithmic response of transistors IC4A through IC4C results in a square-root function for the heater-control voltage.


ideasdesign

incoming bit stream and calculate the av-erage time to receive 1 bit. This imple-mentation of an autobaud routine as-sumes that the receiver knows the bitsequence of the calibration value and thatthe receiver knows when to calibrate. Thetechnique uses a PIC16C54B mC. The mCconnects to a PC via a MAX232 chip. ThePC sends the calibration character to themC. We chose the ASCII value of “?” be-cause of the bit sequence (00111111).The autobaud routine measures the timeto receive the ones in the bit stream andthen divides the time by six. The result isthe time the routine takes to receive ortransmit 1 bit.

Because the PIC16C54B has no hard-ware USART, a software routine meas-ures the timing of the bit sequence. List-ing 1 gives the source code of theautobaud routine. The calibration char-

acter contains one start bit, one stop bit,and no parity bit. For time measurement,the technique uses a 16-bit counter,which provides a range of transmissionspeeds. In the first part of the routine, thesoftware initializes the counter and anautobaud-status register, AUTOB_STA-TUS. The register stores informationabout whether the incoming signal is tooslow or too fast for the autobaud routine.You can use this information to checkwhether the calibration process is suc-cessful. After the initialization, the auto-baud routine looks for the start bit, whichis a logic-one-to-zero transition.After de-tecting the start bit, the autobaud routinelooks for the reverse transition. Follow-ing detection of this transition, the rou-tine starts measuring the time, using the16-bit software counter. The software in-crements the low byte of the 16-bit

counter until the counter overflows.When an overflow occurs, the high

byte of the 16-bit counter increments byone. This process continues until eithera change from logic one to zero occursor the high byte of the counter overflows.In either of these cases, the routine sets aflag in AUTOB_STATUS to indicate thatthe incoming signal is fast or slow. Oth-erwise, the software calculates the trans-mission time of 1 bit. This time generatesthe baud rate for the transmit or receiveroutine. These routines need the trans-mission time of 1 bit either for generat-ing a delay for bit sampling or for bittransmission. The software calculates thetransmission time for 1 bit by dividingthe measured time by the number oftransmitted ones in the calibration value.In the case of the calibration value “?,” it’snecessary to divide the measured time by

LISTING 1—RS-232 TRANSMISSION-RATE-DETECTION ROUTINE


ideasdesign

The simple circuit inFigure 1a cansense both low

and high current levels with-out low sensitivities or lossof accuracy either at the lowor the high end of the scale.The circuit is useful for dis-cerning either low or highcurrents in noisy environ-ments.

The circuit comprises acurrent mirror formed bycomplementary pair Q

1and

Q2

and the feedback provid-ed by Q

3. When a current I

flows through RS, the voltage

at the emitter of Q2

increas-es. The voltage at the base ofQ

3 then increases, which in-

creases the current, IEQ3

,through Q

3’s emitter. This

process continues until thecircuit restores its equilibri-um by positioning Q

2at the

same operating point as Q1,

which is working as a diode.Consequently, the followingrelationship holds:

I•RS5I

EQ3•R

1.

Therefore, Q3’s emitter

delivers a current propor-

tional to the currentthrough R

S. Further, be-

cause Q4

also works as adiode, Q

5has to work at the

same operating point as Q4

so that the current that thecollector of Q

5delivers is

also proportional to I. Thecollection of series diodesprovides the current-to-voltage converter in loga-rithmic scale. Figure 1bshows the dc transfer func-tion, which is the outputvoltage, V

OUT, versus the

current through RS.

It is important to usecomplementary pairs forQ

1- Q

2and Q

4-Q

5because

the operating point of eachtransistor in the pair shouldbe the same, even if temper-ature varies within itsunions. The circuit useslow-power passive compo-nents except for the 5-mVresistor R

S, which is manu-

factured with calibratedwire of well-known ohms/meter characteristics.

(DI #2405)

100k

R1200

RS, 5

200

100k

2N3810

Q4

Q32N2222

2N2060

Q5

VOUTVSUPPLY12V

1021N3600

Q1 Q2

ICURRENT TO BE SENSED

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

00 100 200 300 400 500

INPUT CURRENT (A)

OUTP

UT

VOLT

AGE

(V)

(a)

(b)

F igure 1

A simple current sensor (a) can measure currents of 0 to 500A with a loga-rithmic output (b).

Current sensor measures 0 to 500AJose Carrasco, Universidad de Valencia, Department Electronica, Valencia, Spain

six. Dividing by six entails shifting the 16-bit counter/register three times to theright while drawing zeros from the left.After the division, the routine divides thebit time by two, to calculate the trans-mission of half a bit. This time figureserves in the receive routine to place thebit sampling in the middle of a bit. Thedivision by two entails a simple shift ofthe 16-bit counter by one position to theleft. The program stores the results of thisoperation in two registers: AUTO-HALF_LOW and AUTOHALF_HIGH.

Once the program completes this cal-culation, it’s necessary to adjust the trans-mission time of 1.5 bits to the softwareoverhead. This adjustment involves sub-tracting the number of instruction cyclesit takes to execute either the transmit orthe receive routine. After the subtraction,the software verifies whether the result issmaller than zero. If so, the incoming sig-nal is too fast, and the routine sets an er-ror flag in the AUTOB_STATUS register.After the adjustment, the software veri-fies whether the incoming signal is too

fast by verifying that the value of the 16-bit counter is zero. If the incoming sig-nal is not too fast, the autobaud routinereturns to the operating system. Listing1 is available for downloading fromEDN’s Web site, www.ednmag.com.Click on “Search Databases”and then en-ter the Software Center to download thefile for Design Idea 2418. (DI #2418).



When you insert an SCA2 (single-connector attach) driveinto a live backplane, the

power supply’s bypass capacitors in thedrive can draw huge transient currentsfrom the backplane’s power bus as theycharge. The transient currents may causepermanent damage to the connector pinsand glitches in the system supply, there-by causing other boards in the system toreset. A viable option for solving thisproblem is to slowly increase the supplyvoltage as the drive mates with the back-plane. According to the SFF8046 specifi-cation, an SCA2-drive connector shouldhave a 5V precharge pin, allowing pre-charging to occur before the voltage pinsmake contact (Reference 1, Figure 1). Asimple method for providing theprecharge voltage is to use a power resis-tor from the 5V line to the precharge pin.However, after the precharge cycle com-pletes and before the 5V pin mates withthe precharge pin, some drives draw asmuch as 1A of load current. The voltagedrop across the power resistor preventsa full precharge and results in a glitch inthe 5V backplane supply when the pow-er pin finally mates.

Figure 2 shows a solution to the 5V-precharge problem, using an LTC1422hot-swap controller and using an LT1490as a comparator. The output capacitor,C

1, charges to 4.3V (5V2V

DIODE) through

R2and D

1. IC

2A’s output, Pin 1, is low, and

Pin 7 is high. When you insert the driveand it mates with the 5V precharge-drive1 pin, the drive pulls the voltage on C

1to

ground. This action forces IC2A

’s Pin 1 toswitch high, thereby turning on theLTC1422. The load current then startsramping up. At approximately 1A, thevoltage drop across R

1is sufficient to trip

IC2B

’s output, Pin 2, low, thus keeping theLTC1422’s On pin high. Q

1’s source volt-

age rises to 5V, and the cathode of D3

(5Vprecharge-drive 1 pin) rises to 4.7V. Re-ducing or increasing the value of C

2can

shorten or lengthen the output-voltageturn-on time, respectively. When you ful-ly insert the drive, the 5V line mates withthe 5V precharge-drive 1 pin and reversebiases D

3, allowing the output voltage to

jump from 4.7 to 5V. The load currentthrough Q

1drops to zero, thereby tog-

gling IC2B

’s Pin 7 high and Pin 1 to a lowstate. This action shuts off the gate driv-er in the LTC1422, and the chip powersdown. The output on C

1 falls to 4.3V, and,

as soon as Drive 2 mates with the 5Vprecharge-drive 2 pin, the LTC1422 pow-ers up, providing a controlled ramp-upoutput voltage. The process repeats fordrives 3, 4, and so on. (DI #2419).

Reference1. SFF Committee, SFF8046 specifica-

tion for 80-pin SCA-2 connector for SCSIdisk drives, Revision 2.7, Oct 3, 1996.


ideasdesign

BACKPLANE

LTC1422/LT1490PRECHARGE

CIRCUIT36

75

76

35

34

36

7576

35

34

5V PRECHARGE DRIVE 1

5V 5V

LONG PIN

LONG PINSHORT PIN

SHORT PIN

LONG PIN

SCA2CONNECTOR

SCA2 DISK DRIVEF igure 1

The SFF8046 specification for the SCA-2 connector in SCSI disk drives calls for a 5V precharge pin,allowing precharging of capacitors to take place before the voltage pins make contact.

_

+

_

+

VCC

IC1

SENSEON

TIMER

GND

GATE

FB

RESET

LTC1422

1

2

3

4

8

7

6

5

12

3

5V IN5V PRECHARGE

DRIVE 1

5V PRECHARGEDRIVE 2

5V PRECHARGEDRIVE 3

D3

D4

D5

R51k

R10.03

R35.1

C40.33 mF

C60.1 mF

C50.1 mF

C10.01 mF

C30.1 mF

C20.1 mF

IC2ALT1490

IC2BLT1490

R45.9

R210k

Q1MBRS5206L

D11N4148

D21N4148

MBR1060

MBR1060

MBR1060

GND

7

4

85

6

F igure 2

A hot-swap-controller IC and a comparator provide a controlled ramp-up of the MOSFET’s gate voltage and, consequently, the output voltage.


Safely swap SCSI disk drivesBy Ajmal Godil, Linear Technology Corp, Milpitas, CA


ideasdesign

In a previous Design Idea (“Modula-tor draws just 5 mA at 2.7V,” EDN,June 5, 1997, pg 111), a phasing net-

work combines with a MAX2452 modu-lator to form an single-sideband (SSB)modulator that accepts a 300- to 3000-Hzbaseband signal and generates an SSB-modulated signal in the VHF range. Theauthor alludes to the possibility of im-proved performance if the modulator ICuses differential drive. Indeed, such per-formance is possible, but you need no ad-ditional components; in fact, you canachieve the improvement with a simplercircuit (Figure 1). The phasing networkcomprises four resistor chains intercou-pled with a number of capacitors. Thesignals from the first and third chainssubtract to form the quadrature (Q) sig-nals. You can effect the subtraction byfeeding the signals from the first andthird chains directly to the I inputs of theMAX2452 and feeding the signals from

the second and fourth chains directly tothe Q inputs of the IC. In the aforemen-tioned Design Idea, the signal into thephasing network derives from two opamps that you connect as differentialbuffers. In this approach, you need nobuffers; the circuit uses ac coupling forthe I and Q signals.

The circuit in Figure 1 operates in the3- to 30-MHz band. This band uses mostSSB communication, because it is diffi-cult to achieve frequency stability (bet-ter than 6100 Hz) at higher bands. Themodulating (voice) signal enters thephasing network through C

1. R

1, R

2, and

R3

provide dc bias, which routes throughthe network to buffers IC

1and IC

2. C

2

provides a good ac ground. The outputbuffers allow a tenfold increase in thechain resistors, to 120 kV. This increaseallows a tenfold reduction in capacitorvalues and is an advantage of surface-mount construction. Phase reversal of ei-

ther the I or Q differential pairs allowsyou select between the upper and lowersideband. IC

3provides the selection func-

tion. The modulated signal drives thetank pins of the IC, via a 1-to-1 isolationtransformer. This signal has twice the de-sired carrier frequency. The IF outputsare differential and have a relatively highimpedance.You obtain the desired single-ended, low-impedance output by usinga 1-to-1 isolation transformer and a two-transistor circuit. Q

1must have base-col-

lector capacitance low than 1 pF. R4

inparallel with this capacitance defines thecorner frequency for the buffer. The cir-cuit provides more than 45-dB carrier re-duction through the 3- to 30-MHz range.(DI #2420).

SSB modulator covers HF bandBy Israel Schleicher, Bakersfield, CA

CA

CA

C10.1 mF

R220k

R347k

R115k

C210 mF

CB CC CD CE CF

CA

CA

CB CC CD CE CF

2+

2+

2+

2+

3

3

3

3

4

4

4

4

8

8

2

22

5

5

6

6

7

76V

6V

6V

6V

6V

10k

10k11

100

100

1 mF

0.1 mF

0.1mF

1 mF

0.01 mF

1 mF

1 mF

8

7

6

6

5

5

5%FILM

MAX4528IC3

MAX2452IC4

IC3

VCC

SIDEBANDSELECT

IEN

GND

I

Q

Q

14

117

152

10-TURN, BIFILAR #34 AWG ON FT-23 TOROID MATERIAL #43 (FAIR RITE)

22FC1VP-P

200 pF

200

T2

T1, SAME AS T2

2N3904

2.7k 470

100 SSBOUT

2N3904

MPSH10

47

1k

R410k

SHIELD

IC1

Q1

IC1

NOTES:UNLESS OTHERWISE NOTED, ALL RESISTORS=121k, 1%.CA=4.7 nF, CB=3.3 nF, CC=2 nF, CD=1 nF,CE=560 pF, CF=470 pF; ALL ARE CERAMIC ORSTACKED FILM 2%.IC1 AND IC2=MC33182.

MOD IN 3VP-P300 TO3000 Hz

6V

A B C D E F

A B C D E F

R

R

R

R

+

IC221

IC221

21

21

1 16

8 9

1

F igure 1

An RC network, three ICs, and a handful of discrete components provide an efficient SSB modulator for the HF band.



ideasdesign

You can use a switched-capacitorlowpass filter (LPF) to imple-ment an inexpensive notch

filter (Figure 1a). The internal architec-ture of the IC (Figure 1b) includes sum-ming nodes similar to those nodes thatanalog-signal-processing stages use forfeedback-error generation. The IC low-pass-filters the quantity V

IN2V

COMand

adds VOS

at the output. In other words,

VOUT

5 (VIN

2VCOM

)LPF

1VOS

,

where VCOM

typically equals VDD

/2. Thus,the IC adds common-mode voltage(COM) at the input, and an internal re-sistor divider biases this voltage at mid-supply. For applications that require off-set adjustment or dc-level-shifting, the ICadds an external bias voltage (OS) at theoutput.

To obtain a notch response, you sim-ply apply the input signal to both the OSand IN pins of the IC, so that these twosignals sum at the output (Figure 1a).Frequencies at OS are limited toabout 100 kHz. At low frequen-cies, the output amplitudeequals |V

IN1V

OS|=2|V

IN|.

At the frequency for which thelowpass filter’s phase responsechanges by 1808, the two signalssum to near zero, creating thenotch frequency. The circuit caneasily produce a notch at fre-quencies of 1 Hz to 10 kHz. Athigher frequencies, only the OSsignal passes through to the out-put.

Figure 2a shows the filter re-sponse for a 400-Hz notch and aclock frequency of 47.5 kHz. TheQ is 1.7, and the center-frequen-cy attenuation is approximately 250 dB.Ripple in the passband limits the notchdepth so that the IC’s flat passband in thelowpass configuration suits this applica-tion. The 1808 phase shift occurs at 0.85

fc, giving the response a smooth 26-dB

transition between the prenotch andpostnotch frequencies (Figure 2b). Theusable input bandwidth is f

clk2f

clk/100,

thanks to a 100-to-1 ratio between the fc

and clock frequencies. As with all sam-pling systems, you must take care to avoidinput-signal aliasing.(DI #2416)

OUT

VCC

IN

OS

CLK

COM

GND

(a)

(b)

MAX7410

5V

CLOCK

LOWPASSFILTERS SIN OUT

++

+

OSCOM

1

SHDN

F igure 1

10

100 1000 10,000

0

210

220

230

240

250

260

GAIN (dB)

FREQUENCY (Hz)FREQUENCY (Hz)

PHASESHIFT(%)

9067.5

45

22.50

222.5245

267.5290

100 1000

fCLK=47.5 kHz

(a) (b)

F igure 2

Switched-capacitor IC forms notch filterLuca Vassalli, Maxim Integrated Products, Sunnyvale, CA

Simple connections produce a notch filter response (a). The IC’s internal summing nodes add aVDD/2 common-mode voltage and an externally applied offset voltage (b).


Applying a 47.5-kHz clock to the circuit produces a 400 Hz notch filter with a notch depth of 50 dB and a Qof 1.7 (a). A 1808 phase shift occurs at 0.85 fc (b).




Name

Title

Phone

E-mail Fax

Company

Address

Country ZIP

Design Idea Title





Signed

Date



ideasdesign



141516171819202122232425

12345678910111213

DQ

RST

CLK

1k

1k

1k

9

1

3

5

IC1A

IC1B

IC1C

IC1D8

2

4

6

TO PCPARALLEL

PORT

SCLK

SYN

LDAC

SD_IN

SD_OUT

DCEN

VSS

CLR

AGND BIN-COMP DGND

REFOUT

REFIN

RFOS

VOUT

VDD

SYN

LDAC

SD_IN

SD_OUT

DCEN

VSS

CLR

AGND BIN-COMP DGND

REFOUT

REFIN

RFOS

VOUT

VDD

+

100 nF

47 pF

GNDVI VO

GNDVI

IC2

IC3

IC1F IC1E

VCC OF IC1

GROUND OF IC1

VO

100 nF100 nF100 nF

1

2

31

2

3

12V 5V

5V

78L12ACZ 78L05ACZ1N4148

100 mF25V

16V

0V

13 12 11 10

6 10 32

1

13

14

16

2

1

13

14

16

6 10 3

11 15 12 4 8

11 15 12 4 8

100 nF

12V

12V

OUTPUT A

OUTPUT B7

9

7

9

5

SDin

SDlk

Sync

Ldac

NOTES:IC1=74HC14.IC2, IC3=AD7243.

47 pF

WALLADAPTER

The simple and inexpensive circuitin Figure 1 generates two PC-con-trolled analog reference voltages.

You supply a wall-adapter supply and a

parallel connector, and the circuit isready to run. The circuit uses two 12-bitAD7243 DACs, which require only onesupply voltage. These converters also

include internal references, minimizingthe number of external components.

Simple software uses the parallel portto communicate with the converters. The

PC and DACs generate two simple analog outputsJim Terrade, Clermont-Ferrand, France

F igure 1

Two 12-bit DACs provide two PC-controlled reference voltages.

www.ednmag.com October 14, 1999 | edn 149

ideasdesign

PC and DACs generatetwo simple analog outputs ......................149

Dual 8-bit ADCs provide pseudo high resolution..............................................152

Disturbance simulator checks lines....................................................152

Circuit latches solenoidsat a distance ................................................154

Dual supply suits portable systems ........156

Zener diode and MMICs produce true broadband noise ................................158

Comparator exhibits temporary hysteresis ..................................160


150 edn | October 14, 1999 www.ednmag.com

ideasdesign

two converters connect in series with aconnection of their Sync and Ldac inputs.This arrangement makes it possi-ble for only three wires to drivethe circuit.

The value of N can range from 0 to4095 because the converters are 12 bits.The converters’ internal reference volt-ages are fixed at 5V. To calculate the num-ber N to enter, you can use the equationN5V3(4095/5), where V is the outputvoltage. For example, if V

B needs to be 4V

and VA

needs to be 30 mV, Nb54.0003(4095/5)53276 ($CCC), andNa50.0303(4095/5)549 ($31).

Figure 2 shows how the transmissionoccurs. DQ is the 2’s complement of thereal numbers, Nb and Na, that the PCsends to the converters. The PC sends in-verted data because of the presence of theinverting 74HC14 trigger, IC

1. RST goes

low first to enable the converters. CLKmust also go low because the data inputis active only on the positive edge of theclock signal; the converter reads data bitsonly when CLK goes from a low to highlevel. The transmission starts when thePC sends a 16-bit word—four zeros andthen the 12-bit word—for the secondconverter, IC

3, MSB first. Next, the PC

sends the 16-bit word for the first con-verter, IC

2, MSB first. Niwm RST and

CLK can go high, and the transmissionstops.

If more than two converters are nec-essary, you connect the Sync and Ldacsignals to the other converters and con-nect the SD_IN input to the SD_OUToutput of IC

3. Make sure that the first

word the PC sends is the one for the newconverter.

Because the 74HC14 is an inverter, youhave to consider the following rela-tions—and follow all data-sheet instruc-tions for the AD7243—before readingthe C program that drives the converters:

● RST5Ldac5Sync5Sync● CLK5Sclk● DQ5SdinListing 1 shows the structure of the

standard C program, which you candownload from EDN’s Web site, www.ednmag.com. Click on “Search Databas-

es” and then enter the Software Center todownload the file for Design Idea #2407.(DI #2407)

Transmission begins after RST and CLK go low. Then, the PC sends the 16-bit words for ConverterB and then for Converter A.

HI Z HI Z

RST

CLK

DQ

D15 D14 D13 D12 D5 D4 D3 D2 D1 D0

DQ=NB=$FFCE=1111 1111 1100 1110

NB=$0031=0000 0000 0011 00011111 0011 0011 0011=$F333=NA=DQ

0000 1100 1100 1100=$0CCC=NA

11111 1 0 0 1 1

t

t

t

F igure 2

LISTING 1—STANDARD C PROGRAM



ideasdesign

The simple line-disturbance simu-lator in Figure 1 helps youcheck the immunity of line-

powered devices to line disturbances andnoise; you can build the device from left-over parts found in a junk drawer. Thekey elements are a ballast inductor (L

3)

and a slightly modified glow-dischargestarter (ST

1) from a fluorescent lamp.

Starters for fluorescent lamps usuallycontain a glow-discharge tube togetherwith a noise-suppression capacitor in asmall housing. You must remove the ca-pacitor for this application. Electronicstarters are unsuitable for this simulator.Operation of the circuit is straightfor-ward: When S

1closes, the glow-discharge

starter switches on and off at a randomrate. The abrupt current variations

Disturbance simulator checks linesPeter Guettler, APS Software Engineering, Cologne, Germany

VOUT1

VOUT2

PE

R30.47

R147

S1

L3

ST1

F13A

C14700 pF

C24700 pF R2

47

R40.47

L150 mH

L250 mH

L

FROM AC MAINS(230V)

PE

N

TO UNITUNDER TEST

NOTES:R1, R2: 4.7V, 1W.R3, R4:0.47V, 5W.C1, C2:4700 pF, 250V.L1, L2: 50 mH, 3A.L3, ST1:SEE TEXT.

F igure 1

You can create dirty power lines for testing by using this simple circuit.

Many inexpensive mCs now comewith several 8-bit A/D-con-verter channels. However,

many high-dynamic-range sensors needmore than 8 bits of resolution. The sim-ple technique in Figure 1 provides apseudo-high-resolution result for anyapplication that has a mixture of largelow-resolution signals and small signalsnear zero.

For example, the turning-rate sensor ofa robot autopilot operates in two realms:Either the robot is rapidly turning to anew heading, or it is trying to travel astraight line. When the robot is turning,the least significant bits (LSBs) are mean-ingless because they change too fast forthe system to track them. When the robotis trying to travel a straight line, the LSBsare important, but the most significantbits (MSBs) are all zero.

By using two 8-bit ADC channels forthe same signal, the technique in Figure1 can accommodate both conditions.One channel, which the controller usesfor fast motion, reads the input directlyand adds four 0 LSBs for a 12-bit result.The second channel reads the signal am-

plified by 16 with four 0 MSBs. The am-plification gives this channel the resolu-tion necessary for small-error signalswhile the robot is traveling a nearlystraight line.

The controller first reads the secondchannel and checks for overflow. If nooverflow occurs, the result is the readingplus four zeros for the MSB. If an over-flow occurs, the controller discards thisfirst reading and proceeds to read the firstchannel.

The controller can perform amplifier-offset correction any time the signal is inthe small-signal realm by reading bothchannels, shifting 4 bits, and subtracting.In most cases, this correction is unnec-essary. (DI #2415)

A/DCONVERTER

SENSOR

163

mC

F igure 1

Dual 8-bit ADCs provide pseudo high resolutionDouglas Butler, Imetrix Inc, Cataumet, MA

For a sensor-output signal that is a mixture oflarge low-resolution signals and small signalsnear zero, you can use two ADC channels toachieve a pseudo-high-resolution result.



ideasdesign

The circuit in Figure 1 controls low-cost, latching solenoid valves overlong distances. For example, it can

control one valve 1 km away using twowires and a 12V supply. The circuit pro-vides 700 mA at 12V for the 20 msec nec-essary for latching a solenoid valve. TheCD4538 monostable multivibrator pro-vides an output-pulse width of 100 msec

to 1 sec. The IC consumes 5-nA standbycurrent. The RX

1CX

1and RX

2CX

2net-

work determines the output-pulse dura-tion and accuracy. When the voltage onC

A1reaches 6V, an input trigger occurs,

monostable IC1A

delivers an output pulseto Q

1’s gate, and Q

1sinks the current

needed to open the latching solenoidvalve. When the voltage on C

A1drops be-

low 6V, monostable IC1B

turns on Q2, and

Q2

sinks the current needed to close thelatching solenoid valve. C

1provides pow-

er to the solenoid valve. (DI #2426)

Circuit latches solenoids at a distanceJ Pelegri and D Ramirez, University of Valencia, Spain

CX

RXCX

TR+

TR2RESET

Q

Q

IC1BCD4538

CX

RXCX

TR+

TR2RESET

Q

Q

IC1ACD4538

Q2IRF530

Q1IRF530

D41N4148

D31N4148D2

1N4148

RX1470k

RX2470k

VIN

D11N4007

R1220RA1

10k C14700 mF

CA11 mF

D51N4148

1

2

4

5

6

7

3

1514

12

11

+

2

10

9

13

V+

10M

220 nF

CX1100 nF

CX2100 nF

+ TOSOLENOID

+F igure 1

This circuit can drive a latching solenoid valve over a 1-km distance.

through L3

induce noise at the outputterminals, V

OUT1and V

OUT2.

L1, L

2, C

1, C

2, and R

1through R

4form

a decoupling filter to keep noise fromflowing back into the ac mains. L

1and L

2

must have a 3A current rating. You canwind them yourself, with 40 turns of 1-

mm-diameter magnet wire wound on aferrite rod of 10-mm diameter and 50-mm length. R

1and R

2are 47V, 5W wire-

wound types. You mount all parts in ashielded enclosure. This simple circuitdoes not replace accurate, calibrated testequipment, but it provides a handy tool

for a quick check during development.(DI #2423)




ideasdesign

The primary concern with powermanagement in portable equipmentis to prolong battery life by eliminat-

ing unnecessary energy consumption.The dual-output power supply in Figure1 meets this objective and maintains reg-ulated 5 and 3.3V outputs as long as thebattery or ac-wall-cube voltage or bothare present. The circuit draws batterypower only when the ac source is absent.Switch-over between the battery and thewall cube requires no user intervention,and the circuit imposes no extra diodesor MOSFETs in the battery path. Theswitch-mode regulators deliver as much

as 600 mA at 5V, and the linear regulatorsupplies as much as 200 mA at 3.3V. IC

1,

which contains a switch-mode regulatorand a linear regulator, has separate inter-nal on/off controls that enable its linearregulator to remain on (powered by IC

2’s

output) when its switch-mode regulatoris off.

IC2

is a switch-mode dc/dc converterthat boosts the unregulated 2 to 5V wall-cube output to a regulated 5.1V level.Note that the wall cube’s output variationwould produce excessive power dissipa-tion in a linear regulator. IC

1’s POUT ter-

minal, which can deliver 300 mA at 95%

efficiency, provides a regulated 5V out-put. Thus, when IC

2is producing 5.1V,

IC1’s feedback tells it to stop switching

and wait. IC1

goes into idle mode, draw-ing less than 1 mA of quiescent current,and waits for its output to drop below thesetpoint. Similarly, a comparator in IC

1

(LBN/LBO) tells IC1to shut down when-

ever the ac supply goes off. This shut-down prevents a flow of reverse currentthrough IC

2. (DI #2427)

Dual supply suits portable systemsBudge Ing, Maxim Integrated Products, Sunnyvale, CA

ONB

TRACK

GND

REF

LBP

LBN

LBO PGND FBLDO

LDO

FB

ONA

OUT

POUT

CLK/SEL

IC1MAX1705

3V

`

`

22 mF

10 mH

100k

MBR0520L

5V 600 mA

`

220 mF

100 mF

22 mH

400k

100k

0.1 mF

22 mF

0.1 mF

68 mF

0.33 mF

3.3 V200 mA

1N5817AC

AC/DCRECTIFIER

2 TO 5V

IC2MAX608

SHDN

REF

AGND GND

OUT

FB

CS

EXT

165k

355k

100k50k

`

`

68k

22k

MMFT3055ELT

0.05

150k

+

+

F igure 1

This energy-efficient dual supply works from either an ac supply or a battery.



ideasdesign

Abroadband source of white noisecan be useful for measur-ing and testing communi-

cations equipment. The source in Figure1 is simple and produces a large noise sig-nal at its output terminals. The circuitcomprises a zener diode and a few am-plifying stages. The breakdown occurringin the zener diode is the true source ofbroadband noise in this design. Thisprocess is truly broadband because a sub-stantial amount of noise is measurable atfrequencies higher than 2 GHz.

The circuit ac-couples the zener diodeinto the first amplifier stage, and subse-quent stages build up the zener diode’stiny noise voltage. The amplifiers—theMAR6, MAR3, and ERA5 (Mini-Cir-cuits, www.minicircuits.com)—aremonolithic-microwave ICs (MMICs).The total voltage gain of approximately58 dB is high enough to produce an out-put voltage of approximately 224 mVrms at the 50V terminating load, whichis equivalent to approximately 0 dBm.Each amplifier in the chain has a com-pression point 1 dB higher than that of

the previous amplifier. Good amplifierlinearity is important to ensure that theoutput signal has a Gaussian probability-density function. The 1-dB compressionpoint for the last amplifier in the chainis more than 18 dBm to ensure that theamplifier operates in the linear mode.

From observations and measure-ments, it appears that the noise level ofthe avalanche-type breakdown diodesprevails over the noise based on the tun-nel effect, and this noise level increaseswith the zener voltage of the diode. Thefrequency spectrum of the noise signal

Zener diode and MMICs produce true broadband noiseLukasz Sliwczynski, University of Mining and Metallurgy,Institute of Electronics, Krakow, Poland

A 24V zener diode and a series of MMIC amplifiers create a broadband noise source.

14 13 10 7 6 1

2 4 5 8 3

TL497

78L05

10 nF

100 mF180 pF

4.710 mH

33k

1.24k

1.24k470 mF35V

1 nF

1 nF

1 nF

1 nF

100 mF

1 nF

~34V

FERRITE BEAD

FERRITE BEAD

FERRITE BEAD

FERRITE BEAD FERRITE

BEAD

R1500

C31.8 pF

R282.4

C41.8 pF

C210 nF

C547 pF

C610 nF

120 12

12

510

180

12V

12

75

ERA5MAR3MAR6

330 pF

24V

C1

OUTPUT

F igure 1

A power-density spectrum of the noise source shows a flat spectrum with an accuracy of 661 dBfrom 20 MHz to 1 GHz.

F igure 2

2302dBmREFERENCELEVEL

NOISE-SOURCEPOWER DENSITY

POWER-DENSITY SPECTRUM (180 MHz/DIV)

NOTE:RESOLUTION=300 kHz.


ideasdesign

Noise and interference can be sig-nificant problems when youtransform a signal from a

sine wave to a square wave. When thesine wave crosses the reference level, acomparator can exhibit uncertainty, orjitter. A common method to eliminatecomparator uncertainty is to introducepositive feedback by using a resistor di-vider at the comparator’s output. The

drawback of this method is that the re-sulting hysteresis produces an offset that’sa function of the state of the compara-tor. With an asymmetric output, the off-set of the comparator’s input is alsoasymmetric. The result is asymmetry in

Comparator exhibits temporary hysteresisVictor Axenenko, CSRI, St Petersburg, Russia

VCC

VOUT

LM301VIN

T=1 mSEC

V`

1

`

C1 0.01 mFR1

8.2k

R21.6k

F igure 1

Replacing a resistor by a capacitor eliminatesasymmetry by providing “temporary hysteresis.”

is independent of the zener diode’s volt-age value, although a higherbreakdown voltage typicallymeans lower bandwidth. Using a zenerdiode with a 24V breakdown voltage forthe circuit in Figure 1 allows the designto produce a 10-dB-greater output signalthan a design that uses a 9.1V zenerdiode.

A switching regulator, the TL497, andassociated components provide the sup-ply voltage for the zener diode; a 12Vsource supplies power for the rest of thecircuitry. An additional linear regulator,the 78L05, supplies current to the zenerdiode. Changing the value of the currentthrough the zener diode by trimming R

1

allows you to obtain a flat frequencyspectrum from the source. You can in-crease the current to some value to findan optimum point for which the noisespectrum is flat and the noise level is ashigh as possible. For this design, the op-timum current is approximately 21 mA.Increasing the current beyond this opti-mum point is not recommended becausefurther increases cause a decrease of theoutput signal. Figure 2 is a plot of thenoise-power-density spectrum, meas-ured with a spectrum analyzer. In the fre-quency range of 20 MHz to approxi-mately 1 GHz, the spectrum is flat withan accuracy of 61 dB, and the 3-dBbandwidth is approximately 10 MHz to1.35 GHz. The probability-density func-tion measured for 107 samples has thewell-known Gaussian shape (Figure 3).

The calculated rms value from the his-togram differs slightly from the power-measurement value; this difference stemsfrom the limited bandwidth of the sam-pling gate used to acquire the samples.

To achieve a flat power-density spec-trum of the noise in the low-frequencyregion, some spectrum whitening is nec-essary because of the existence of 1/f-typenoise. This circuit achieves the necessaryfrequency shape of the amplifier gain us-ing properly chosen values of couplingcapacitors between amplifier stages—C

1,

C2,

and C6—and by using a correcting

network before the last stage—C3, C

4, C

5,

and R2. The values of all frequency-shap-

ing components were chosen experi-mentally while observing the power-den-sity spectrum on the analyzer screen.

To obtain good performance from thecircuit, you must obey all RF design rules.In particular, keep the pins of the zenerdiode as short as possible and locate alldecoupling capacitors near the MMICamplifiers. Screening the entire circuit isalso recommended. (DI #2406)

The probability-density function has a Gaussian shape, and the calculated rms value is 192.1 mV.


NORMALIZED FREQUENCY(31023)

NOISE VOLTAGE (mV)

F igure 3

the desired rectangular output signal.You can eliminate this draw-back by creating a “temporary-hysteresis” characteristic. You create thischaracteristic by substituting a capacitorfor one of the positive-feedback resistors,as in Figure 1.

When the comparator’s outputswitches, the voltage step transfers to thenoninverting input through C

1. When

the comparator’s output switches froma high level,V

H, to a low level, V

L, its out-

put transistor saturates. C1, initially

charged to VH

, begins to dischargethrough R

1. The noninverting-input sig-

nal, V+, rises exponentially from its ini-

tial value (VH2V

L) to 0V with a time

constant T1=R

1•C

1 (Figure 2). When the

comparator’s output switches from VL

toV

H, its output transistor switches off. C

1

charges through R1

and R2

and creates avoltage step V

+5(V

CC2V

L)•R

1/(R

11R

2)

at the noninverting input. V+

then de-creases exponentially with the time con-stant T

25(R

11R

2)•C

1. Note that the hys-

teresis is present only in the timeintervals defining the time constants, T

1

and T2. Note also that upon termination

of transients, the signal V+

on the com-parator’s noninverting input in bothcases is equal to 0V (if T

1,0.1T and

T2,0.1T, where T is the input signal’s

period). For maximum symmetry, you

should select R1..R

2. (DI #2425)


ideasdesign


The feedback capacitor in Figure 1 provides a step voltage to the noninverting input each time thecomparator switches.

F igure 2


INPUT “2”

INPUT “+”

OUTPUT

0.0 0.4 0.8 1.2 1.6 t/T

The quest for low standby power isa challenge for switch-mode-power-supply (SMPS) designers. You can

split the definition of “standby” into twofacets. In “no-load” standby, such as in afully charged battery, output-power de-mand is nonexistent. In “light-load”standby, such as in a TV set awaiting a re-mote-control command, internal cir-cuitry has turned off most of the power-hungry blocks, but some mC activity stilltakes place. The design in Figure 1 coversboth standby facets with a simple solu-tion. Figure 1a depicts the way you couldachieve the regulation using a classic op-toisolated supply that uses a mem-ber of the UC384X family. Whenthe output load decreases, the LED biasraises Pin 2 (the FB pin) and demands alower peak current. At no load or lightload, the PWM IC tries to reduce the dutycycle as much as possible. Unfortunate-ly, high-frequency limitations lead tocompromised performance at the lowestduty cycles, and the circuit can waste asmuch as 1.5W with a 30W SMPS oper-ating at no load.

One possible solution uses a hystereticregulator but, as you can imagine, thehigh peak currents switched in the audi-ble range make the design of a quiet,medium-power SMPS a difficult task. Anelegant solution would combine the bestof both worlds: normal high-frequencyoperation in current mode and burst-mode operation when the output-pow-er demand diminishes. Figure 1b showshow to apply the method to yourUC384X-based design by simply addinga low-cost comparator. In nominal-pow-

er operation, the voltage on Pin 1 is high-er than the level imposed by the 100-kVpotentiometer’s wiper, and the UC384Xoperates in its normal mode. When theload disappears, the voltage on Pin 1drops to reduce the primary peak-cur-rent setpoint. If you adjust the poten-tiometer for a given peak level, the onlyway to further reduce the power is to stopthe output pulses. The comparator, de-riving its power from the UC384X’s in-ternal reference, biases the pnp transistorand brings the current-sense pin to the

www.ednmag.com November 11, 1999 | edn 169

ideasdesign

Controller IC halves switcher’s standby power..............................................169

Load detector controls power sources ..............................................170

Two-wire interface has galvanic isolation ........................................174

Measure power-on current transients on ac line ....................................176

Generator has independentpulse width, frequency................................178

Customized potentiometers aidamplifier design ..........................................180

Ring your bell; light your light ..................182


(a)

(b)

FROM SECONDARY CIRCUIT

8

7

6

5

1

2

3

4UC384X

FROM CURRENT SHUNT

FROM SECONDARY CIRCUIT

8

7

6

5

1

2

3

4UC384X

FROM CURRENT SHUNT

1

1

22k

100k

100k

MPSA2907

½ LM393

10 nF

F igure 1

Controller IC halves switcher’s standby powerChristophe Basso, On Semiconductor, Toulouse, France

The classic arrangement in (a) reduces no-load standby power; the addition of a comparator (b)cuts the standby power by 50%.

170 edn | November 11, 1999 www.ednmag.com

ideasdesign

Emergency generators normallyoperate when the mainpower source fails. Invert-

ers run continuously (and ex-pensively) even when no load-power de-mand exists. Even unloaded, a me-dium-sized inverter consumes some tensof watts just to keep its fan running (andto make noise). A generator running un-der no-load conditions just wastes fuel.The simple scheme in Figure 1’s block di-agram controls your power source (gen-erator or inverter), switching it off whenno load exists and turning it on when theload needs power. The device is basically

1

1

THRESHOLDAMPLIFIER

DC SOURCE

INVERTER ORGENERATOR

OUTPUT

GALVANICISOLATION

AND LOWPASSFILTER

INVERTER ORGENERATOR

CONTROL

LOADS

F igure 1

Load detector controls power sourcesGiovanni Romeo, Instituto Nazionale de Geofisica, Rome, Italy

Why waste generator power when there’s noload? This simple circuit turns the generator ononly when a load demands power.

level at Pin 8. This action blocksthe output pulses, and the circuitdelivers no power.

The output voltage decreases, and, assoon as the error amplifier’s level cross-es the level at the potentiometer’s wiper,the pulses reappear for another timepacket. In other words, the circuit goesinto burst mode. Thanks to the lack ofhysteresis in the comparator, the outputripple is minimal. However, you mustprevent the UC384X from entering hic-cup mode during the burst-mode oper-ation to preserve good transient re-sponse. Increasing the power-rail bulkcapacitor can prevent hiccup mode. Ifthe circuit enters hiccup mode, the pow-er consumption further decreases but tothe detriment of the transient response.Figure 2 shows how the circuit behavesat different load conditions. By adjustingthe level at the comparator’s inverting in-put, you have the flexibility to make thesupply enter burst mode at a peak valueat which no acoustic noise results. Youcan also select the output level at which

the circuit enters burst mode: a no- orlight-load condition. With a typical 12V,30W flyback supply using a UC3843,measurements reveal an input power of 1.35W at no load (V

IN5100V ac;

RSTARTUP

5100 kV). Adding the compara-

tor reduces the input power to 770 mW.(DI #2436)

F igure 2

Burst-mode pulses reflect a no-load condition (a) and different light-load conditions (b and c).


(a)

(b)

(c)


ideasdesign

24 TO 12VDC/DC CONVERTER

UPSSTART/STOP

DIGITALCONTROL

LINE SENSE

VIN VOUT

VCC

GND

+

+

+

IN

OUT

1k

1k

2N2222RELAY

12

100 mF

100 mF

24V INVERTERBATTERY

1M10k

50k1M1M

1 mF

1k

1k

1k

D5

D4

D3

R1 R2

D1

D2

Q1

OUT

LM7805

100F igure 2

This galvanically isolated generator-control circuit turns on the emergency generator only when the load demands it.

an ohmmeter that monitors the genera-tor resistance of the generator or invert-er output. Usually, the output comesfrom a motor coil or a transformer wind-ing having low resistance. The circuit inFigure 1 can detect any load whose re-sistance is lower than 15 kV. When noload exists, the voltage at the amplifier in-put (the generator’s voltage minus thediode-junction voltage) does not exceedthe threshold, so the relay does not en-gage.

When one or more loads connect tothe circuit, the voltage at the amplifier in-put exceeds the threshold, actuating the

relay and starting the generator or in-verter. When the ac load current flowsthrough the circuit, it keeps the relay en-gaged.When the load disconnects, the re-lay disengages. In operating a generator,you should wire the system to start thegenerator when no line power exists andwhen the load requires power. Figure 2shows a complete schematic. In the no-load case, the voltage source (R

1, R

2, D

1,

and D2) cannot forward-bias Q

1’s base-

emitter junction, because of the voltagedrop across D

3, D

4, and D

5. The junction

becomes forward-biased when a loadconnects to the inverter, and the load cur-

rent flows through the output coil (in-verter or generator transformer). Thehigh-voltage section of the circuit is gal-vanically isolated via the dc/dc convert-er and the optocoupler. An RC lowpassfilter delays the relay’s actuation; it takesapproximately 1 sec for the relay to en-gage after connecting the load and 2 secto disengage after disconnecting the load.(DI #2435)



ideasdesign

Unlike the four-wire SPI, QSPI,and Microwire data-in-terface standards, I2C

and SBBus buses require only two wiresfor data transmission, because they sendand receive over the same wire. The cir-cuit in Figure 1 provides galvanic isola-tion for the two-wire interface. A smalltransformer and a MAX253 transformerdriver (not shown) derive an isolated 5Vrail from the master-side 5V rail. Thedata rate and isolation-barrier voltage inyour application guide the selection ofthe transformer and optocoupler. Thecircuit in Figure 1 uses a Hewlett-Packard 6N138 optocoupler. For moreinformation on component suppliers,see the MAX253 and MAX845 datasheets. The scheme assumes a mP or mCfor the master device, and the current-sink limitation of the processor’s SDAterminal dictates that the optocoupler’sminimum on-state current be less than 3mA. Even so, the optocoupler’s 300%current-transfer ratio (CTR) is adequateto ensure proper operation in this circuit.

The slave side should host an I2C-compatible device, such as the MAX5178-bit DAC or the MAX127 data-acquisi-tion system. The master-side SDA andSCL signals are high when the bus is notin use. The I2C Start condition is typical-ly a high-to-low transition on SDA whileSCL remains low (Figure 2). With SDAlow, current through R

2and the opto-

coupler’s input causes the opto output toproduce a signal of approximately 0.4V

(sum of the opto output and the forward-biased Schottky diode, D

2). Pull-up resis-

tors R1, R

4, and R

6are necessary for I2C

compatibility. After the master addressesthe slave as described, the addressed slaveresponds with a low-level acknowledgebit. The bidirectional SDA line allowsdata transfer in both directions, but theunidirectional SCL line needs only to

conduct signals from master to slave.Data transmission ends with the Stopcondition, in which SDA typically makesa low-to-high transition while SCL ishigh. (DI #2438)

5V 5V

SCL

SCL (ISOLATED)

SDA (ISOLATED)

MASTER SLAVE

SDA

D1

D2

R43.3k

R63.3k

R52.2k

R32.2k

R13.3k

R22.2k

F igure 1

SLAVE ADDRESS BYTE COMMAND BYTE OUTPUT BYTE

MSB

START CONDITION

SDA

SCLLSB ACK MSB LSB ACK LSB ACKMSB

STOP CONDITION

F igure 2

Two-wire interface has galvanic isolationMinh-Tam Nguyen and Martin Baumbach, Maxim Integrated Products, Munich, Germany

A handful of components provides an isolation barrier for the two wires of an I2C transmissioninterface.

This diagram shows the I2C timing protocol for the MAX517 D/A converter.



ideasdesign

For any electronic or electricalsystem, you usually deter-mine the ac-line fuse rating

based on the steady-state current. How-ever, the power-on current surge is animportant parameter in determining thefuse’s I2t rating. The I2t rating is a meas-ure of the energy required to blow a fusein pulsed conditions. Also, in many cas-es, you may find it of value to know theshape of the current surge and its har-monic content. The circuit in Figure 1can help you capture the power-on cur-rent transients in a system. The circuitcosts less than $25 to build. You need aDSO to capture the waveforms. In Fig-ure 1, the neutral line of the equipmentunder test contains a 1V, 12W current-sense resistor. The resistor should be ableto handle10A surge current and 3Asteady-state current. The voltage dropacross the sense resistor drives anISO122P isolation amplifier (Burr-Brown, www.burr-brown.com). Thezener diode and the transient-voltagesuppressor provide overvoltage protec-tion.

A DCP011515DP isolated dc/dc con-verter (also Burr-Brown) generates615V isolated supplies to power the in-put side of the ISO122P. Both devicesprovide more than a 1000V rms isolationcapability. A local supply powers the in-

Measure power-on current transients on ac lineN Kannan, Mediatronix, Trivandrum, India

1

2

6

7

15 (I)

15 (I)

15V

115 (I)

115V

5

15V

AGND

2.2kTO

DSO

32 31

0.01 mF/50V

10V/0.5W (22)

10k 10k

N NE E

POWER GROUND

TO MAINSPLUG

TO EUT(SOCKET)

4.7

7

9

810

15

16

10 mF0.14 mF

10 mF

0.1 mF

0.1 mF

0.1 mF

115 (I)

2.2 nF

4.7

31

32

12

AGND

15V

115V

TVS (P6KE15CA)

4.7 4.7

GI

LL

7815

7915

DCP011515DP

ISO122P

ISOLATIONBARRIER

1V, 12W

470 mF/35V

470 mF/35V

10 mF/35V

10 mF/35V

F igure 1

This simple tester allows you to measure power-on current surges.

A highly capacitive power supply causes a 4A current surge (a) in the power line; an incandescent bulb produces a 1.5A spike (b).

F igure 2

(a) (b)

put of the dc/dc converter and the out-put side of the ISO122P. The filtered out-put of the ISO122P provides the input toa DSO. You use transient-capture modein the DSO to capture the power-on cur-rent surge. Figure 2 shows the waveformsfor:

● A system with a 10,000-mF trans-former/bridge-capacitor filter (Fig-ure 2a). Steady-state rms current isapproximately 0.13A at 220V rms.

● An incandescent lamp (Figure 2b).From the waveforms, you can de-termine the surge’s shape, width,and peak value. You can then usethis information to determine theproper I2t rating for the system fuse.Figure 2a shows a current surge of4A peak, although the steady-statecurrent is only 0.13A. The heavysurge arises because of the large-value capacitor filter and also from

core-saturation effects. Figure 2bshows a turn-on surge of approxi-mately 1.5A for the 60W, 220V in-candescent bulb. Warning: Haz-ardous voltages are present in themains-side circuitry. (DI #2428).


ideasdesign

Generator has independent pulse width, frequencyDarvinder Oberoi, CEDTI, Jammy, India

Acommon circuit in electronics isthe square-wave, astable multivibra-tor (one-shot), which is use-

ful for various purposes, such astiming circuits and audible alarms. Themost common way to generate the de-sired square wave is to use the inexpen-sive 555 timer. The need sometimes aris-es for a square wave with fixed frequencybut variable pulse width or vice versa. It’sdifficult to satisfy these requirementswith a conventional 555-based astablecircuit. Figure 1 shows a modification ofthe basic 555-based astable circuit. Youcan use the circuit to generate stable,variable-pulse-width or variable-fre-quency signals, which are independent ofeach other by means of individual dedi-cated controls. The Pin 3 output of the555 charges and discharges C

1. D

1and D

2

provide individual paths for the chargingand discharging operations, respectively.The two timing potentiometers, P

1and

P2, control the RC

1 time constant during

the charging and discharging cycles.When Pin 3 of the 555 is high, the ca-

pacitor charges through R2(a component

of P1, whose value depends on the wiper

position). When C1charges to two-thirds

VCC

, Pin 3 goes low, and C1

dischargesthrough the combination of D

2, P

2(re-

sistance R1), and P

1(resistance R

3). When

the voltage across C1

reaches one-thirdV

CC, the Pin 3 output again switches high.

The process of alternately charging anddischarging C

1continues; the result is an

output with a desired pulse width andfrequency. Because the forward resistanceof the diodes is negligible, the pulsewidth equates to R

2C

1log(2). The pulse

period (reciprocal of frequency) is

0.693(R1`R

2`R

3)C

1. Thus, the pulse

width is independent of P2’s wiper posi-

tion, and the frequency is independent ofP

1’s wiper position. (DI #2444)

You can independently and noninteractively control pulse width and frequency by adjusting twopotentiometers.

P2, 47kFREQUENCY CONTROL

P1, 47kPULSE-WIDTH

CONTROL

R1

VCC

R3

R2

D11N4148

D21N4148

C10.047 mF

C20.01 mF

15

2

6

4 8

3 PULSEOUTPUT

555

F igure 1




ideasdesign

The circuit in Figure 1 is a model ofan amplifier circuit whosecutoff frequency and gain are

functions of the values of variable resis-tors. A first-order, RC lowpass filter es-tablishes the cutoff frequency, and a tra-ditional noninverting op-amp circuitdetermines the gain. You can add vari-ability and programmability if you usedigitally controlled potentiometers toimplement the variable resistors. The cir-cuit in Figure 2 shows the implementa-tion of the frequency and gain controls.The potentiometer, R, forms a pseudo-teenetwork; along with capacitor C, the po-tentiometer establishes the upper cutofffrequency f

C. Potentiometer R

2is

a three-terminal device that es-tablishes the voltage gain, G

0. The voltage

gain for the circuit is:

G0

is the programmable closed-looppassband gain:

where k2

reflects the proportionate posi-tion of the wiper from one end of the po-tentiometer (0) to the other end (1). Thegain is programmable from 1 to(R

11R

2)/R

1. The fixed resistor, R

1,

limits the circuit’s maximum volt-age gain, a limitation usually necessaryfor accuracy and bandwidth purposes.The upper cutoff frequency f

Cis a func-

tion of the input RC network:

where k1, like k

2, reflects the proportion-

ate position of the wiper from one endof the potentiometer (0) to the other end(1). The dual versions of the XDCP dig-ital potentiometers use the same serialbus with different addresses for the indi-vidual potentiometers.

+

1

RVS

R2

R1

VOUT

C

LOWPASS FILTER NONINVERTING AMPLIFIER

G0 =1+R2/R1.

fC= 12pRC

F igure 1

+

1

VS

R1 k2R2

5V

VOUT

15V

15V

(11k2R2)CONTROL

ANDMEMORY

SCL

SDA

ADDR

C

kR (11k)R

X9418W

5V

F igure 2

+

1

5V

R1

R2

RLOW RHIGH

5V

VOUT

15V

15V

5V

CONTROLAND

MEMORY

SCL

SDA

ADDR

W

X9418W

R45k, 1%

R55k, 1%

R31k, 1%

R1910, 1%

300 pF

3 76

42

LT1220

W

HIGH LOW

10k

10kF igure 3

Customized potentiometers aid amplifier designChuck Wojslaw, Xicor Inc, Milpitas, CA

You can use potentiometers to program an amplifier’s gain and cutoff frequency.

Replacing Figure 1’s potentiometer with digitally programmable potentiometers allows you digital-ly to control gain and cutoff frequency.

You can use the same serial bus to control both the gain and the cutoff-frequency potentiometersin an amplifier circuit.

.j

G

V

V

C

C0

S

0

ω+ωω=

,1k0 and ,RkR

RRG 2

221

210 ≤≤

++=

.1k0 and ,C)Rk(2

1

2f 1

1

CC ≤≤

π=

πω=


ideasdesign

For high-frequency amplifiers, the 10-kV end-to-end resistance of the X9418creates time constants limiting the band-width of the circuit. You can reduce theeffective end-to-end resistance of the po-tentiometers by using two techniquesshown in the high-frequency amplifiercircuit in Figure 3. If you connect thewiper of the potentiometer to a high im-pedance, shunting R

TOTALdirectly with an

external resistor reduces the effective

end-to-end resistance. Resistor R3

changes the effective end-to-end resist-ance of potentiometer R

2from 10 to

0.909 kV. If you do not connect thewiper of the potentiometer to a high im-pedance, you can reduce the effectiveend-to-end resistance by adding external,equal-value resistors, R

4and R

5, from the

wiper to the high and low terminals. Thistechnique, however, creates a poten-tiometer whose taper is pseudolinear andwhose end-to-end resistance varies with

wiper position by approximately 20%.The gain of the amplifier circuit in Fig-ure 3 is programmable from 1 to 2, andthe cutoff frequency is programmablefrom 130 kHz to more than 1 MHz. (DI#2437)

The circuit in Figure 1 provides asimple and inexpensive wayto provide illumination for

a dark doorway. Pressing the doorbellbutton momentarily rings the doorbelland turns on the porch light. The porchlight remains on for approximately 25 secand then turns off. This interval is longenough for a person to find his or her waywhen it’s dark. The system also providessecurity in that anyone pressing the door-bell button is automatically illuminated.The circuit receives its power from thedoorbell system. Pressing the doorbellbutton provides voltage to diode D

1,

which acts as a half-wave rectifier. D1also

acts as a blocking diode to prevent cur-rent from flowing back to the doorbell af-ter you release the doorbell button. Ca-pacitor C

1filters the half-wave-rectified

voltage, and voltage regulator IC1

regu-lates the filtered voltage. The regulatedvoltage supplies timer IC

2, configured as

a monostable multivibrator.Relay K

1activates when you press the

doorbell button. It remains activated un-til IC

2times out, according to the expres-

sion t51•1R1C

2. Diode D

3is a flyback

diode to protect IC2

from the inductivespike K

1generates when it becomes de-

activated. Normally open relay contactK

1Acontinues to power the circuit via

diode D2

after you release the doorbellbutton. K

1Bconnects in parallel with the

porch-light switch to power the porchlight by means of the new circuit. Youmust size the relay contacts to accom-

modate the current requirements of theporch light. (DI #2433)

Ring your bell; light your lightDennis Eichenberg, Parma Heights, OH

IC2555

12V-ACDOORBELL

POWER

DOORBELL

D21N4001

D11N4001

DOORBELL BUTTON

1

2

34

68

PORCH-LIGHT SWITCH

PORCH LIGHT

D3 1N4001

K112V DC

+

+

C1470 mF

35V C22.2 mF25V

120V AC

K1A

K1B

R110M

7812IC1

F igure 1

Scared of the dark? Use this circuit to turn on your porch light when you ring the doorbell.






Name

Title

Phone

E-mail Fax

Company

Address

Country ZIP

Design Idea Title





Signed

Date



ideasdesign



Power consumption and failingbatteries are key issues inbattery-operated applica-

tions. Features in the new generation ofseries voltage regulators address theseconcerns. For example, National Semi-conductor’s LP2951 micropower voltageregulator provides a logic-level outputsignal indicating a low regulated outputvoltage; the IC also has a logic-level inputto shut down the regulator to conservepower. These signals are digital; therefore,they are compatible with mP-based sys-tems. But what about the programmingor controlling the regulator’s output volt-age? A mechanical potentiometer or se-lected resistors are not elegant solutions.You can complete the so-called comput-erization or digitizing of the voltage reg-ulator by using a digitally controlled po-tentiometer to program the regulator’soutput voltage. The circuit in Figure 1 isa wide-range, computer-controlled volt-age regulator with a nominal output volt-age that varies from 1.235 to 14.8V. Theregulator uses a Xicor XDCP X9312Wdigitally controlled potentiometer that,

with its 100 steps, can program the regu-lator with a resolution of 0.136V per step.The output voltage is 1.235V(11kR/910V), where k is a number from 0 to1 and reflects the proportionate positionof the wiper from one end of the pot (0)to the other end (1). R is the end-to-endresistance of the potentiometer.

The XDCP’s programming uses athree-wire bus. The potentiometer isconfigured as a two-terminal variable re-sistor. The regulator’s Error output signalwarns of a low output voltage; you canuse it as a power-on reset. The logic-com-patible Shutdown input signal allows youto switch the regulator on and off to con-serve power. These signals, along withthose you require to program the XDCP,typically connect to the I/O port or the

mP or mC. The potentiometer adds vari-ability to the regulator circuit; its digitalcontrols, which are attached to a com-puter-controlled bus, provide program-mability. For example, an automatedclosed-loop calibration procedure toprogram the regulator saves manufac-turing test time.You can use the circuit asa bias supply; a voltage reference; or a programmable, high-output-currentvoltage source in test-and-measurementapplications. (DI #2442).

Voltage regulator goes digitalChuck Wojslaw, Xicor Inc, Milpitas, CA


5

8

3

4

LP2951

2

1

7

8

0.01 mF3.3 mF

VIN (UNREGULATED)

ERROR

SHUTDOWN

U/D

INC

CS

X9312W

5V

4

910

+

VOUT (REGULATED)

100k

1

10k

7

CONTROLSOUTPUTVOLTAGE

F igure 1

A digital potentiometer adds programmability to an ordinary series voltage regulator.

www.ednmag.com November 24, 1999 | edn 167

ideasdesign

Voltage regulator goes digital ..................167

Supply converts 5V to 148V ..................168

C routine speeds decimal-to-binary conversion ........................................170

Resistor implements half-duplexRS-232 with echo ........................................172

Circuit monitors ac-power loss ................172

RF transmitter uses AMI encoding ..........174

High-voltage regulator is 100% surface-mountable ......................................178



ideasdesign

As the demand for networkingequipment grows, the needarises for a 148V supply that

can power telecommunication lines. Thecircuit in Figure 1 delivers 24W at 248Vfrom a 5V input. One of the biggest chal-lenges in this design is choosing the inputvoltage. Although high-current, 5Vsources are commonly available, lowerinput voltages generally mean high inputcurrents with accompanying low effi-ciency. With a relatively simple topologyand a 5V input source, the circuit in Fig-ure 1 delivers greater than 85% efficien-cy (Figure 2). T

1stores energy during the

on-state time of Q1. Energy transfers to

two stacked 24V outputs to create 248V.C

1charges to a dc value equal to the 24V

input voltage while clamping T1’s leak-

age-inductance spike and providing a

path for input current dur-ing Q

1’s off-state time. This

operation results in con-tinuous input current andthus reduces capacitor rip-ple-current requirements

The reduced input rip-ple current, which is char-acteristic of this topology,demands sensing of theswitch current rather thanthe input current. In thiscase, T

2senses the switch

current, eliminating 400mW of resistor loss with-out using excessive board

space (738 mm). Other additions im-prove the circuit’s efficiency and per-

+

VIN

D11N5235B

6.8V

Q1

VOUT

VIN5V

R151

T2

T1

VFB

S2

BOOST

GND

TG

SW

LTC1624

2 4 3

ITH/RUN

+

+

+

+

+

++

NOTES:T1=COILTRONIC CTX02-14261.EFD20; SIX WINDINGS, EACH 12 mH.T2=DALE LPE3325-A087EES CORE; 1 TO 70, LS=980 mH.RESISTORS= W, 5%.

248V/0.5A

470 mF35VSANYOMV-GX

470 mF35VSANYOMV-GX

4.7 mF30VFILM

4.7 mF30VFILM

MBRS340T3

MBRS340T3

1 nF

15

30 220 pF

IRL3705N

Q3ZTX749

Q2

T2

C1

ZTX649

2N5210Q4

2N5210Q5

1 mF10 mF

1500 mF6.3VSANYOMV-GX

0.022 mF

2.2 nF

36k

12k1M

10.5k1%

8 1

7

6

5

BAV21

0.82

248V

14

F igure 1

95

90

85

0.05 0.1 0.2 0.3 0.4 0.5

OUTPUT CURRENT (A)

EFFICIENCY (%)

5.25VIN

5VIN

4.75VIN

F igure 2

Supply converts 5V to 1148VKurk Mathews, Linear Technology Corp, Milpitas, CA

This circuit uses numerous tricks to boost efficiency to more than 85% in converting 5V to 1148V.

The circuit in Figure 1 delivers greater than 85% efficiencyunder all conditions and greater than 90% for much of its out-put-current range.

formance. The LTC1624’s Boost pin nor-mally provides the internal output driv-er (the TG pin) with a 5.6V regulatedsupply, but TG produces only 4.2V witha 5V input. Bypassing the internal regu-lator by connecting the Boost and V

IN

pins increases Q1’s gate voltage, resulting

in a gain of more than 3.2% in overall ef-ficiency. R

1and D

1keep the Boost pin be-

low its 7.8V rating in the event of an in-put overvoltage condition. The additionof Q

2and Q

3provides an additional 5.5%

of efficiency by speeding transitions andincreasing gate voltage from 5 to 5.3V.This voltage peaking results from excessemitter current as Q

2turns off after

charging Q1’s gate capacitance. Q

4and Q

5

translate the 248V output to the 1.2V

that the feedback pin (VFB

) requires toregulate the output voltage. TheLTC1624’s switching frequency decreas-es with output voltage, thereby reducinginput current during output short-cir-cuit conditions. (DI #2440).


ideasdesign

Aprevious Design Idea (“Programprovides integer-to-binary conver-sion,” EDN, March 2, 1998, pg 110)

describes a C/C11 function that pro-vides integer-to-binary conversion. Thefunction, named cintbin/classicC, imple-ments a conversion in a straightforwardway that defines decimal and binarynumbers in terms of powers. Althoughthis function can be useful for testing oreducational purposes, its low efficiencyprecludes its use in embedded or otherfast applications. The main source of in-efficiency is the use of the pow C func-tion, which requires linking the math li-brary. By carefully rewriting the functionand by directly accessing the binary rep-resentation of the integers in C, you canspeed the conversion by as much as 58times. The rewrite also results in morecompact code, because linking the mathlibrary is unnecessary. Listing 1 shows asimple calling program and two func-tions, fast_d2b and fast_b2d, that imple-ment conversion between decimal andbinary integer representations.

In fast_d2b, the main loop is a for loop,in which the variable, i, accesses the ar-ray, c, sequentially, from 0 to 31. At eachiteration, x, the number to convert, right-shifts by i positions (the >> operator),and the routine extracts its least signifi-cant bit by masking x with the constant1 (the & operator). The routine finally as-signs the result to the ith term of the vec-tor c. The symmetric fast_b2d functionconverts a binary number to its decimal

equivalent. The func-tion performs theconversion through asequence of left shiftsand sums. To com-pare the perform-ance of fast_d2b withthe function classicC, we ran several testson two platforms, both running Unix-like OSs. We used the GNU C compiler(gcc) with and without turning on “ag-gressive optimization” (the O3 flag).Table 1 shows the time to convert the first100 million integers. The Unix timecommand produces the running-timefigure. Fast_d2b is 20 to 58 times faster

than classicC. You can download Listing1 from EDN’s Web site. At the registered-user area, go into the Software Centerand download the file from DI-SIG#2444. (DI #2443).

C routine speeds decimal-to-binary conversionGiovanni Motta, Brandeis University, Waltham, MA



Irix (SGI Indy R5000) Linux (PIII/500)gcc gcc-03 gcc gcc-03

fast_d2b 476 160 80 28classicC 9377 8542 2206 1672

TABLE 1—SECONDS TO CONVERT 100 MILLION INTEGERS

LISTING 1—DECIMAL-TO-BINARY CONVERSION IN C


ideasdesign

Aprevious Design Idea (“Single mCpin makes half-duplex RS-232,” EDN, Aug 5, 1999, pg

118) presented a way to implement half-duplex RS-232 communications withoutecho. Sometimes, an echo is desirable ina mC application.You can obtain the echoby using a single resistor (Figure 1). Youinsert a 5.1-kV resistor between thetransmit and receive pins on the RS-232driver (such as a MAX232). The I/O pinon the mC (RB0 on 14-bit PIC mCs) con-nects directly to the transmit gate on theRS-232 driver. This technique is usefulfor implementing a user interface on aMicrochip PIC for applications in whichyou communicate to the PIC via a termi-nal or a terminal-emulation program.Full duplex is unnecessary with a user in-terface based on user-issued commandsand mC responses, when the mC gener-ates no spontaneous data that wouldmask the user-issued commands. Thecharacter echo is useful in determiningwhether the device is powered up and theRS-232 receiver is active, but an echoalone does not tell you whether the mCis active; the mC must send data.

When the mC is in receive mode, itmakes the input pin a high-impedance

input. All RS-232 data sent to the mC isimmediately retransmitted via the resis-tor that connects the receiver to the trans-mitter. Because the input has high im-pedance, the mC is essentially justmonitoring the traffic on the RS-232 line.When the mC must send serial informa-tion, the mC converts its I/O pin to a low-impedance driver. Anything now sent tothe mC shunts to ground or V

CC(de-

pending on the mC’s output state)

through the resistor and the mC’s driver.The mC ignores data sent to it. The mCnow directly sends data down the serialline. The mC must immediately changethe serial line back to high-impedancemode after transmitting or risk data loss.(DI #2445).

Resistor implements half-duplex RS-232 with echoMatt Bennett, Austin, TX


PIC16C71

18

17

16

15

14

13

12

11

10

1

2

3

4

5

6

7

8

9

IC1

RA2/AIN2 RA1/AIN1

RA3/AIN3 RA0/AIN0

RA4/TOCKI OSC1

MCLR OSC2

VSS VDD

RB0/INT RB7

RB1 RB6

RB2 RB5

RB3 RB4

IC2

1

3

4

5

11

10

12

9

14

7

13

8

2

6

5.1k

C1`

C11

C2`

C21

T1IN

T2IN

R1OUT

R2OUT

T1OUT

T2OUT

R1IN

R2IN

V`

V1

MAX232

F igure 1

The addition of a single resistor provides an echo in RS-232 half-duplex communications.

The circuit in Figure 1 provides asimple, nonvolatile means of moni-toring critical ac-power failures.

Monitoring the power is important insuch systems as heating and refrigeration,in which damage can occur if the ac pow-er goes down for an extended period. Thecircuit in Figure 1 requires little powerfrom the ac-power system. The quiescentbattery current of approximately 5 mA

provides long battery life in this applica-tion. The optocoupler consists of a neonlamp and a photocell. When the ac-pow-er system is active, the neon lamp lightsvia current-limiting resistor R

1. A neon

lamp is ideal for this application becauseof its low power drain. The resistance ofthe photocell in the optocoupler is lowwhen the cell is illuminated and highwhen it’s unilluminated. R

2serves as a

current-limiting resistor for the photo-cell.

IC1A

of the quad two-input NAND-gate Schmitt trigger serves as a buffer forthe optocoupler. The output of IC

1Ais

normally high when the ac power is pres-ent and goes low when a power failureoccurs. IC

1Bis configured as a negative-

edge-triggered, half-monostable multivi-brator. It produces a positive pulse with

Circuit monitors ac-power lossDennis Eichenberg, Parma Heights, OH


ideasdesign

9V

R1

S1

120V AC

SIGMA 30 1T 1-150A 1OPTO 1

1 34

Q1

2N22222

5

6

8

9

12

13

10

11

1k

IC1A

14

C1

IC14093 IC1C

IC1D

R4

D1

1N4001

S1

9V

R21M

220k

R31M

0.1 mF

IC1B

F igure 1

This circuit sets a flag or triggers a visual alarm when the ac-power line fails.

a width of approximately 0.8R3C

1, or ap-

proximately 0.8 sec, whenever the acpower goes down. The output pulsedrives transistor Q

1via the current-lim-

iting resistor, R4, to activate solenoid S

1.

D1

is a flyback diode to protect Q1

fromthe inductive spike S

1generates when it

becomes deactivated. You can use S1

totrigger a flag or to provide a similar vi-sual alarm. The flag remains in position

until you manually reset it to prepare thecircuit for the next power failure. (DI#2446).


Although alternate-mark-inver-sion (AMI) encoding is well-suited for direct-conversion

FM transmission, designers often over-look the technique. AMI, a three-phase,synchronous-encoding technique, usesbipolar pulses to represent logic ones andno signal to represent logic zeros (Figure1). Direct-conversion FM transmission,in which data directly modulates a carri-er, is also known as frequency-shift-key-ing (FSK) modulation. For higher fre-quency transmissions, a PLL usuallysynthesizes the carrier from a crystal ref-erence. This type of RF transmission re-quires the dc voltage of the modulatingsignal to be 0V; otherwise, the PLL tendsto “track out” the transmitted data. FSKtransmission usually uses the familiarManchester-encoding method. However,

Manchester encoding requires twice thebandwidth of AMI encoding and usual-ly requires the addition of preamble andpostamble bits to allow the receiver to de-termine the center of the data bit for de-coding. AMI suffers from none of these

disadvantages; however, it has a draw-back: A long string of zeros produces notransitions in the data stream. To addressthis drawback, high-density bipolar 3(HDB3) encoding is available.

The circuit in Figure 2 shows a 16-channel, AMI-encoded RF transmitterfor data rates as high as 28.8 kbps. Thecircuit operates in the unlicensed (FCCPart 15) 902- to 928-MHz industrial, sci-entific, and medical (ISM) band and is re-liable for open-field distances as long as1000 ft. You can easily modify it to sus-tain higher or lower data rates. IC

1, IC

2,

R1, and R

2perform the AMI encoding.

IC1A

, a simple D flip-flop, controls thehigh-impedance state on Pin 13 of IC

2.

IC1B

alternates the data presented to IC2

whenever the previous data is a logic one.This data has a slight delay to avoid

RF transmitter uses AMI encodingPaul Sofianos, Motorola, Tempe, AZ

AMI encoding uses a pulse of either polarity todenote a logic one and a 0V level to denote alogic zero.

0 1 0 0 1 1 1 0 1 0

F igure 1


ideasdesign

glitches in the output waveform. R1 and

R2

set the high-impedance voltage to1/2V

CC. R

2adjusts the peak deviation of

the transmitted RF signal from IC3, nom-

inally set at 50 kHz. C1

and R2

constitutea lowpass filter with corner frequency setto attenuate the data at frequencies abovethe third harmonic.

IC3

is a low-power, integrated RFtransmitter (Motorola, www.motorola.com) targeting ISM applications. Its volt-age-controlled oscillator is a parallel-res-onant Colpitts type. The varactor diode,D

1, controls the modulation, and D

2sets

the center frequency. The modulation,D

1, is set to approximately 60 kHz/V, and

the frequency adjustment, D2, is set to 7

MHz/V. The mixer of the IC serves as abuffer; you can adjust R

3for desired out-

put power. C2/L

1 and C

3/L

2conjugately

match the source-to-load impedances.These values can vary, depending on theparasitics of your layout. CF

1(TDK

Corp, www.tdk.com) provides final fil-tering of the output before transmission.IC

4synthesizes the desired carrier fre-

quency. The IC internally divides by 512the frequency that crystal Y

1establishes.

With Pin 16 of IC3

tied low, the synthe-sized frequency is f

OUT5(2.048 MHz/

512)•65•N, where N represents the digi-tal value present on the N bus of IC

4.

As illustrated, N can vary from 3472 to3487, yielding 16 discrete output chan-

nels from 902.72 to 906.62 MHz in 260-kHz steps. R

4and C

4form a lowpass fil-

ter with corner frequency set to a valuesubstantially lower than the internal ref-erence frequency of the synthesizer or thedata stream, whichever is lower. As withany RF design, you should give carefulconsideration to parts placement andshielding. You should also apply gener-ous decoupling. If desired, you can holdPin 17 of IC

3 at logic zero for low-pow-

er-disabled operation. (DI #2429).

1A11A2

J

1A3

1A4

2A12A2

1Y11Y2

1Y31Y4

2Y12Y2

1G

2G

IC274HC368

IC1A74HC112CLK

K

Q

Q

PR

CL

J

CLK

K

Q

Q

PR

OSCB

OSCE

OSCC

OSC0

OSCI RA0 RA1 RA2 T/R N0 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13

LD FV PV PR PD

MIX/BUF_IN

PA_IN

LINADJ

CL

+

+

+

MC

EN

VCC

VCC

VCC

VCC

VCC

VCC

R11k

R21k

IC1B74HC112

2 3

5

79

11

13

46

10

12

14

1

15

CLK

DATA

9

11

12

5

4

22

16

17

2.7 pF

27 pF

27 pF

1000 pF

100 pF

C12700 pF

R4, 39k

C4

C5C6

C2

2.7 pF

VCC

R3, 270

C9

R3, 10k

R4, 10k

L1 1.8 nF

D2

D1

0.1

10 nF

FIN

22 23252420191817161514135

5

27 6

6

7

78

4321

121121

26 28 10 9 8 4

ANTENNA

IC4 MC145151

C16

27 pF

27 pF

Y12.048 MHz

S1

1000 pF

C32.2 pF

100 pF

L23.3 nF

200CF1

CF6118702

IC3MC13146

R8

51RF2

RF+

PA_OUT

PRSCOUT

MMBV809LT1

0.5 pF

15 pF

2.2 pF

3

1

2

4

5 11

13

14

612

10

9

7

1

2

3

F igure 2

AMI provides an attractive alternative to Manchester encoding for direct-conversion FM transmission.



ideasdesign

It can be difficult to generate ahigh-voltage supply from amedium-voltage input, espe-

cially if you need a surface-mount design.It is difficult to find surface-mount com-ponents with the necessary specs, espe-cially the transformer and power switch-es. High-voltage surface-mount capa-citors can also be hard to locate. The cir-cuit in Figure 1 generates 100V from25V. The circuit is a typical flyback regu-lator that uses a couple of well-estab-lished circuit techniques to handle thehigh voltage. The first technique is to in-sert an n-channel MOSFET (Si4480) inseries with IC

1’s internal power transis-

tor. The cascoded FET stands off the largeswitch voltage that arises when the switchturns off. The large switch voltage repre-sents the input voltage summed with thereflected output voltage of the trans-former’s primary. Using the cascode FETnot only increases the effective switch-voltage capability, but also eliminates the

need for a snubber circuit across the pri-mary of the transformer.

Of course, the FET actively turns onwhen the source goes low. But simply us-ing the input voltage to supply the gatevoltage doesn’t work, because the maxi-mum input voltage (25V) exceeds themaximum 620V limit of the MOSFET’sgate-to-source voltage. Therefore, the cir-

cuit uses an emitter follower to supply aconstant voltage to the gate of the MOS-FET. A 1-kV resistor delivers bias currentto an 8.2V zener diode at the base of thenpn transistor and provides base currentto the npn. This arrangement sets thenpn’s emitter and the FET gate connect-ed to it at 7.5V—more than enough volt-age for a logic-level FET. The input to IC

1

also connects to the emitter through anRC filter. A convenient feature of this cir-cuit is that the IC switch voltage feedsback through the diode to the input(bootstrapping). This connection allowsfor a small boost in efficiency, negatingthe loss of efficiency from using a cas-coding FET and the emitter-follower cir-cuit. Figure 2 shows the efficiency of theregulator with and without the boot-strapped diode at different load currents.(DI #2439).

High-voltage regulator is 100%-surface-mountableTom Gross, Linear Technology Corp, Milpitas, CA

+

+

+

+

100k

100k

100k

100k

220 mF, 35V

10 mF, 16VCERAMIC

22 mF, 35VAVX TPS

1 mFCERAMIC

10 mH

220 mF, 35V

220 mF, 35V

220 mF, 35V

SANYO CV-GXALUMINUMELECTROLYTIC

VOUTVIN

10 TO 25V100V AT 50 mA MAXIMUM

825k1%

10.5k1%

VIN

VC

SW

FB

GND

1 2

56

46800 pF560 pF

47k

10MBR0520

MBRS1100

MURS1601k FMMT619

COILCRAFTVP2-0216

1:5

6

3

7

5

IC1LT1308

8.2V, W14

+

Si4480

F igure 1

This bootstrapped high-voltage regulator uses all surface-mount components.

75

5020 30 40 50 60

WITHOUT DIODE

WITH DIODE

LOAD CURRENT (mA)

EFFICIENCY (%)

F igure 2

Bootstrapping the IC switch voltage to the in-put in the circuit of Figure 1 improves efficien-cy by about 3%.





Name

Title

Phone

E-mail Fax

Company

Address

Country ZIP

Design Idea Title





Signed

Date



ideasdesign



www.ednmag.com December 9, 1999 | edn 159

ideasdesign

The circuit in Figure 1, using a low-offset amplifier, is a basic ohmmetercircuit common in multime-

ters, except for the addition of thetwo diode-connected transistors. A cur-rent source supplies a selectable currentranging from 100 nA to 1 mA to RX. AnA/D converter with a 400-mV referencevoltage reads the voltage drop across R

X.

Manufacturers of handheld DMMs lim-it I

Mto 1 mA to save battery power. So,

to measure resistance lower than 40Vwith 10-mV resolution, you need to am-plify the voltage drop across R

Xby 10

times to fully use the ADC’s dynamicrange. For high-precision measurements,you need a low-offset, high-input-im-pedance amplifier. The moderate-powerOP97 from Analog Devices is a goodchoice. Because the OP97’s inputs haveback-to-back diode protection, differen-tial input voltages greater than 1V causecurrent to flow through the diodes, caus-ing measurement errors. For example, er-rors can occur when you try tomeasure a high value of R

X, say a

few megohms, with a wrong value of IM

.

5V

RX

20k

180k

BC847

BC847

OP97

3

2

6IM

5V

5V

VOUT1.21M

1.21M

1

1

+

F igure 1

F igure 2

Scheme cancels amplifier errorDavid Magliocco, CDPI, Scientrier, France

The addition of two diodes in the feedback loop prevents excessive input current in the OP97.

Scheme cancels amplifier error................159

Serial port provides interrupts for 8031 mC ..................................................160

ADC-to-PC interface transfers data in nibbles..............................................162

Matched offsets put signals into ADC’s range..........................................164

Amplifier compensates piezoelectric-rate gyros ..............................166

Digital camera subs as a scope camera ......................................168

MOSFET pair makes simple SPDT switch ....................................168

Motor controller operates without tachometer feedback ..................170


Without the diodes in Figure 1, the amplifier saturates, and current flows in the differential inputs.

Not all the measurement current goes toR

X, so the converted value is in-

accurate.Figure 2 shows V

OUTand the current

that goes into the noninverting input ofthe OP97 (without the diode-connectedtransistors), configured for a gain of 10,for input voltages as high as 2V. For V

IN

greater than 1V, the leakage current be-comes non-negligible in comparisonwith the lowest values of I

M. A simple way

to limit the leakage current is to limit thegain of the amplifier for high input volt-ages. To prevent the differential inputvoltage from exceeding 1V, you can re-duce the gain by limiting the voltageacross the feedback resistor. When thatvoltage reaches approximately 0.8V, forexample for I

MR

XQ10 mV, the two

diode-connected transistors start to con-duct and limit the gain. Transistors arebetter than signal diodes because theyhave lower leakage current at low volt-ages. Low leakage current is critical inavoiding additional errors when readingthe output of the OP97. Figure 3 showsV

OUTand the current that enters the non-

inverting input of the OP97 for inputvoltages as high as 2V in the circuit ofFigure 1. The leakage remains low in

comparison with IM

. (DI #2447)

160 edn | December 9, 1999 www.ednmag.com

ideasdesign

F igure 3

The diodes in Figure 1 prevent the amplifier from saturating, so the input current remains negli-gible with respect to IM.

You can use the RxD pin of an 8031mC for external interrupts(Figure 1). You program the

serial port to receive in Mode 2 with abaud rate either 1/32 or 1/64 of the oscilla-tor frequency, depending on the SMODbit in the PCON register. In serial mode,the start bit should be a zero, and the stopbit should be a one for a valid reception.The mC generates the interrupt upon re-ception of a low start bit, nine data bits,and a high stop bit; the interrupt occursat the end of reception. The one-shotmultivibrator in Figure 1 provides a lowpulse (the start bit) to the RxD input witha width greater than one bit period; forexample, four periods. The bit period de-pends on the baud rate. Whenever an ex-ternal signal edge-triggers the one-shot,

the 8031 enters serial-reception modeand generates an interrupt after 10 bit pe-riods. The only disadvantage of themethod is that at least 10 bit periodsshould occur between interrupts. Also,you should use the mC’s ISR pin to reini-tialize the controller for the next inter-rupt. If you can’t guarantee the mini-mum period between interrupts, thenyou can use a dual 74LS221 one-shot

multivibrator.You can use the rising edgeat Q

1to trigger a second one-shot and

then use the output of the second to clearthe first one-shot. This action forces Q

1

to a high state for five to six bit periods toensure a high stop bit. (DI #2441)

Serial port provides interrupts for 8031 mCN Kannan, Mediatronix Ltd, Trivandrum, India

You can use the serial port of an 8031 mC to generate interrupts.

EDGE-TRIGGERONE-SHOT74LS221

T T'FIVE BIT PERIODS

RxDQ112IN

F igure 1




ideasdesign

The circuit in Figure 1 uses a Cen-tronics printer port to interface aneight-channel, 8-bit ADC to a PC.

The circuit cuts the cost of addressingand decoder circuitry and saves one ex-pansion slot for interfacing. The designuses three of the subport’s various signalsas control signals for channel selection,handshaking, and data transfer to theMAX158 ADC. These signals are pro-grammable by means of a bit position inthe control word of the respective port.

Two signals, P_Slct1 and P_Slct2, whenhigh and low, respectively, select theMAX158 ADC. This arrangement over-comes any accidental-selection problem,which can happen when you use a singleselect bit. A falling edge at the RD and CSpins of the MAX158 initiates a conver-sion, and the read operation latches the

multiplexer address inputs, A0

throughA

2, for the channel selection. The level at

the INT pin of IC2

indicates the status ofthe conversion process.A low level at INTindicates that conversion process is overand that the converted digital data isavailable. The INT pin interfaces to theport through the D_Rdy signal. The cor-responding software repeatedly samplesthis line to check its status. When D_Rdyis low, the PC reads the converted digitaldata through IC

1.

Only five input lines to the printer portare available, so the 8-bit data transfer oc-curs in two nibbles from IC

1. The higher

or lower nibble is available when IC1’s Pin

1 or Pin 19 is low, respectively. Under thecontrol of the N_Slct signal, only one ofthese pins is low at once. The softwarethen combines two nibbles to complete

1 byte of data. The circuit uses the fifthinput bit, which is the D_Rdy signal, tocheck the conversion status of IC

2.

VREF

1 and bypass capacitors C1and C

2

connect to a 5V input supply, which re-sults in a full 0-to-5V conversion. A 7805regulator (not shown) generates V

CC.

The accompanying C program workssatisfactorily and can scan all the chan-nels one after the other and print theconverted data on the screen. You candownload the program from EDN’s Website, www.ednmag.com. Click on “SearchDatabases” and then enter the SoftwareCenter to download the file for DesignIdea #2448. (DI #2448)

ADC-to-PC interface transfers data in nibblesDS Oberoi, Jammu, India

+

1

14

15

12

14

1618

3

16

17

9

10

11

24

12

25

13

IC2MAX158

IC174LS244

VDD

C147 mF16V

C20.1 mF

VCC (5V)

VREF2

VREF+

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

6

5

4

3

2

1

28

27

26

INPUTCHANNELS

ONE TO EIGHT

2Y42Y32Y2

2Y1

1Y41Y31Y2

1Y1

2A4

2G

1G

2A3

2A2

2A11A4

1A3

1A21A1

P_S1ct2

D6, D2

D7, D3

D5, D1

D4, D0

D4

D5

P1

D6

D7

3

5

79

D0

A0

A1

A2

A0

A1

A2

D0

D1

D2

D3

D4

D5

D6

D7

D1

D2

D3

25

24

23

17

19

15

13118

1

6

42

8

9

10

111920

21

22

13

12

18

11

2

23

3

ADC_S1ct74LS32

74LS32

74LS04 74LS32

74LS32

4

4

5

12

6

1311

9

108

DATA_HIGH

DATA_LOW

CONNECTOR DB25

D_Rdy

P_S1ct1

N_S1ctINT

RD

CS

14

GND

16

15

D_RDY

74LS04

F igure 1

Only five input lines to the printer port are available, so the 8-bit data transfer from the ADC to the PC occurs in two nibbles from IC1, under the con-trol of the N_Slct signal from the PC.


The circuit in Figure 1 measures avoltage that is negative with respectto the system’s ground point. The

constraint is that the a single supply pow-ers the ADC, and its ground point is fixedrelative to the measured voltage. A sim-ple current source and matched resistorset provide the necessary offset to bringthe voltage within the ADC’s common-mode range.

This circuit was designed for measur-ing the current from a set of power track-ers on the Iowa State University Solar Car,the PrISUm Phoenix. The power trackersprovide impedance matching betweenthe solar array and the main electrical buson the car. Because the current shunt forthe power trackers is on the low side andthe ground reference point is on the elec-trical-system side of the shunt, the volt-age is normally negative with respect tothe system ground.

The current to be measured flowsthrough the 0.01V shunt. Because thevoltage is negative with respect to the sys-tem ground, you must add an offset toplace the signal within the common-mode range of the ADC. The REF200

matched current sources and the 10-kVmatched resistors create this offset. Thisscheme provides a positive offset of ap-proximately 1V with a reasonable tem-perature coefficient. Because the ADCmeasures a differential voltage, the exactoffset is unimportant as long as both legshave the same offset and remainmatched. For this application, 1V is anadequate offset because the maximumcurrent expected to flow through theshunt is only 10A, which equates to amaximum differential voltage of only0.1V. You can easily modify this offset forother current-and-shunt-resistor combi-nations by selecting different resistor val-ues for the matched resistor pair. Takecare not to make the resistance values toohigh because high values may cause set-tling-time errors on the ADC’s input.

Suitable ADCs for this circuit are theAD7705 (Analog Devices) and theADS121x (Burr-Brown Corp). TheseADCs provide system-calibration capa-bilities that let you easily correct for slightmismatches in the current sources andresistors. The system-gain- and system-offset-correction features enable the cir-

cuit to maintain accuracy even in thepresence of these mismatches. To adjustfor offset, apply zero current and instructthe ADC to perform the system-offsetcalibration. To perform gain calibration,apply a current that corresponds to fullscale and instruct the ADC to performthe system-gain calibration. You can ob-tain these calibration values, store themin the mC, and then send them to theADC upon subsequent power-ups, elim-inating the need for calibration on everypower-up.

The diode across the current shuntpasses any high-current transients whenyou apply the power source. In the orig-inal design, this feature was necessary topass the high-current surge that chargedthe power tracker’s output capacitorswhen the power trackers switch into thesystem.Without the diodes, this surge de-stroyed the current shunt. Depending onthe application and the size of the currentshunt, these diodes may be unnecessary.(DI #2450)

Matched offsets put signals into ADC’s rangeMichael Petersen, Iowa State University, Ames, IA


ideasdesign

10k

MATCHED RESISTOR SET(CADDOCK T912)

0.01

100 mA

100 mA

REF200(BURR-BROWN)

AIN1+

AIN12

VDD

ADC

GND

I/O

I/O

IIN

IOUT

1 mF

5V

5V

F igure 1

A simple current source and a matched resistor set provide the necessary offset to bring the voltage within the ADC’s common-mode range.



ideasdesign

Low-power, low-cost ceramic pi-ezoelectric rate gyros are available,but they lack the low-temperature-

coefficient characteristics of their quartzcounterparts. However, you can use a ser-vo amplifier to remove the dc level shiftdue to temperature-related drift effects(Figure 1). The original application ofthese small, rugged gyros was for damp-ing video-camcorder jitter, but these de-vices suit many other applications, in-cluding camera-platform stabilization,radio-controlled-airplane- and helicop-ter-rate-damping-control assistance, re-motely piloted vehicles, and computer-mouse motion sensors.

By setting the time constant of the ser-vo loop in Figure 1, the circuit respondsat an appropriate low frequency for thesystem under control. The time constantyou use for the servo loop depends on the

dynamics of this system, but 10 to 50times the lowest frequency of interest isa good starting point. The dc-level driftoccurs at a slow rate and hence appearsto be a valid response. However, the rate-gyro amplifier also passes some frequen-cies above the set frequency. (The cornerfrequency of the highpass filter dependson what the circuit is controlling.)

Amplifier IC1A

and its servo-driverstage, IC

1B, comprise a low-power op

amp. The servo controlling the dc levelac-couples, or highpass-filters, the gyro’soutput by forcing the output of IC

1Ato

swing around V42. The lowest frequen-cy that the circuit passes is a function ofthe C

1/R

1time constant. The maximum

value of R1 depends on the minimum in-

put bias current of the op amp, which is250 pA for the LT1495. If space permits,

C1

should be a good low-leakage type,such as polystyrene, Teflon, orpolypropylene. A Mylar capacitor com-promises the integrator’s performance.

The gyro and its amplifier can be somedistance from the main processing cir-cuit, and cable capacitance can causemany op amps to oscillate. However, theLT1368, IC

2B, at the output can drive ca-

ble capacitance without stability prob-lems. The LT1368, IC

2A, also serves to

drive a filter capacitor to provide a low-noise 1/2V reference point for the LT1495servo driver. (DI #2453)

Amplifier compensates piezoelectric-rate gyrosJim Mahoney, Linear Technology Corp, Milpitas, CA


+2.2 mF

2

+2

+

2

2

+

+

GYRO_AMP_OUT

0.1 mF

4.7 mF

0.1 mF

4.7 mF

0.01 mF

0.01 mF

IC2BLT1368

IC1BLT1495

IC1ALT1495

IC2ALT1368

5

6

7

R11M

C1100k

200k

10k200k

4.99k

4.99k

1

2

3

5

67

V+/2

GYRO(TOKIN_CD_16C1)

4

2

3

V

V/2

3

2

1

Servo amplifier IC1A removes the dc level shift due to temperature-related drift effects of a piezoelectric-rate gyro.

F igure 1


ideasdesign

Adigital camera can be a handysubstitute for an oscilloscopecamera for older scopes that

cannot output hard copy or digital data.A digital camera provides instant resultsand allows you to easily enhance the im-age and then add it to reports or Webpages.

If the scope has an illuminated grati-cule, turn up the illumination. A tripodis useful for repeated shots but is other-wise unnecessary. Position the cameraand adjust the camera’s zoom so that theoscilloscope screen fills the picture. Ad-just lighting and position to minimize re-flections.

After you take the picture, transfer it toa PC. You can then use an image-editingprogram to crop, rotate, and otherwiseenhance the photo as necessary. To addannotations, such as text and arrows, tothe image, you can import the image intoa drawing program, although some im-age-editing programs offer this capabili-ty as well.You can then print the final im-age, insert it in a document, or add it toa Web page.

For output to monochrome devices,such as a black-and-while printer, it canbe advantageous to first convert the col-or image to monochrome and then re-

verse the result: Change the white to blackand the black to white. This procedure re-sults in sharp, dark lines for the oscillo-scope traces against a light-gray back-ground. Some digital cameras have amonochrome mode.

The image in Figure 1 illustrates theresults of this procedure in capturing atiming measurement using a Sony Ma-vica MVC-FD7 camera set to mono-chrome mode. After image capture, the

next step is cropping the resulting JPEGimage using Microsoft Photo Editor 3.0and then applying a reverse effect to swapthe black and white tones. Finally, im-porting the image to Micrografx Win-dows Draw 6.0 allows you to add anno-tations, such as in the figure. (DI #2452)

Digital camera subs as a scope cameraAllen Moore, Redmond, WA

F igure 1

If you use an old oscilloscope lacking hard-copy- or digital-output capability, you can use a digitalcamera to capture, save, and annotate the oscilloscope image


With an n-and p-channel MOS-FET, you can easily implement asingle-pole double-throw (SPDT)

switch to isolate part of a circuit andpower it from a secondary supply forstandby operation while the rest of thecircuit is off (Figure 1). By using a com-plementary pair, you can use a single con-trol input for the MOSFETs. An

Si4501DY MOSFET in this topology ex-hibits less than a 0.1V drop at 5A for themain element and contains both MOS-FETs in an SO-8 package.

When the 2N7002 or similar controlMOSFET ties the gates together and pullsthem to ground, the p-channel MOSFETis on. Pulling the gates above the supplyrail by turning the 2N7002 off results in

turning the n-channel MOSFET on.Pulling the gate of the p-channel MOS-FET above the source potential has no ef-fect; the MOSFET remains off with lowleakage.

The resultant switch is a break-before-make configuration, which is necessaryto ensure that the secondary, or always-on, supply never has to power the whole

MOSFET pair makes simple SPDT switchHoward Chen, Vishay Siliconix, Santa Clara, CA

circuit. However, due to the fast switch-ing of the MOSFETs, extra ca-pacitance beyond normal designrules is probably unnecessary to main-tain the operating voltage.

The arrangement of the n-channel de-vice in the circuit ensures that the inter-nal diode does not conduct while thesubcircuit is isolated. In this direction,the n-channel MOSFET also provides afail-safe path for the circuit’s powerthrough the diode. The forward voltageof the p-channel MOSFET’s diode blocksany current from “back-feeding”the sec-ondary supply, assuming that the twosupplies are close in voltage.

An example of an application for thiscircuit is the Advanced Configurationand Power Interface in desktop comput-ers providing instant-on and low powerconsumption in standby. The main pow-er supply is a high-power switching pow-er supply, and the secondary supply is a60-Hz transformer with linear regula-tion. (DI #2451)


ideasdesign


Speed controllers have long ex-ploited the reverse-EMF character-istics of dc motors to control their

speed. These linear driver circuits usepower op amps to create a negative re-sistance drive to the motor that counter-acts the voltage drop in the motor’s seriesresistance (Reference 1). The circuit inFigure 1 shows an implementation ofthis type of speed control using a PWMdrive, which reduces power dissipation inthe drive circuitry.

Control voltage VIN

sets the speed, andIC

1, Q

1, and R

3convert V

IN to a 0- to 200-

mA current. The current source controlsthe duty cycle of the PWM driver, IC

2, at

Pin 3. D1, D

2, and R

5prevent the circuit

from pulling the control input too low,which can cause an inversion in the con-trol loop.

Motor current flows through the in-ternal switching transistor in IC

2out the

common terminal and through the cur-

rent-sense resistor, RS. The circuit filters

and scales the voltage across the sense re-sistor to provide positive feedback to theinput circuitry through R

2. With the

proper amount of positive feedback, anincrease in motor load increases motorcurrent, which increases duty-cycle driveto maintain constant speed.

The equation of speed balance is

Motor controller operates without tachometer feedbackBruce Trump, Burr-Brown Corp, Tucson, AZ

LOAD

ALWAYS-ONCIRCUIT

MAINCIRCUIT

CONTROL

MAINSUPPLY

ALWAYS-ONSUPPLY

CONTROL

12V

MAIN SUPPLY

Si4500DY OR Si4501DY

SECONDARYSUPPLY

(a)

(b)

2N7002

F igure 1

An n- and p-channel MOSFET pair comprises a break-before-make, single-pole, double-throwswitch (a). The switch isolates part of a circuit and powers it from a secondary supply during stand-by operation when the rest of the circuit is off (b).

.A 200R

V

RR

RRI)RR(I

321

1SMSMM

µ×+

+=+

This model neglects losses in theswitching circuitry of IC

2. De-

pending on supply voltage, suchlosses may significantly affect the re-quired feedback. Unlike the power opamp implementation of the scheme, theabsolute supply voltage affects this com-pensated PWM controller. The voltagelost in switching is not truly resistive andcan be tricky to model. In practice, youcan optimize the speed control by ad-justing the positive feedback control atR

4.With proper adjustment, motor speed

remains relatively constant with sub-stantial changes in load.Although less ac-curate than true closed-loop tachometer-feedback controllers, this low-costtechnique provides a dramatic improve-ment over simple voltage drive. (DI#2449)

Reference1. Burr-Brown Applications Bulletin

AB-152


ideasdesign


DRV101PWM

EMF

OPA237VIN

R2

`

`

1

15k

IC1

4.5 TO 36V

Q1

R410k

10k

20 nF RS

0 TO 200 mA

D2

10 TO 60V

1 5

4

6

DC MOTOR

IN40001

D1

10 mFTANTALUM

R5

IC2

R1

470k

R31k

1k

1

221N4148

2N7000

3

F igure 1

Positive feedback derived from current-sense resistor RS increases the duty-cycle drive from PWMcontroller IC2 to compensate motor speed with varying loads.


Telephone subscriber lines havebecome a topic of intense interest fororganizations attempting to transmit

Internet signals on telephone lines. Basicloop standards exist, and tables of twist-ed-pair primary constants extending to20 MHz are in the literature. Asymmet-ric digital-subscriber lines (ADSLs) arenow available for high-speed Internetservice. The telephone industry has al-ways used two-port networks in the formof ABCD matrices to cascade sections oftelephone cable. These configurations al-low you to join the sections by matrixmultiplication. However, because the el-ements in the matrices are complex num-bers and several sections make up achain, you need to organize the processof matrix multiplication. A short com-puter program performs this task (List-ing 1). You enter the number of matricesin the chain and then enter the real andimaginary parts for each A, B, C, and Delement. The product then appears onthe screen.

The two-port matrix equation with

the ABDC parameters has the followingformat:

where

A represents the open-circuit transferfunction, B represents the short-circuittransfer impedance, C represents theopen-circuit transfer admittance, and Drepresents the short-circuit current ratio.You can find the ABCD matrix for a lad-der network composed of RLC elementsby slicing the network into series andshunt matrices. You then multiply the

product of the first two by the third, andthe progression continues with addition-al subscripts identifying the components.In the final product, the elements A, B, C,and D—with all their component sym-bols—may become quite cumbersome.To avoid these complicated expressionsin the matrix for the ladder network,don’t use them. Rather, enter the numer-ical values for the series and shunt com-ponents along with the necessary 0,0sand 1,0s.You can use this concept for anynetwork comprising passive componentsthat you can separate into isolated two-port sections. You can also use themethod to predict the degradation abridged tap produces in a telephone cable.

The progression of entering values forcascaded networks is normally from leftto right, or from source to load with the


ideasdesign

Cascade ABCD two-port networks ..........107

Simple tester checks Christmas-tree lights ..................................108

Power meter uses low-cost multiplier ........................................................110

Add music to your next project ................112

PWM circuit uses fuse to sense current ............................................114

Bias supply accepts high inputs ..............116

Method provides simpleerror-rate generator ....................................118


Cascade ABCD two-port networksBert Erickson, Thomson Consumer Electronics, Fayetteville, NY

LISTING 1—CASCADING TWO-PORT NETWORKS

V1 V1I1

I1[ [ AB

CD

A

C

B

D[ [ V2 V2I2

I2[ [= ,

A=V1

V2 I2=0

V2

I2 V2=0B=

I1V2 I2=0

C=I2I2 V2=0

.D=

ideasdesign

current pointing toward the load. If youreverse the progression, the direction ofthe current is usually reversed, and thelocation of elements A and D is reversedto conform to the reciprocity theorem.The matrices for a single series compo-nent and a single shunt component areas follows:

You can use these simple matrices torepresent RLC components, transform-ers, and bridged taps in telephone cables.However, for a telephone cable, you mustconsider the reflected wave. Thus, youmust express the A, B, C, D elements bythe following hyperbolic functions:

A5cosh(gd),B5Z

0sinh(gd),

C5(1/ Z0)sinh(gd), and

D5cosh(gd).

where the propagation constant g5a1b, d is the electrical length of the ca-ble, and Z

0is the characteristic imped-

ance. In the United States, the nominal

value for Z0

is 100V, which is also thespecified value for the source and loadimpedance. Because g is a complex num-ber,A, B, C, and D are also complex num-bers, or the polar equivalent thereof.These numbers are not difficult to cal-culate; however, the parameters dependon the application (references 1 and 2).The following example shows how to en-ter the data and read the results:

Within the solid bars, N1

through N4

show the entered data for the compo-

nents. The bottom line shows the matrixproduct as it appears on the screen. Forthis network, the matrix elements areA5431j0, B502j25, C501j12, andD571j0. The open-circuit voltage ratiois V

1/V

2=A=43. The open-circuit trans-

fer admittance I1/V25C501j12. Theinput impedance is Z

IN5A/C502j

(43/12). Listing 1 uses easy-to-read and-compile QuickBasic. You can downloadthis listing from EDN’s Web site,www.ednmag.com. Click on “SearchDatabases” and then enter the SoftwareCenter to download the file for DesignIdea #2455. (DI #2455)

References1. Rauschmayer, Dennis, ADSL/VDSL

Principles, MacMillan Technical Publish-ing, 1999.

2. Chen, Walter, DLS: Simulation Tech-niques and Standards Development ofDigital Subscriber Line Systems, MacMil-lan Technical Publishing, 1998.


1,00,0

Z1,0[ [ 1,0

1/Z0,01,0[ [

Z

Z.

I2I1

V1

3H1/4F

1/2H 2F V2

2

+

2

+

1,01/Z

0,241,0[ [

1,00,0

0,31,0[ [

1,00,22

0,01,0[ [N1= N2=

N3= 1,00,2

0,01,0[ [N4=

27,00,22

0,2257,0[ [0,2

0,2427,01,0[ [43,00,12

0,2257,0[ [N1z N2zN3zN4=

N1z N2zN3=N1z N2=

;

Why is it that you alwaystest 48 bulbs before youfind the bad one in a 50-

light string? The simple circuit in Figure1 allows you to divide and conquer,greatly reducing the time it takes to findthe bad bulb. The circuit uses a pair ofNE2 neon bulbs with current-limitingresistors. You can use a pair of RadioShack 272-1100 bulb-resistor sets. It’sconvenient to house the tester in a clearpiece of plastic tubing, with the probe tipemerging from one end and a light-dutypower cord emerging from the other end.You place the bulbs in the tube such thatone is close to the probe tip and the oth-er is near the power cord, so it’s easy to re-

member which bulb lit last. The probe tipconnects to common point between theneon bulbs. It consists of thin spring wirewith all but the last 1/4 in. insulated. You

use the bare tip to make contact with thecrimp connectors in the base of the bulbs.

Series-string Christmas-tree lightscome in two types. The first type is thecontinuous-series string (Figure 2a). Inthis configuration, one wire from theplug goes from bulb to bulb until itreaches the last bulb. A return wire by-passes all the bulbs and returns to theplug. The second type is the alternating-series string (Figure 2b). In this connec-tion, one wire from the plug goes to thefirst bulb, and the other wire from theplug goes to the second bulb. The con-nections then alternate through thestring. To troubleshoot a defective con-tinuous series string:

Simple tester checks Christmas-tree lightsWilliam Dias, Brown & Sharpe, North Kingstown, RI

PROBEF igure 1

A simple probe set cuts the time you spendtroubleshooting a series-string light set.


ideasdesign

● Plug in both the tester and the bulbset.

● Insert the tip of the tester’s probeinto the wire hole in the base of thefirst bulb. One of the neon bulbsshould light; remember which one.

● Move halfway down the set and in-sert the probe again. If the sameneon bulb lights, then the problemis in the second half of the set. If theother neon bulb lights, then theproblem is in the first half of the set.Either way, you are testing 25 of the50 bulbs without breaking into asweat.

● If the original neon bulb lights,move halfway down the remaining

part of the set and try again. If theother neon bulb lights, you mustmove back halfway to the last bulbyou tested and try again. Thisprocess should allow you to find abad bulb in a set of 50 in only sev-en steps.You know you have the badbulb when inserting the probe tipinto one side of the bulb lights oneneon bulb and placing the tip in theother side lights the other neonbulb.

To troubleshoot a defective set withmany bad bulbs, use the same process asabove. At some point, you will reach thedead spot between two or more badbulbs.When you reach this point, neither

neon lamp will light. Back up, just as if theother neon bulb had lit. You know youhave a bad bulb if the probe lights whenyou plug it into one side and nothinglights when you plug it into the otherside. Replace this bulb and start over.

To troubleshoot an alternating-seriesstring, you must work in pairs. Test thefirst bulb, and one neon bulb lights. Testthe second bulb, and the other neon bulblights. Now move down the set an evennumber of lights and test the next pairof lights.When you pass the bad bulb, thesame neon lamp lights for both series-string bulbs. (DI #2457).


(a)

(b)

F igure 2

Series-string light sets come in two flavors: a continuous-series string (a) and an alternating-series string (b).

Apower-meter circuit typically re-quires either an analog or a digitalmultiplying circuit. These circuits

can be complex, finicky, or expensive. Asimpler way to achieve the multiplicationfirst converts the current to a duty cycleproportional to the current. You can usethis duty cycle to gate the input voltage;the gating effectively provides a multipli-cation function. A lowpass filter thenprovides an output voltage proportional

to power. The method sounds convolut-ed, but the implementation is simple.Figure 1 shows the complete power-me-ter circuit. The National SemiconductorLM3812M-7.0 IC senses current and de-livers a duty cycle proportional to thecurrent. The current relates to the duty-cycle output as follows:

The desired output is a voltage equal to

the input power divided by 10. The di-vide-by-10 operation keeps the voltagewithin a manageable range. The outputis, then:

To subtract the 1/2VIN

term in the equa-tion, the first op amp inverts the powersignal. The second op amp adds in the

Power meter uses low-cost multiplierJeff Kotowski and Alan Johnston, National Semiconductor, Grass Valley, CA

).5.0CYCLE_DUTY(22I 1•=

[ ].V21VCYCLE_DUTY

2.210/IVV

ININ

INOUT

••

•=•=

1


ideasdesign

+_

+RLOAD

1

2

3

4 5

6

7

8

1

1

1

C2

C3 C4

C1

J1

J2

J3

VOUTLM412

SENSE 6VDD GND

SENSE 1 GND

FILTER + PWM

FILTER 1 SD

SUPPLY (2 to 5.5V)110k

110kLM412

R1

LM3812

400k

R2

R3

R5

R4

10 mF 10 mF

IC2BIC2A

IC1

0.1 mF

0.1 mF

200k

220K

5V

25V _ 5V

5V

1

F igure 1

A low-cost duty-cycle IC forms the heart of a power-meter circuit.

offset and again inverts the signal. Ca-pacitors C

1and C

2provide filtering.

These capacitors connect back-to-backto achieve nonpolar operation. Tests withinput currents of 27 to 17A and with asource voltage of 2 to 5.25V showed bet-

ter than 3% accuracy over the range of 0to 25W. (DI # 2458)

Adding music to your nextdesign is as simple as usingone I/O pin to drive the

speaker and approximately 150 words ofprogram memory to play the music. Youcan store the musical notes and durationsinternally in program memory or exter-nally in a serial EEPROM. Frequently, im-plementing musical playback requires anexternal processor with memory or a spe-cialized melody device. Both cases canbring increased cost and can limit thenumber of songs you can play back. Theapproach described here uses a Mi-crochip Technology midrange PIC mCwith a free 8-bit timer resource. Two im-plementations are possible. The one pre-sented here uses internal program mem-ory to store the musical notes. Thismethod allows as many as 127 notes persong. The other technique is to use an ex-

ternal serial EEPROM to store the notes.The first important point to consider

is that the musical playback is complete-ly interrupt-driven. Therefore, the mainapplication can run in the foregroundand can accept interrupts as necessaryfrom the musical playback. Timer0 con-trols the playback; you can find it on anyof the midrange PIC mCs—from theeight-pin PIC12C671 to the 68-pin

PIC16C924. This timer is a generic 8-bittimer with an 8-bit prescaler. You candownload the assembly code from EDN’sWeb site, www.ednmag.com. Click on“Search Databases” and then enter theSoftware Center to download the file forDesign Idea #2556. The code is designedto run a PIC mC at 4 MHz. You can ac-commodate other frequencies by chang-ing defines in the code.At 4 MHz, you usea 1-to-8 prescaler to provide the correctfrequencies for the notes to play. Again,you can modify the prescale value to suitthe desired operating frequency bychanging the value in the Option register.One I/O pin provides the musical notesto the speaker. Figure 1 shows the sim-ple connections. You can modify thesource code and hardware to drive thespeaker differentially using two I/O pins.

Toggling an I/O pin at twice the fre-

Add music to your next projectRodger Richey, Microchip Technology Inc, Chandler, AZ

VDD

PIC mC

RA0

F igure 1

You need only one I/O pin and a capacitor togenerate music with a PIC mC.



ideasdesign

quency of the desired note generates eachnote. This technique creates software-based pulse-width modulation with a50% duty cycle and a tone at the desiredfrequency. At each Timer0 interrupt, theroutine reloads TMR0 with the numberof ticks for the desired frequency.You usethe following formula to calculate thenumber of ticks for each note:

TICKS(Freqx)5[2562((CLOCK/4/PRESCALER/

Freqx/2)21)]

Using CLOCK=4MHz, PRESCALER=8, and Freqx5523, the calculated num-ber of ticks for an A tone is 137. Thenumber of ticks required is actually 118,but by subtracting this number from 256in the formula, you can get the value toload into TMR0. A table designatedNotes in the source code lists only sevennotes, but it’s easy to add more. You candetermine the duration of each note bycounting the number of Timer0 inter-

rupts. Because the timer interrupt peri-od differs for every note, the number ofTimer0 interrupts differs for every note.A table called Durations in the sourcecode contains the note duration for thecorresponding note in the Notes table.On each Timer0 interrupt, the Notes val-ue loads into TMR0 and the note dura-tion decrements. At the end of each note,a pause of 1/64 occurs to emphasize thenote you are playing. The routine createsthe pause by not toggling the output pinduring the pause interrupts. Again, eachnote requires a different number of in-terrupts to generate a pause of a set du-ration. To simplify the pause generation,the program subtracts the number of in-terrupts required for a pause from eachnote duration. The routine creates thepause by setting the timer such that thepause occurs from one timer interrupt. Ifthe clock frequency is such that you can-not create the pause with one interrupt,you can alter the value STOP_LENGTHin the source code. The program loads

the next note to play after the pause in-terrupt. A 0 in the Notes and Durationstables in the source code denotes the endof the song. At this point, the programplays the song again.

Using internal memory to store thenotes and durations has some limita-tions.Without some extra table-handlingcode, tables are limited to 255 elementsand must start on a 256-byte boundary.Because the duration values are 16 bitslong, the number of notes the PIC mCcan play is 127. Depending on the size ofprogram memory, you can place manysongs in 256-byte blocks and play themindividually. By using two more I/O pins(SCL and SDA), the PIC mC can interfaceto an external serial EEPROM and playany number of notes up to the maximummemory size divided by 3. A 24LC01Bfrom Microchip Technology can hold341 notes plus corresponding durations.(DI #2456)


High efficiency and, hence, lowloss is a usual design goal fora PWM circuit. Figure 1

shows one of several channels of low-loss PWM control for hydraulic valvesused in heavy industrial machinery.These valves usually have dc resistanceof approximately 12V and substantialinductive reactance. The operating volt-age is 24V, and the PWM circuit usual-ly operates at frequencies of 50 to 500Hz to prevent valve sticking. To mini-mize on-resistance losses in the powerMOSFET, the circuit uses a MotorolaMTP36N06, even though that device’scurrent-handling capacity greatly ex-ceeds the load requirements. A MicrelMIC5021 high-side driver provides gatecontrol; its high slew rate minimizes theMOSFET’s switching losses. To imple-ment the overload-protection feature in

PWM circuit uses fuse to sense currentEugene Kaplounovski, Nautilus International, Burnaby, BC, Canada

MTP36NO6

C310 nF

IC1MIC5021

C21 mF

C110 mF

20 TO 36V

Q1VBOOSTVDD

VTRIP=30 TO 70 mV

CT

R11k

R21k

R3330

F1BUSSPCE-55A

D11N4148

D31N5819 D4

MUR420

D21N5819

8

7

6

5

LLOAD

RLOAD

GATE

GND

INPUT

SENSE2

SENSE+

1

2

3

4

PWM INPUT

F igure 1

A fuse does double duty as a protection device and a current-sensing resistor.


the gate driver, a low-resistancecurrent-sensing resistor is neces-sary. Safety requirements and commonsense mandate protection against cata-strophic component failure. Unfortu-nately, the resistance of the fuse con-tributes to circuit losses. The combinedlosses in the fuse and current-sensing re-sistor are comparable with those in therest of the circuit.

You can sometimes replace the cur-rent-sensing resistor by the fuse, therebyeliminating one of the two sources ofloss. The dc resistance of a Buss PCE-55A fuse is 20 to 30 mV, which is quiteclose to the value that the overload-pro-tection circuit requires. The trip point ofthe MIC5021 overcurrent comparator isnominally 50 mV, but it may vary from30 to 70 mV. Such wide tolerance makessetting a precise trip point with a preci-sion resistor impossible. Another of thefuse’s benefits is its positive temperaturecoefficient of resistance. The compara-tor’s trip differential voltage also has apositive temperature coefficient. Thesetwo temperature coefficients track some-what, offering some temperature com-pensation. Figure 2 plots the fuse-resist-ance behavior. The curve is an approx-imated mean value of resistance versuscurrent. Data for the graph uses 10 sam-

ples of the fuse and a second-order poly-nomial function using Matlab software.According to Micrel’s data sheet, the trippoint is a linear function of the ambienttemperature.

R2

and R3, along with D

2and D

3, pro-

vide protection against negative induc-tive-kick spikes at the comparator’s in-puts. Adding R

1allows adjustment of the

current trip point. D1 does not conduct

during normal operation but protects the

comparator from excessive differentialvoltage if the fuse fails. R

2and R

3 limit the

load current under this condition to alow and safe level. Disconnecting the fuseduring experimentation leads to imme-diate shutdown, with only short (sever-al-microsecond) pulses at the output. C

2

determines the time between the circuit’sattempts to restart. (DI #2459)

ideasdesign

0.0265

0.026

0.0255

0.025

0.0245

0.024

0.0235

0.023

0.02250.5 1 1.5 2 2.5 3

R (V)

CURRENT (A)

F igure 2

Self-heating causes a positive temperature coefficient of resistance in the fuse in Figure 1.

When you design dc/dc converters,it is often necessary to generate abias supply to operate the control

circuitry from the raw input voltage.Many methods are available for config-uring the bias supply, each with its ownbenefits and shortcomings. Some meth-ods use a “trickle-charge”start-up circuit,with a back-feed winding to providepower under normal operating condi-tions. With a low parts count and cyclingshort-circuit protection (if leakage in-ductance to the back-feed winding does-n’t cause cycling to stop), this configura-tion is widely used in the power-supplyindustry. However, the configuration suf-

fers from a long turn-on time and a lim-it on the capacitive load into which theconverter starts up. Another popular ap-proach uses a transistor-based pass reg-ulator, often in conjunction with an over-winding to keep power dissipation low innormal run conditions. Although thismethod can provide a fast start-up, itgenerally exhibits high power dissipationduring an output short circuit. Attemptsto gate this type of circuit can be messyand complicated. A buck regulator over-comes the disadvantages but can be com-plex and costly. The circuit in Figure 1uses IC

1, an LT1431 shunt regulator, low-

cost transistors, and an off-the-shelf in-

ductor to form a high-voltage converterfor use as a bias supply.

The circuit needs no bleeder resistorsor tertiary winding. The selection of Q

1

and Q3

limits the maximum input volt-age to 80V in the circuit as shown. Thecircuit operates as a hysteretic regulator,also called a ripple regulator, relaxationoscillator, or bang-bang controller. Pos-itive feedback comes from R

6and R

7;

negative feedback comes from C2, R

8,

and R9. With a 48V input, inductor cur-

rent is discontinuous, and the switchingfrequency is 50 kHz. Efficiency is typi-cally 74% with a 48V input and a 50-mAload, an acceptable figure for bias-sup-

Bias supply accepts high inputsRobert Sheehan, Linear Technology Corp, Milpitas, CA



ideasdesign

ply power. Q2

and Q4

provide short-cir-cuit protection; thus, the design is ro-bust. Short-circuit current is typically

120 mA. You can repeatedly hot-plug the circuit with no adverse effects.(DI #2454)

+

+

VIN

36 TO 72V DC

R11k

R41k

R104.7

R210k

R3100k

R520k

R610

R747k

R94.75k

R816.2k

D1BAS21

IC1LT1431

C112 mF100V

C20.01 mF

C310 mF25V

Q1MMBTA56

Q2MMBTA56

Q4MMBTA06

Q3MMBTA06

COLL V+

REF

GND-F GND-S

D03316P-105COILCRAFT

11V

VOUTAT 50 mA

L1

F igure 1

A shunt-regulator IC and a handful of low-cost components form an efficient, robust bias supply.

Testing the performance of a sys-tem being fed random errors can betricky; it is not easy to add an accu-

rate, low-level bit-error rate to a datastream. The technique shown in Figure 1(page 121) uses a PC, some simple soft-ware, and a few external components oran FPGA. The PC computes an n-bitthreshold from the chosen bit-error rate,which then downloads to the FPGA. Us-ing a magnitude comparator, the FPGAcompares the threshold with the contentsof the linear-feedback-shift register (LF-SR), which clocks at the same rate as thedata stream. If the LFSR’s contents arelower in magnitude than the threshold,an error occurs. If they are greater thanor equal to the threshold, no error occurs.Thus, if you need 50% errors, you set thethreshold to 1000...0; if you need 25% er-rors, you set the threshold to 0100...0, andso on. The PC translates from rates ex-

pressed as, for example, 1 in 104, to sucha threshold. The n-bit threshold shouldbe long enough to achieve the desired ac-curacy. The LFSR must be longer than thethreshold to minimize the effects of theLFSR’s not generating the all-zeros state.Making the LFSR twice the length of thethreshold vector is satisfactory. It is alsonecessary to randomize the starting pointof the LFSR. You can do this by down-loading random digits from the PC at thesame time the threshold downloads.

You use the serial data port and aUART to control the FPGA and load datainto it, by choosing one of the UART’soutput bits to set the Run/Load modeand two other output bits to drive theData and Clock lines.You then write rou-tines to translate loading informationinto sequences of asynchronous charac-ters. Other methods are obviously avail-able. Building the UART into the FPGA

design is another clear improvement. Ifthe threshold register is 32 bits long, theLFSR should be 64 bits long. You shouldchoose the taps to give a sequence lengthof 26421. In other words, the choiceshould be in accordance with a primitivepolynomial. Reference 1 gives a useful listof taps that yield a maximal length se-quence. One choice (chosen at random)requires three taps located at stages 2, 19,and 25 (Figure 1). The speed of opera-tion depends on the capabilities of theFPGA. With modern FPGAs and a littlecare in the design, rates in the hundredsof megahertz are possible. (DI #2460)

Reference1. Schneier, Bruce, Applied Cryptogra-

phy, Second Edition, John Wiley, pg 408.

Method provides simple error-rate generatorJM Williams, Marconi Communications, Liverpool, UK




ideasdesign

ERROR-FREE DATA

DATA CLOCK+

+++

DATA PLUS ERRORS

n-BIT MAGNITUDECOMPARATOR

A<B

SETUP DATAFROM PC

UART (RX)

0 1 2 3 4 5 6 7

NC

n-BIT THRESHOLD REGISTER

n-BIT THRESHOLD VECTOR

B

n-BIT P-NOISE VECTOR

A

FPGA

DATA2n-BIT LINEAR-FEEDBACK-SHIFT REGISTER

CLOCK

LOAD RUN

DATA

LOAD DATA

CLOCK

LOAD CLOCK

RUN CLOCK

F igure 1

Using a PC and an FPGA, you can generate any percentage of random errors in a data stream.


Documents

EDN Design Ideas 1999