7. SUBJECTWISE DETAILS

7.6 ELECTRONIC CIRCUIT ANALYSIS

7.6.1 Objectives and Relevance

7.6.2 Scope of the Subject

7.6.3 Prerequisites

7.6.4 Syllabus

i. JNTU

ii. GATE

iii. IES

7.6.5 Suggested Books

7.6.6 Websites

7.6.7 Expert details

7.6.8 Journals

7.6.9 Recent Findings and Developments

7.6.10 Session Plan

7.6.11 Tutorial Plan

7.6.12 Student Seminar Topics

7.6.13 Question Bank

i. JNTU

ii. GATE

iii. IES

7.6.1 OBJECTIVES AND RELEVANCE

In this subject, a major emphasis is laid on various types of amplifiers while a discussion on Regulated power supplies is carried out in unit-V.

Almost all electronic equipments must include means for amplifying electrical signals. The subject of “Electronic Circuit Analysis” explains in detail how a electrical signal is amplified. The purpose here will be to discuss about “Amplifiers & Power supplies”. The various amplifiers that are going to be discussed include-Single stage, Multistage, Power & Tuned Amplifiers. The design of these amplifiers will also be discussed. The concept of voltage regulator is studied in the last unit wherein various types of voltage regulators are used.

7.6.2 SCOPE

This subject provides a great deal of knowledge on various multistage amplifiers and their cascading depending upon the various requirements such as voltage gain current gain, impedance. Designing of power amplifiers and determining the efficiency of the power amplifiers and also the design of various voltage regulators for various purposes.

7.6.3 PREREQUISITES

The prerequisites for understanding this subject includes concepts of diode and their voltage current characteristics, various configurations of transistors and amplifiers and also the DC and AC analysis of various amplifiers such as BJET, FET.

7.6.4.i SYLLABUS – JNTU

UNIT – IOBJECTIVE

It deals with the design of various amplifiers in terms of voltage gain, current gain and impedance and also deals with the lower and higher frequency response of the amplifiers.

SYLLABUSReview Small Signal Analysis of Junction Transistor, Frequency response of Common Emitter Amplifier, Common Base Amplifier, Common Collector Amplifier, JFET Amplifiers, Common Drain Amplifier, Common Gate Amplifiers, Gain Band Width Product.

UNIT – IIOBJECTIVE

It deals with the design of various multistage amplifiers of BJT and FET and also the determination of the frequency response and the bandwidth of various multistage amplifiers.

SYLLABUS

Multi stage Amplifiers, Method of Inter Stage Coupling, n-State Cascaded Amplifier, Equivalent Circuits, Miller’s Theorem, Frequency Effects, Amplifier Analysis, High Input Resistance Transistor Circuits. Cascode - Transistor Configuration, CE-CC Amplifiers, Two Stage RC Coupled JFET amplifier (CS), Difference Amplifier.

UNIT - IIIOBJECTIVE

It deals with the design of Transistor at High Frequencies, Determination of Hybrid-Phi parameters for various configurations and also Short Circuit Current Gain with and without Rl.

SYLLABUS

Transistor at High Frequencies, Hybrid-Phi CE Transconductance Model, Determination of Hybrid-Phi Conductance, Variation of Hybrid Parameters with IC, VCE and Temperature. The Parameters, expression for - b, Current gain with resistance load, CE Short Circuit Current Gain, Hybrid - Pi Parameters, Measurement of Ic, Variation of Hybrid-Pi Parameters with Voltage, Current and Temperature, Design of High Frequency Amplifier.

UNIT - IV OBJECTIVE

It deals with the design of various power amplifiers and determining efficiency, power output of various classes of power amplifiers and also discusses concepts of distortion.

SYLLABUS

Class A power amplifiers, Maximum Efficiency of Class A Amplifier, Transformer Coupled Amplifier, Transformer Coupled Audio Amplifier, push pull amplifier, Complementary Symmetry Circuits, Phase Inverters, Class D Operation Class S Operation, Heat Sinks.

UNIT – VOBJECTIVE

It deals with the design and analysis of various tuned amplifiers and various applications of the tuned amplifiers.

SYLLABUS

Single tuned Capacitive Coupled Amplifier, Tapped Single Tuned Capacitance Coupled Amplifier, Single Tuned Transformer Coupled, Inductively Coupled Amplifier, CE Double Tuned Amplifier, Applications of Tune Amplifiers.

UNIT-VIOBJECTIVE

It deals with the design and analysis of various tuned amplifiers of Class B and Class C and various Stability Considerations, design and analysis of Wideband Amplifiers

SYLLABUS

Stagger Tuning, Stability Considerations, Tuned Class B and Class C amplifiers, Wideband Amplifiers, Tuned Amplifiers.

UNIT-VIIOBJECTIVE

It deals with basic concepts of various voltage regulators, Voltage Multipliers, the design of and various Short Circuit Protection circuits

SYLLABUS

Terminology, Basic Regulator Circuit, Short Circuit Protection, Current Linking, Specification of Voltage Regulator Circuits, Voltage Multipliers.

UNIT-VIIIOBJECTIVE

It deals with basic concepts of various adjustable voltage regulators, design and analysis of IC 723 Voltage Regulators and Three Terminal IC Regulators.

SYLLABUS

IC 723 Voltage Regulators and Three Terminal IC Regulators, DC to DC Converter, Switching Regulators, Voltage Multipliers, UPS, SMPS.

7.6.4.ii SYLLABUS – GATE

Not applicable

7.6.4.iii SYLLABUS - IES

UNIT – 1Not Applicable

UNIT – IINot Applicable

UNIT – IIINot Applicable

UNIT – IV Power Amplifiers

UNIT – VTuned Amplifiers UNIT – VINot Applicable

UNIT – VIINot Applicable

UNIT – VIIINot Applicable

7.6.5 SUGGESTED BOOKS

TEXT BOOKS

T1 Electronic Circuit Analysis. – by A.P.Godse, U. A. Bakshi

T2 Integrated Electronics - by J. Millman and C.C. Halkias, McGraw-Hill,

T3 Electronic Devices and Circuits - by Theodere F. Bogart, Pearson edition.

T4 Electronic Circuit Analysis and Design - by Donald A. Neaman, McGraw Hill.

REFERENCE BOOKS

R1 Electronic Devices Circuits - by G. K. Mithal, Khanna Publications.

R2 Micro Electronic Circuits - by Serda A.S. and K.C. Smith, Oxford University Press.

R3 Micro Electronic Circuits : Analysis and Design - by M.H. Rashid, PWS Publications.

R4 Electronic Devices and Circuits - by K. Lal Kishore, B.S. Publications

R5 Principles of electronic circuits-PWS Publishing 2nd edition 1977Burns G Sand Bond PR.

R6 Microelectronic circuits and design—Prentice Hall 2nd edition 19967.6.6 WEBSITES

1. www.CircuitDesign.com2. www.uoquelph.ca/nantoon/circ3. www.reed.electronics.com4. www.ece.ufl.edu5. www.howstuff.work.com6. www.vlsi.com7. www.princeton.edu8. wwwl.stanford.edu9. www.yale.edu10. www.college.harvard.edu11. www.mit.edu.12. www.iitm.ac.in13. www.iitd.ac.in14. www.iitk.ac.in15. www.iitb.ac.in16. www.iitg.ernet.in17. www.iisc.ernet-in18. www.users.pandora.be/educypedia/electornics/radio tunning.htm19. www.electronics - tutorials.com20. www.lce.mcmaster.ca/courses/ee 3tr4/ee3tr4_Kumar.htm.21. www.radio-electronics.com22. www.radioelectronics school.com/raccourse.html.

7.6.7 EXPERT DETAILS

REGIONAL

1. Name : Prof. N. S. MurthyDesignation : Professor.Department : Dept of ECEOffice Address : National institute of Technology, Warangal.Phone No : +91-870-2459191E-mail Id : webmasters@nitw.ac.in

2. Name : L. Anjaneyulu M.Tech, (Ph.D) Designation : Sr. Lecturer,Department : Dept of ECEOffice Address : National institute of Technology, Warangal.Phone No : 91-870-2462435, 9440663561E-mail Id : anjan@nitw.ac.in

3. Name : T.V.K. Hanumantha RaoDesignation : Lecturer,Department : Dept of ECE

Office Address : National institute of Technology, Warangal.Phone No : Phone:+91-870-2459191, FAX : +91-870-

2459547E-mail Id : webmasters@nitw.ac.in

NATIONAL

1. Name : Prof. G.S VisveshwaranDesignation : Professor.Department : Department of Electrical EngineeringOffice Address : IIT Delhi, New Delhi, 110016Phone No : 91-11 26591077 E-mail Id : gswaran@ee.iitd.ac.in

2. Name : Prof. Pramod AgarwalDesignation : Professor.Department : Department of Electrical EngineeringOffice Address : IIT RoorkeePhone No : 91-1332E-mail Id : pramgfee@iitr.ernet.in

3. Name : Yatindra Nath SinghDesignation : Assistant Professor.Department : Department of Electrical EngineeringOffice Address : IIT KanpurPhone No : 91-512-259-7944E-mail Id : ynsing@iitk.ac.in

INTERNATIONAL

1. Name : Kameda YoshiniDesignation : Associate Professor.Department : Department of Intelligent Interaction TechnologyOffice Address : University of Tsukuba.Phone No : +81-29-853-5256 E-mail Id : kanda@iit.tsukuba.ac.jp

2. Name : Olev SolgardDesignation : Associate Professor.Department : Department of Electrical Engineering.Office Address : Stanford UniversityPhone No : (650) 724-2765 E-mail Id : solgard@stanford.edu

3. Name : Thomas. M.CoverDesignation : Professor.Department : Department of Engineering & Statistics.Office Address : Stanford UniversityPhone No : (650) 723-4505 E-mail Id : libveb@isl.stanford.edu

7.6.8 JOURNALS

1. Name of the Journal : Transactions of Electron Devices.Publisher : IEEE Publications

2. Name of the Journal : Transactions on Circuits and systems.

Publisher : IEEE Publications

3. Name of the Journal : Transactions on Power Electronics.Publisher : IEEE Publications

4. Name of the Journal : Transactions on VLSI SystemsPublisher : IEEE Publications

5. Name of the Journal : transactions on Circuits and SystemsPublisher : IEEE Publications

6. Name of the Journal : IEEE journal of Solid-State CircuitsPublisher : IEEE Publications

7. Name of the Journal : International Journal of ElectronicsPublisher : Taylor & Francis Ltd

7.6.9 RECENT FINDINGS AND DEVELOPMENTS

1. Title : Metal gate work function on gear leakage of MOFFETSAuthor : Tony Low and Dim Lee and WongJournal : IEEE Transactions on electronic devicesVol, Year & Pg. No. : vol & Pg.No. 50, January 2004

2. Title : Fabrication and characterization of High current gain (ß = 450) and High Power (23A – 500V) Darlington BJT

Author : Y.Leo, J.JhangJournal : IEEE Transactions on electronic developmentVol, Year & Pg. No. : vol & Pg.No. 50, January 2004

3. Title : Statistical model for extracting geometric source of transistor performance variation. Sean J.N.A

Author : JHON.R. BREWSJournal : IEEE Transactions on electronic developmentVol, Year & Pg. No. : vol & Pg.No. 52, July, 2003

4. Title : Noise model of gate leakage currents in ultra thin oxide MOSFETS Author : J.Lee, G.LosmalJournal : IEEE Transactions on electronic developmentVol, Year & Pg. No. : vol & Pg.No. 50, December, 2003

7.6.10 SESSION PLAN

Sl. No.

Topics in JNTU Syllabus

Modules and Sub modules

Lecture No.

Suggested Books Remarks

UNIT – 1 – SINGLE STAGE AMPLIFIERS (No. of Lectures – 09)1. Introduction L1 T1 (P:118-125)

2.Review Small Signal Analysis of Junction Transistor

TransistorVarious configurationsSmall Signal Analysis

L2T1-Ch1 (P:1.1)T2-Ch8 (P:233-237)R1-Ch3 (P:74)

3.Frequency response of Common Emitter Amplifier

Common Emitter Amplifier

Determination of Voltage gain, current gain, i/p, o/p impedanceFrequency response

L3L4

T1-Ch1 (P:1.1-1.3)T2-Ch5 (P:237-245)T3-Ch6 (P:204-231)R1-Ch3 (P:74)

4. Common Base Amplifier

Common Base AmplifierDetermination of voltage gain, current gain i/p, o/p impedanceFrequency response

L5

T1-Ch1 (P:1.6) T2-Ch.8 (P:233-274)T3-Ch5 (P:216)R1-Ch3 (P:94-96)

5.Common Collector Amplifier,

Common Collector amplifier

Determination of voltage gain, current gain, i/p, o/p impedanceFrequency response

L6

T1-Ch1 (P:1.5) T2-Ch11 (P:348-367)T3-Ch7 (P:226-230)R1-Ch3 (P:91-94)

6.JFET Amplifiers Common Drain Amplifier

Common Drain AmplifierDetermination of voltage gain, current gain, i/p, o/p impedanceFrequency response, Gain Band Width Product

L7

T1-Ch1 (P:1.63) T2-Ch11 (P:348-370)T3-Ch10 (P:261)R1-Ch4 (P:115-120)

7.Common Gate Amplifiers, Gain Band Width Product

Common Gate AmplifiersDetermination of voltage gain, current gain/ i/p, o/p impedanceFrequency response, Gain Band Width Product

L8L9

T1-Ch1 (P:1.66)T2-Ch11 (P:348-370)T3-Ch7 (P:263)

UNIT-II - MULTISTAGE AMPLIFIERS (No. of Lectures – 09)

8.Multistage Amplifiers, Method of Inter stage Coupling

Introduction, classification on the basis of coupling, comparison

L10

T1-Ch2 (P:2.2) T2-Ch12 (P:395-401)T3-Ch11 (P:189-193)R1-Ch6 (P:153-156)

9. N-State Cascaded Amplifier

N-State Cascaded Amplifier Voltage Gain, Current Gain, Power Gain, Input

L11L12

T1-Ch2 (P:2.2) T2-Ch12 (P:395-401)T3-Ch11 (P:189-193)R1-Ch6 (P:153-156)

and Output impedance

10.Equivalent Circuits, Miller’s Theorem

Equivalent Circuits, Miller’s Theorem

L13T1-Ch2 (P:2.63)

11.Two Stage RC Coupled JEFT amplifier (CS)

Two stage RC coupled amplifier –

OperationDetermination of current gain, voltage gain in low, mid frequency. Range

L14T1-Ch2 (P:2.31)T2-Ch12 (P:255)

12.Frequency Effects, Amplifier Analysis

RC coupled two stage amplifier –

High frequency rangeEffect of miller capacitanceLow frequency, high frequency response

L15L16

T1-Ch2 (P:2.42) T2-Ch12 (P:388)T3-Ch11 (P:232)R1-(P:173-184)

13.

High Input Resistance Transistor Circuits.Cascode – Transistor Configuration

Cascode – Transistor Configuration

OperationDetermination of Current Gain, voltage gain in low, mid frequency range

L17T1-Ch2 (P:2.17) T2-Ch12 (P:401)T3-Ch11 (P:349)

14.CE-CC Amplifiers Difference Amplifier

Difference Amplifier, CE-CC Amplifiers

OperationDetermination of current gain, voltage gain in low, mid frequency range

L18T1-Ch2 (P:2.23) T3-Ch11 (P:188)R1-(P:157-159)

UNIT-III – HIGH FREQUENCY TRANSISTOR CIRCUITS (No. of Lectures – 06)

15.

Transistor at High Frequencies, Hybrid-Phi CE Transconductance Model

Transistor at High Frequencies

Hybrid-Phi ModelCE Transconductance Model

L19

T1-Ch3 (P:3.1) T2-Ch11 (P:348-350)T3-Ch7 (P:345-348)R1-(P:135-139)

16.

Determination of Hybrid-Phi Conductances Variation of Hybrid Parameters with IC, VCE and Te

Determination of Hybrid-Phi ConductancesVariation of Hybrid Parameters with IC, VCE and Temperature

L20

T1-Ch3 (P:3.3) T3-Ch11 (P:350)T3-Ch7 (P:243-245)R1- (P:135-139)

17.Current gain with resistance load, CE Short Circuit Current Gain

CE Hybrid pi modelModel Current gain with resistance loadCE Short Circuit Current Gain

L21

T1-Ch3 (P:3.10) T2-Ch11 (P:359)R1-(P:135)

18. Hybrid – Pi Parameters, Measurement of IC

Hybrid – Pi ParametersMeasurement of IC of High Frequency

L22 T1-Ch3 (P:3.3) T2-Ch11 (P:355-358)T3-Ch7 (P:245-249)R1-(P:135-139)

Amplifier

19.Variation of Hybrid-Pi Parameters with Voltage, Current and Temperature

Variation of Hybrid-Pi Parameters with Voltage, Current and Temperature

L23T1-Ch3 (P:3.11) T3-Ch7 (P:323) R1-(P:135-144)

20.Design of High Frequency Amplifier

Design of High Frequency Amplifier

L24T1-Ch3 (P:3.21)T2-Ch11 (P:367)R1- (P:193-198)

UNIT-IV - POWER AMPLIFIERS (No. of Lectures – 10)

21.Class A power Amplifier Maximum Efficiency of Class A Amplifier

Class A series fed power amplifier

Efficiency, maximum powerProblems

L25

T1-Ch4 (P:4.6) T2-(P:674)T3-(P:643-644)R1-(P:193-198)

IES

22.

Transformer Coupled Amplifier, Transformer Coupled Audio Amplifier

Transformer coupled Class A power amplifier –

Operation, Circuit Analysis, EfficiencyProblems

L26T1-Ch4 (P:4.18) T2-(P:684)R1-(P:193-198)

23.Class B push pull power amplifier Crossover distortion

Class B push pull power amplifier

Power Output efficiencyCrossover distortion

L27

T1-Ch4 (P:4.38) T2-(P:692)T3-(P:653-655)R1-(P:199-204)

24.Complementary Symmetry Circuits

Class B Complimentary symmetry power amplifier

L28

T1-Ch4 (P:4.51)T2-(P:692)T3-(P:666-667)R1-(P:200)

25.Complementary Symmetry Circuits

Class B Complimentary Symmetry power amplifier

Operation, EfficiencyAdvantages, Disadvantages

L29L30

T1-Ch4 (P:4.51 T2-(P:693)R1-Ch7 (P:201-203)

26.Class D, Class S power Amplifiers

Class D power amplifiers Class S power amplifiers* Analysis and Design

L31T1-Ch4 (P:4.73) T3-(P:682)

27. Phase Inverters Phase Inverters L32 T1-Ch4 (P:4.79)

28.Design of Heat Sinks

Heat Sinks, Thermal Runaway

L33T1-Ch4 (P:4.67) T2-Ch9 (P:303-306)

Problems L34T1-Ch4 (P:4.80) T2-Ch9 (P:309)

UNIT-V - TUNED AMPLIFIERS-I (No. of Lectures – 06)

29.Single tuned Capacitive Coupled Amplifier

Single tuned Capacitive Coupled Amplifier* Analysis and Design of single tuned amplifier

L35L36

R1-(P:344-347)T1-Ch5 (P:5.1)

IES30.

Tapped Single Tuned Capacitance Coupled Amplifier

Tapped Single Tuned Capacitance Coupled Amplifier

Analysis and DesignFrequency Response

L37T1-Ch5 (P:5.17) R1-(P:347-351)

31.

Single Tuned Transformer Coupled, Inductively Coupled Amplifier

Single Tuned Transformer Coupled, Inductively Coupled Amplifier

Analysis and DesignFrequency Response

L38T1-Ch5 (P:5.18)R1-(P:351-355)

32.Double Tuned Amplifier, Applications of Tune Amplifiers

Double Tuned AmplifierAnalysis and DesignFrequency Response Applications of Tune Amplifiers

L39L40

T1-Ch5 (P:5.20)R1-(P:355-359)

UNIT – VI – TUNED AMPLIFIER-II (No. of Lectures – 05)

33. Stagger Tuning

Stagger Tuning Analysis and Design

Frequency ResponseProblems

L41T1-Ch6 (P:6.1)R1-(P:347)

IES34.

Class B and Class C tuned power amplifiers

Analysis and Design of Class B tuned amplifier

L42R1-(P:343)T1-Ch6-(P:6.7)

Analysis and Design of Class C tuned amplifier

L43R1-(P:345)T1-Ch6 (P:6.8)

35. Instability considerationsProblem of instability in RF tuned amplifiers* Stabilization techniques

L44L45

R1-(P:348)T1-Ch6(P:6.4)

UNIT-VII – VOLTAGE REGULATORS (No. of Lectures – 07)

36. Voltage Multipliers

Review of rectifiers and filters

Voltage multipliersMerits and Limitation

L46T2-(P:103)T3-Ch16 (P:52-54)R1-Ch1 (P:22)

37.Terminology, Basic Regulator Circuit

Zener voltage regulatorLoad and Line RegulationProblems

L47L48

T3-(P:54-56)

38. Short Circuit ProtectionSeries voltage regulator

Analysis and DesignMerits and Limitations

L49T1-Ch7 (P:7.10) T3-(P:516-522)

39. Current Linking

Shunt Voltage RegulatorOperation stability factorMerits and Demerits

L50T1-Ch7 (P:7.9) T3-(P:522-524)

40.Specification of Voltage Regulator Circuits

Specification of Voltage Regulator CircuitsProblems on series and shunt voltage regulator

L51L52

T3-Ch13 (P:528)

UNIT-VIII – SWITCHING AND IC VOLTAGE REGULATORS (No. of Lectures – 07)

41. Switching Regulators

Switching RegulatorsOperationDesignMerits and Demerits

L53 T3-Ch16 (P:525-528)

42.Three Terminal IC Regulators

Three Terminal IC regulators

Different TypesDesign Analysis

L54T3-Ch1 (P:528-534)

43.IC 723 Voltage Regulators

IC 723 Voltage Regulators Comparison Advantages, Disadvantages

L55L56

T1-Ch8 (P:8.6) T3-Ch16 (P:535)R1-Ch6 (P:40)

44. DC to DC Converter DC to DC ConverterOperation

L57 T2-Ch16 (P:572)T3- (P:513)

Design R1-Ch6 (P:42)

45. UPS, SMPS

UPS, SMPSOperationDesignMerits and Demerits

L58T1-Ch8 (P:8.67) R1-Ch6 (P:46)

7.6.11 TUTORIAL PLAN

Sl.No.

Date Topics scheduled Salient topics to be discussed

1 02-07-08Small signal Analysis. A junction transistor

H-parameter model, voltage gain current gain, input using output admantacnce with and without source resistant taken into account in the CB CE and CC configuration.

2 09-07-08 Junction FETJFET amplifiers, CD, CS CG, frequency response and gain bandwidth products.

3 16-07-08 Multistage AmplifierMethods into stage coupling, n-stage cascaded amplifiers, equivalent circuits, skills theorem.

4 23-07-08 Frequency effects. Gain, bandwidth, lower 3dB, upper 3db.

5 30-07-08Two stage RC coupled JFET amplifier

Voltage gain for mid frequencies, voltage gain at low frequency, voltage gain at high frequency.

6 07-08-08 Difference AmplifierDifferential mode of operation, common mode of operation, AD, AC CURR.

7 14-08-08 Class A power amplifierConcept of power amplifier, features class A, Class B, Class AB, comparison analysis of class A amplifier.

8 21-08-08 Push pull amplifierDC operation, DC power input, AC operation, AC power input, AC power input, efficiency.

9 18-09-08 Stagger tuned amplifier Neutralization.

10 25-09-08Tuned class B and class C amplifier.

Class B, Class C applications of Class B, Class C.

11 16-10-08 Voltage RegulatorTerminology, basic regulator circuit short circuit protection, current limiting.

12 30-10-08Switching and RC voltage regulator

IC 723 voltage regulator, and three terminal voltage regulator

7.6.12 STUDENT SEMINAR TOPICS

1. Title : Specific Analog Electronic Circuit Analysis using PC Based Acquisition Card

Author : M.A. DrirnitrineviJournal : Computer as Tools Vol, Year & Pg. No. : Eurocon 2005. Volume:2 Pg:910-913 – Nov 2005

2. Title : Computer aided design of an RF Mosfet Power amplifierAuthor : G.A.Hoile and H.C.ReaderJournal : Circuits devices and system, IEEEVol, Year & Pg. No. : Dec 1994,vol:141 issue 6 pg:433-536

3. Title : Current Transistor-transistor – inductor oscillatorAuthor : J.C.CommercanJournal : IEEE JournalVol, Year & Pg. No. : Dec 1994,vol:141 , issue 6 Pg: 498-504

4. Title : Modular spice macro model for operational amplifierAuthor : M.E.Brinsan and D.J.FaulknerJournal : Circuits devices and systemsVol, Year & Pg. No. : 1994,vol:141 , issue 5, Pg: 417-420

5. Title : Realization of analogue divider using current feedback amplifier

Author : S I Liu and J.JactonJournal : circuits, devices and SystemVol, Year & Pg. No. : Feb 1995 , Vol:142 , issue 1, Pg 45-48

7.6.13 QUESTION BANK

1. a. Draw the circuit of an Emitter follower and its equivalent circuit. List out its characteristics.b. Desing a single stage Emitter follower having Ri = 500 K Ω and R0 = 20Ω. Assume hfe = 50, hie =

1K, hoe = 25 A/V. (JNUT Feb 08)

2. a. Draw the circuit diagram and low frequency equivalent circuit of commin source amplifier and derive an expression for its voltage gain.

b. For the emitter follower circuit with RS = 0.5K and RL = 5K, calculate AI, Ri, AV, AVS, and R0. Assume hfe = 50, hie = 1 K, hoe = 25 A/V. (JNUT Feb 08)

3. a. Derive the expression for Ai,Av of CE amplifier circuit Explain how Ai and Av are affected by RL. b. Consider a single stage CE amplifier with Rs=1K,R1=50K, R2=2K, Rc=1K, RL=1.2K, hfe=50, hie=1.1K, hre=hoe=0; Find Ai, Ri, Ro, Av and power gain (JNTU Feb 07)

4. a. For a single stage transistor amplifier, Rs =10K and RL = 10K, The h parameter values are hfc = -51 , hic = 1.1 k ohm, hrc = 1, hoc = 25µA/V. Find Ai,Av,Avs,Ri,and Ro for the CC transistor configuration.b. For a single stage transistor amplifier, Rs=1K, and Rl=10K.The h-parameter values are hfe=50,

hie=1.1K, hre=2.5x10-4,hoe=25µA/V.Find Ai,Av,Avs,Ri and Ro for the CE configuration (JNTU Feb 07)

5. a. Draw the circuit diagram of CB amplifier and h-parameter equivalent circuit. List out the characteristics of a CB amplifier. (JNTU Feb 07)

b. In a single stage CB amplifier circuit, RE=20K,Rc=10K,VEE=-20,Vcc=20V,RL=10K and Rs=0.5K. Find Ai,Ri,Ro,Av (JNTU Feb 07)

6. a. For a single stage transistor amplifier Rs=200 and RL=5K. The h-parameter values are hfb=-0.98, hib = 21 ohms , hrb=2.9x10-4, hob=0.49µA/V . Find A, Av, Avs,Ri,and Ro for the CB

transistor configuration

b. For a single stage transistor amplifier , Rs=1K ,and Rl=10K.The h-parameter values are hfe=50,hie=1.1K,hre=2.5x10-4,hoe=25 µA/V.Find Ai,Av,Avs,Ri and Ro for the CE configuration

(JNTU Feb 07)

7. Draw the basic circuit of CS amplifier with load resistor Rd in the drain circuit and an additional resistor Rs in the source to ground circuit. Draw its small signal low frequency equivalent circuit

(JNTU Mar 06)

8. Draw the h-parameter equivalent circuit of CC, CE configuration and what are the typical values of h-parameters for a transistor in CE and CB configuration. (JNTU Mar 06)

9. i. Draw ac equivalent circuit for a CE amplifieri. with a bypassed emitter resistor andii. with an unbypassed emitter resistor. Briefly explain each circuit. (JNTU Mar 06)

ii. Using the approximate h-parameter model, derive expressions for current gain, input resistance, voltage gain and output admittance of a CE amplifier with a resistor in emitter circuit. (JNTU Nov 05)

10. Give the typical values for h-parameters of CC configuration. Prove that Yo = ho ffRs+Ri1 Rs+Rio ff Where Ri1ff Ri for RL = 1,and Rioff Ri for RL = 0. (JNTU Nov 05)

11. i. For a CE amplifier, what is the maximum value of Rs for which Ro differs by not more than 10% of its value for Rs = 0 ? Given hie = 1.1K, hfe = 50, hre= 2.5 x 10-4, hoe = 25µA/V.

ii. Derive the condition to obtain AV =1 in CC single stage amplifier. (JNTU Nov 05)

12. Derive the expression for Ai, Ri, AV and Ro. 16Calculate Ai,Ri,Av and Ro for the above CB amplifier, with RL=5k, RS=500 ohms, hfe=50, hie=1k, hoe = 50k, RE = 10k and Re = 10k (JNTU Nov 05)

13. i. Sketch CS amplifier using JFET and draw its small signal equivalent circuit.ii. In the above circuit, if VDD = 20 V, IDSS = 3mA, VP = -2.4V, rd = 10 k, RD = 10 k, RG = 1 M,

RS = 470Ω, determine AV, gm, VDS, ID and VGS. (JNTU

Apr 04)14. i. Draw AC equivalent circuit for a CE amplifier

(i) with a bypassed emitter resistor and (ii) with an unbypassed emitter resistor. Briefly explain each circuit.

ii. Using the approximate h-parameter model, derive expressions for current gain, input resistance, voltage gain and output admittance of a CE amplifier with a resistor in emitter circuit.

(JNTU Apr 04)

15. i. Draw the basic circuit of CS amplifier with load resistor Rd in drain circuit and an additional

resistor Rs in the source to ground circuit.ii. Draw its small signal low frequency equivalent circuit.iii. Derive expressions for voltage gain and output resistance. (JNTU Apr 04)

16. i. Draw a typical CE amplifier and explain the function of each component in it.ii. Design a single stage CE amplifier to meet the following specifications, Ri = 1k,

R0 = 2k, Av = 100, fL = 50 Hz, fH = 100 KHz. (JNTU Apr 04)

17. For the emitter follower with Rs = 0.5 K and RL = 5K, calculate Aj, Rj, Av, Avs and RO. Assume

hfe = 50, hie = IK, hoe = 25uA/V. (JNTU Nov 04)

18. Draw the circuit diagram and Low frequency equivalent circuit of common source amplifier and derive an expression for its voltage gain. (JNTU Nov 04)

19. i. What is swamping resistor? What are its effects when used in CS amplifier circuit? Explain clearly.

ii. Design 1 -stage emitter follower having Ri = 500 KΩ. and RO = 20Ω. Assume hfe = 50, hie = 1K, hoe = 25 micro-amp/ V. (JNTU Nov 04)

20. i. Derive the expressions for transconductance and input conductance of CE amplifier using HF model.

ii. The following LF parameters are known for a given transistor at Ic = 10 mA, VCE=5V and at

room temperature hie = 500Ω, hoe = 10-5A/V, hfe = 100, hre = 10-4. At the same operating point

ft = 50 MHz, and C0b = 3 PF, Compute the values of the entire hybrid -π parameter. (JNTU

Nov 04)

21. A JFET with the following parameters is used in a single stage common source amplifier with a load resistance of 100 k . Calculate the high frequency cut off (upper 3 dB cut off frequency) of the amplifier? (JNTU Nov 03)

Gm = 2.0 mA/V

Ggd = 2.0 pF

rd= 100 k

Cgd=2.0 pF

Cgd=1.0 Pf

22. i. Draw the circuit diagram of voltage series feedback and derive expressions for input and output resistances.

ii. For the circuit shown below hfe =100, hie=1 K and other two parameters are negligible if

Re=1k find the value of Av= Vo/ Vi, AVS = Vo/ VS, Rif and Rof (JNTU

Nov 03)

23. i. For the given circuit find Av, Rif and also resistance seen by VS, assume RC = 4k, R1 = 40k,

RS=10k and the transistor parameters are hie=1.1k, hfe=50, hre=0, 1/ hoe = 40 k (Assume

AV>>1)

ii. The gain of an amplifier is decreased to 1000 with –ve feedback from its gain of 5000. Calculate the feedback factor and the amount of –ve feedback in dBs. (JNTU Nov 03)

24. Draw the circuit diagram of CE amplifier with emitter resistance and obtain its equivalent hybrid model and derive expressions for AI, RI, AV with the approximate analysis (JNTU

Nov 03)

25. Determine AV, AI, RI, R0 for a CE amplifier using NPN transistor with hie = 1200, hre=0, hfe=36

and hoe = 2 x 10-6 mhos. RL = 2.5K , RS=500 (neglect the effect of biasing circuit)

(JNTU Nov 03)

26. Compare common collector and common emitter configuration with regard to RI, Ro, AI, and AV.

(JNTU Nov 03)

27. Draw the circuit diagram of CC amplifier using hybrid parameters and derive expressions for RI,

Ro, AI, and AV. (JNTU Nov 03)

28. i. Define the stability factors S, S1, S11 and what is the need of this in BJT circuits.(JNTU Apr 03)ii. Draw the circuit diagram of a self bias BJT circuit and how to determine the value of R1 and R2.

29. i. How to obtain Quiescent point graphically for a given transistor amplifier of CE configuration explain.

ii. Obtain frequency response of CE amplifier circuit and find out its bandwidth. What is the impact of CC and CS on the bandwidth? (JNTU

Apr 03)

30. i. Draw the circuit diagram of emitter follower using NPN transistor and derive expression for RI,

Ro, AI, and AV using hybrid model. (JNTU Apr 03)

ii. Derive expression for the lower and upper cut-off frequencies of an n-stage amplifier

31. i. Draw the circuit diagram of a collector to base bias circuit of CE amplifier and derive expression for S.

ii. Determine the Quiescent currents and the collector to emitter voltage for a Ge transistor with h fe = 50 in self-biasing arrangement. Draw the circuit with a given component value with VCC= 20V,

RC=2k, Re = 5V, R1=100k and R2= 5k. Also find out stability factor. (JNTU

Apr 05)

32. Draw the circuit diagram of a collector to base bias circuit of CE amplifier and derive expression for S (JNTU Apr 05)

33. Determine the quiscent currents and the collector to emitter voltage for a germanium transistor with b=50 in self biasing arrangement. Draw the circuit with a given component value VCC =

20V, RC = 2K, Re = 100 ohms R1 = 100Kilo ohms R2 = 5K. Also find out stability factor.

(JNTU Apr 05)

34. i. What are the compensation techniques used for VBE and ICO. Explain with the help of suitable

circuits.ii. Draw the h-parameters equivalent circuit of CC, CE configuration and what are the typical values

of h-parameters for a transistor in CE and CB configuration. (JNTU Apr 03)

35. i. What is meant by thermal run away briefly explain?ii. What is the condition for thermal stability? (JNTU Apr 03)

36. Calculate the minimum value of VDS required for an NMOSFET to operate in pinch of condition

when VGS= 1 V, VP = -2 V, IDSS = 10mA also find the corresponding drain current. (JNTU

Apr 03)

37. Find the value of R1 in the amplifier circuit shown below such that the Quiescent drain to ground

voltage becomes 10 V. Assume IDSS = 2mA and VP = -1 V (JNTU

Apr 03)

38. A CE BJT amplifier has following circuit and transistor parameters: Rc=10K , RE=2K ,

hie=2k , hfe=60, hoe=10μV and hre=1x10-4. Assuming RE is adequately by passed by a

capacitor CE

, determine

i. Voltage gain ii. Current gain of the amplifier

39. Determine AV, AI, Ri, Ro and the power gain for a CE amplifier using a transistor with hie=1200,

hfe=36, hre=0, hoe=2x10-6mho, use RL=2500 source resistance RS=500 , neglect the effect

of the biasing circuit.

40. An RC couple amplifier has a gain of 100 in the frequency range of 400Hz to 25KHz, on either side of these frequencies the gain falls so that it is reduced 3dB at 80Hz and 40KHz. Calculate gain in dB at cutoff frequencies and construct a plot of frequency response curve.

41. Write the general equation in terms of h-parameters for a BJT in CB amplifier configuration and

define h-parameters?

42. The following test results were obtained in a CE amplifier circuit while measuring h-parameters experimentally.

i. With AC output shorted, Ib=20m A, Ic=1mA, Vbe=22mV and Vce=0.

ii. With AC output open-circuited Ib=0, Vbe=0.25mV, Ic=30μA and Vce=1V.

Determine hybrid parameters of the given transistor.

43. A junction transistor has the following h-parameters hie=2000, hre=1.6x10-4 hfe=49,

hoe=50μA/V. Determine the current gain, voltage gain, input resistance and output resistance of

the CE amplifier if the load resistance is 30K and the source resistance is 600 ?

44. A BJT has hie=2K , hfe=100, hre=2.5x10-4 and hoe=25μA/V as parameters in CE

configuration, It is used as an emitter follower amplifier with Rs=1K and RL=500 .

Determine for the amplifieri. Voltage gain Avs=Vo/Vs ii. Current gain Ais=Io/Ioiii. Input resistant Ri iv. Output resistance Ro

45. Design 1 -stage emitter follower having Ri = 500 KΩ. and RO = 20Ω. Assume hfe = 50, hie =

1K, hoe = 25 micro-amp/ V. (JNTU

Nov 03)

46. Obtain frequency response of CE amplifier circuit and find out its bandwidth. What is the impact of CC and CS on the bandwidth? (JNTU

Apr 03)

47. Determine the Quiescent currents and the collector to emitter voltage for a Ge transistor with = 50 in self-biasing arrangement. Draw the circuit with a given component value with VCC= 20V,

RC=2k, Re = 5V, R1=100k and R2= 5k. Also find out stability factor. (JNTU

Apr 05)

48. i. What is swamping resistor? What are its effects when used in CS amplifier circuit? Explain clearly.

ii. Design 1 -stage emitter follower having Ri = 500 KΩ. and RO = 20Ω. Assume hfe = 50, hie = 1K, hoe = 25 micro-amp/ V. (JNTU Nov 04)

49. i. Derive the expressions for trans conductance and input conductance of CE amplifier using HF model.

ii. The following LF parameters are known for a given transistor at Ic = 10 mA, VCE=5V and at

room temperature hie = 500Ω, hoe = 10-5A/V, hfe = 100, hre = 10-4. At the same operating point

ft = 50 MHz, and C0b = 3 PF, Compute the values of the entire hybrid -π parameter. (JNTU

Nov 04)

50. i. Draw ac equivalent circuit for a CE amplifieri. with a bypassed emitter resistor andii. with an unbypassed emitter resistor. Briefly explain each circuit.

ii. Using the approximate h-parameter model, derive expressions for current gain, input resistance, voltage

gain and output admittance of a CE amplifier with a resistor in emitter circuit. (JNTU Nov 05)

51. Determine AV, AI, Ri, Ro and the power gain for a CE amplifier using a transistor with

hie=1200Ω, hfe=36, hre=0, hoe=2x10-6mho, use RL=2500Ω source resistance RS=500Ω, neglect

the effect of the biasing circuit.

52. An RC couple amplifier has a gain of 100 in the frequency range of 400Hz to 25KHz, on either side of these frequencies the gain falls so that it is reduced 3dB at 80Hz and 40KHz. Calculate gain in dB at cutoff frequencies and construct a plot of frequency response curve.

53. A junction transistor has the following h-parameters hie=2000Ω, hre=1.6x10-4 hfe=49,

hoe=50μA/V. Determine the current gain, voltage gain, input resistance and output resistance of

the CE amplifier if the load resistance is 30KΩ and the source resistance is 600Ω?

54. Define the stability factors S, S1, S11 and what is the need of this in BJT circuits.(JNTU Apr 03)

55. Draw the circuit diagram of a self bias BJT circuit and how to determine the value of R 1 and R2.

(JNTU Apr 03)

56. Compare common collector and common emitter configuration with regard to RI, Ro, AI, and AV.

(JNTU Nov 03)

57. Draw the circuit diagram of CC amplifier using hybrid parameters and derive expressions for RI,

Ro, AI, and AV. (JNTU Nov 03)

58. Draw ac equivalent circuit for a CE amplifieri. with a bypassed emitter resistor andii. with an unbypassed emitter resistor. Briefly explain each circuit. (JNTU Nov 03)

59. Using the approximate h-parameter model, derive expressions for current gain, input resistance, voltage gain and output admittance of a CE amplifier with a resistor in emitter circuit. (JNTU Nov 05)

60. For the amplifier of Fig., IC=1.3 mA, RC=2kΩ, RE=500 Ω, VT=T/q = 26 mV, hfe =100, VCC=15

V vs=0.001 sin(wt) V and Cb=Ce=10 F

61. Draw the circuit diagram of CC amplifier using hybrid parameters and derive expressions for Av, Av0, Ri, R0

UNIT – II

1. a. Derive the expression for the low 3-dB frequency f of n-identical non interacting stages in terms

of fL for one stage.b. If four identical amplifiers are cascaded each having fL = 100Hz, determine the overall lower 3dB

frequency f . Assume non interacting stages.

c. Write a short note on Gain-Band width product of amplifiers. (JNTU Feb 08)

2. For a two stage FET RC Coupled amplifier has the following parameters; gm=10mA/V,rd=5.5K and Rg = 0.5 M for each stage . Assume Cs as arbitrarily large.

a. What must be the value of Cb in order that the frequency characteristics of each stage be flat within 1 dB down to 10HZ?

b. Repeat the above part if the overall gain of both stages is to be down 1 dBat 10 HZ. (JNTU Feb 07)

3. a. State Millers Theorem. Explain its significance in transistor circuit analysis.b. For the amplifier shown in fig Calculate Ri,RI,Av and Avs, A’i=-I2/I1. The h- parameter values

are hfe=50,hie=1.1K, hre=2.5x10-4 , hoe=24 μA/V (JNTU Feb 07)

4. a. How are multistage amplifiers classified depending upon the type of coupling. b. Write a note on distortions in amplifiers

c. If eight identical amplifiers are cascaded each having f H=200KHZ, Determine the overall upper 3dB frequency f h. Assume non interacting stages. (JNTU Feb 07)

5. a. How are multistage amplifiers classified depending upon the type of coupling. b. Write a note on gain – bandwidth product of amplifiers. c. If eight identical amplifiers are cascaded each having f H=100KHZ, Determine the overall upper

3dB frequency f h. Assume non interacting stages. (JNTU Feb 07)

6. i. The gain of an RC coupled 2 stage FET amplifier falls by 90% of the midband value at 400 kHz. If gm of each FET is 10 m A/V, and total output capacitance for each stage is 20 pF. Calculate the RL required and the midband gain of each stage Write a short note on Bandwidth of amplifiers.

(JNTU Apr 06)

7. i. Obtain the theoretical expressions for f1n and f2n when n-stages of identical amplifiers are cascaded.

ii. For a given transistor (BJT), hfe = 100. fB = 5 KHzs. Determine the Bandwidth of the transistor. If the

lower cut off frequency f1 = 100 Hzs and upper cut off frequency f2 = 100 KHzs, then determine the midband frequency f0 of the amplifier circuit. (JNTU Apr 06)

8. i. Three identical non interacting amplifier stages in cascade have an overall gain of 0.3dB down at 50 kHz compared to midband. Calculate the upper cutoff frequency of the individual stages.ii. Write a note on distortions in amplifiers (JNTU Apr 06)

9. Analyze the two stage cascaded amplifier circuit. Obtain the expression for the Gain-Band width product of the circuit. (JNTU Apr 06)

10. Five identical stages are coupled, each amplifier having f2 = 100 KHzs. Determine the overall upper cut-off frequency for the five stages. (JNTU Apr 06)

11. i. How is the High frequency gain of a single stage amplifier dependent on frequencies f1 and f2.ii. In an RC-coupled BJT amplifier, we have RL=6.8k, effective ac load after Cc is Rac=1k, Cc=1 µ

f, CE=24µF, RE=2.2k, hfe =49, RS=5k and hie=1k, find the low frequency cut off point.(JNTU Apr 06)

12. Draw High frequency model of an RC coupled amplifier, and derive the expression for voltage gain.

(JNTU Nov 05)

13. i. Draw ac equivalent circuit for a CE amplifieri. with a bypassed emitter resistor andii. with an un bypassed emitter resistor. Briefly explain each circuit.

ii. Using the approximate h-parameter model, derive expressions for current gain, input resistance, voltage gain and output admittance of a CE amplifier with a resistor in emitter circuit.

(JNTU Nov 05)

14. How is the High frequency gain of a single stage amplifier dependent on frequencies f1 and f2.(JNTU Nov 05)

15. A RC-coupled BJT amplifier, we have RL=6.8k, effective ac load after Cc is Rac=1k, Cc=1 µ f, CE=24µF, RE=2.2k, hfe =49, RS=5k and hie=1k, find the low frequency cut off point.

(JNTU Nov 05)

16. Obtain the theoretical expressions for f1n and f2n when n-stages of identical amplifiers are cascaded.

(JNTU Nov 05)17. For a given transistor (BJT), hfe = 100. fB = 5 KHzs. Determine the Bandwidth of the transistor. If the

lower cut off frequency f1 = 100 Hzs and upper cut off frequency f2 = 100 KHzs, then determine the

midband frequency f0 of the amplifier circuit. (JNTU Nov 05)

18. i. What are the specifications of amplifiers? Explain them. Give their typical values.

ii. The LF parameters of a transistor at Ic = 20mA, Vce = 10V and at room temperature hie = 400 Q,

h^ = 10 “5 A/V , hfe - 150, hre = 10-4 . At the same operating point fT =60 mHZ, and C0b = 3PF ,

compute the values of all the hybrid π parameters (JNTU Nov 04)

19. i. Draw the circuit of two stages R-C coupled JFET amplifier and explain its working. ii. If six identical R-C coupled amplifiers are cascaded each having f1 = 100 Hz, determine the

overall f1. (JNTU

Nov 04)

20. i. Three identical non interacting amplifier stages in cascade have an overall gain of 0.3dB down at 50 kHz compared to mid band. Calculate the upper cutoff frequency of the individual stages.

ii. Write a note on distortions in amplifiers. (JNTU Nov 04)

21. i. Compare different types of amplifier circuits based on the type of coupling. ii. Design a class A transformer coupled amplifier using a BJT to deliver 100 mw of audio power

into 8Ω load. At the operating point IB-250 uA. VCC=16V. The collector dissipation should not

exceed 200mw. RL=lkΩ. Make reasonable approximations wherever necessary. (JNTU Nov 04)

22. i. Derive the relation between f1 and f1n when such n-identical amplifier stages are cascaded.

ii. For a given single stage amplifier, f2= 100 KHz. If 8 of such stages are cascaded, determine the

overall f2, for such a configuration. (JNTU Apr 04)

23. i. Derive the relation between f2 and f2n, when such n identical amplifier stages are cascaded.

ii. Draw high frequency model of an RC coupled amplifier and derive the expression for voltage gain. (JNTU Apr 04)

24. i. Draw the circuit for two stages R-C coupled JFET amplifier and explain its working.ii. If six identical R-C coupled amplifiers are cascaded each having f1 = 100 Hz, determine the

overall f1.

(JNTU Apr 04)

25. i. Obtain the theoretical expressions for f1n and f2n when n-stages of identical amplifiers are

cascaded.ii. For a given transistor (BJT), hfe = 100, fB = 5 KHz. Determine the Bandwidth of the transistor.

If the lower cut off frequency f1 = 100 Hz and upper cut off frequency f2 = 100 KHz, then

determine the mid band frequency f0 of the amplifier circuit.

(JNTU Apr 04)

26. i. The gain of an RC coupled 2 stage FET amplifier falls by 90% of the midband value at 400 kHz. If gm of each FET is 10 m A/V, and total output capacitance for each stage is 20 pf. Calculate the RL

required and the stage midband gain. ii. Write a short note on Bandwidth of amplifiers. (JNTU Apr 04)

27. i. How is high frequency gain of a single stage amplifier depended on the frequencies f1 & f2.

ii. In an RC coupled BJT amplifier we have Rl = 6.8K, effective AC load after Cc is Rac = 1 K, Cc =

1 micro farad, Ce = 24 micro farad, Re = 2.2K, hfe = 49, Rs = 5K and hie = 1K, find the low

frequency cut off point. (JNTU Nov 03)

28. i. The gain of an RC coupled two stage FET amplifier falls by 90% of the mid band value at 400 KHz. If gm of each FET is 10 milli Amps per volt, the total output capacitance of each stage is

20pf. Calculate the Rl required and the stage mid band gain.

ii. Write a short note on Bandwidth of amplifiers. (JNTU Nov 03)

29. i. Three identical non-interacting amplifier stages in cascade have an overall gain of 0.3dB down at 50KHz. Compared to mid band. Calculate the upper cut off frequency of the individual stages.

ii. Write a note on distortion in amplifiers. (JNTU Nov 03)

30. In the cascade amplifier circuit shown in Fig., determine the values of R1, R2 and RL such that the

quiescent current through the transistors is 1mA and the collector voltages are VC=3 V and VC2 =

6V, Table VBE=0.7V, transistor to be high and base currents to be negligible. (JNTU

Nov 03)

31. Fig. shows a 2-state amplifier. The transistors Q1 and Q2 are identical with current gain hfe=100;

furtherVdc=Vac=. The zener diode Dz has a break-down voltage Vz=10.7 volt. Assume that Dz is

in breakdown region and its dynamic resistance rz is zero. The capacitors C1 and C2 are large and

provide negligible impedance at signal frequencies. (JNTU Nov 03)

i. Identify the configuration in each of the amplifier stages (i.e. whether CE, CC, CB etc.)ii. Determine the quiescent quantities IC1 and VC1.

iii. Derive an expression for the voltage gain AV VO/VR and determine its value.

(Assume VBE = 0.7 V, r0=0 and Thermal voltage VT = 25 mV)

32. The input power to an amplifier is 15mW while Output power is 2 Watts. Find the decibel gain of the amplifier.

33. What is the dB gain for an increase of power level from 12Watts to 24mWatts?

34. What is the dB gain for an increase of voltage from 4mV to 8mV?

35. A two stage amplifier has first stage voltage gain of 20 & second stage voltage gain of 00. Find the total decibel gain.

36. A multistage amplifier consists of three stages, the voltage gains of the stages are 30, 50 & 60. Calculate the overall gain in dB.

37. In an RC coupled amplifier, the mid frequency gain is 2000. What will be its value at upper & lower cut off frequencies?

38. A 3 stage amplifier employs RC coupling. The voltage gain of each stage is 50 & Rc=5Kohm for each stage. If input impedance of each stage is 2Kohm, find the overall decibel voltage gain.

39. We are to match a 16 ohm speaker load to an amplifier so that the effective load resistance is 10 Kohm. What should be the transformer turn ratio.

40. Explain direct coupled transistor amplifier.

41. How will you achieve impedance matching with transformer coupling?

42. With a neat circuit diagram, explain the working of transformer- coupled transistor amplifier.

43. Why does transformer coupling give poor frequency response?

44. Why does RC coupling give constant gain over mid-frequency range?

45. Write a short note on Bandwidth of amplifiers. (JNTU Nov 03)

46. i. Fig. shows a 2-state amplifier. The transistors Q1 and Q2 are identical with current gain hfe =100;

further idc=iac=. The zener diode Dz has a break-down voltage Vz=10.7 volt. Assume that Dz is

in breakdown region and its dynamic resistance rz is zero. The capacitors C1 and C2 are large and

provide negligible impedance at signal frequencies. (JNTU Nov 03)

ii. Determine the quiescent quantities IC1 and VC1.

iii. Derive an expression for the voltage gain AV = VO/VR and determine its value.

(Assume VBE = 0.7 V, rd = 0 and Thermal voltage VT = 25 mV)

45. Write a short note on Bandwidth of amplifiers. (JNTU Nov 03)

46. Explain the need of cascading amplifiers?

47. Draw and explain the block diagram of two stage cascading amplifier

48. Draw and explain the block diagram of n stage cascading amplifier.

49. Explain the significance of representing in gain in decibels?

50. Explain the selection of configuration of multi stage amplifier?

51. What is the effect of cascading on gain?

52. What is the effect of cascading on frequency response and bandwidth?

53. What is the effect of coupling and bypass capacitor on freq response of RC-coupled amplifier?

54. Write a short note on Miller’s theorem?

55. Explain any one circuit which is used to improve the i/p impedance of the amplifier?

56. What is Darlington Connection? Explain its advantage?

57. Why darlington connection cannot be used for more number of stages?

58. Explain the concept of bootstrapping?

59. Derive the expression for Ai ,Ri,Av and Ro of Bootstraped darligton circuit?

60. Derive the relation between f2 and f2n when such, n-identical amplifier stages are cascaded.

UNIT – III

1. a. Draw Hybrid - model for a transistor in the CE configuration and explain the significance of every component in this model.

b. Given a germanium p-n-p transistor whose basewidth is 10 -4 cm. At room temperature and for a dc emitter current of 2 mA, find

i. emitter diffusion capacitance,ii. fT [Assume Diffusion constant as 47 cm2 / sec]. (JNTU Feb 07)

2. a. Prove that in Hybrid- II model, the diffusion capacitance is proportional to the emitter bias current.b. In Giacolletto model of a transistor at high frequencies, how does Ce vary with I Ic I and I vce I?

How does Cc vary with I Ic I and I vce I (JNTU Feb 07)

3. a. Derive various resistive parameters of Hybrid – II model of a transistor in terms of h parameters.b. What is the relationship between fT and FB? Discuss the significance of fT. (JNTU Feb 07)

4. a. Draw the small signal equivalent circuit for an emitter follower stage at high frequencies.b. Consider a CE stage with a resistive load RL. Using Millers theorem Find out input capacitance at

mid band frequencies and high frequencies. (JNTU Feb 07)

5. a. In Hybrid – II model of a transistor at high frequencies, show that gm is proportional to the collector currentb. Define fT and what is physical significance of fT ? If a silicon p-n-p transistor has an fT=400

MHz. What is the base thickness? Assume Diffussion Constant as 13 cm2/sec (JNTU Feb 07)

6. i. Explain the principle of operation of basic CE amplifier circuit. Mention important characteristics

of CE amplifier. ii. For the 1-stage CE amplifier circuit shown in figure1. calculate Ri, Ro, Ai, Av and power gain in dB. Take β = 50, γe = 25 mv/IE (JNTU Mar 06)

7. i. What is the order of magnitude of each resistance in the hybrid π-mode ? ii. Explain why the 3dB frequency for currenct gain is not same as fH for voltage gain. iii. Draw the small-signal equivalent circuit for an emitter follower stage at high frequencies.

(JNTU Mar 06)

8. i. What is the order of magnitude of each resistance in the hybrid π-mode ?ii. Explain why the 3dB frequency for currenct gain is not same as fH for voltage gain.iii. Draw the small-signal equivalent circuit for an emitter follower stage at high frequencies.

(JNTU Mar 06)

9. i. Draw the basic circuit of CS amplifier with load resistor Rd in the drain circuit and an additional resistor Rs in the source to ground circuit. Draw its small signal low frequency equivalent

circuitii. The amplifier shown in figure1 utilizes an N-channel FET for which VP = -2v and IDSS=

0.8mA.It is desired to bias the circuit at ID=0.8mA using VDD=24v. Assume rd>>RD. Find VGS ,gm , RS, Rd ch that voltage gain is at least 20dB with RS bypassed with a very large capacitance CS.

(JNTU Mar 06)

10. i. Explain how the parameters of hybrid-π model varies with IC, VCE and temperature.ii. The hybrid-π parameters of the transistor used in circuit are : gm = 50mA/V, rbb’=100, rb’e= 1K,

rb’c = 4M, rce = 80K, Cc = 3PF, Ce = 100 PF. Using Miller’s theorem and the appropriate analysis, compute As shown in the Figure2i. The upper 3 dB frequency of the current gain AIii. The magnitude of voltage gain at the frequency of part (i). (JNTU Mar 06)

11. i. What is swamping resistor? What are its effects when used in CS amplifier circuit? Explain clearlyii. Design 1 -stage emitter follower having Ri = 500 KΩ. and RO = 20Ω.

Assume hfe = 50, hie = 1K, hoe = 25 micro-amp/ V. (JNTU Mar 06)

12. i. Draw the circuit diagram of CE amplifier and its h-parameter equivalent circuit. Give typical values of h-parameters of a transistor in CE configuration.ii. Findout Ai, AV , Ri and Ro of CE, self-bias amplifier circuit, given R1 = R2 = 100 K , RE = 2.93,

Rc = 2.1K, RS = 50, RL = 1K. The h-parameters of the transistor are hfe = 100, hie = 2K, hre = 0, hoe = 10- 5 mhos. Neglect capacitive reactance’s of coupling and bypass capacitors.

(JNTU Mar 06)

13. i. Draw the typical Hybrid π model for a transistor in the CE configuration. Derive the hybrid π conductances in CE configuration.

ii. Show that the hybrid π model is valid for frequencies upto approximately fT /3. (JNTU Mar 06)

14. i. Draw it’s a.c. equivalent circuit of CE-CC amplifier and derive the expression for Ri.ii. If RL = RE = 1K and using typical values of h-parameters hie = 1.1K, hfe = 50, hre = 2.5 x 10-4,

hoe= 25 µA/V. What is the value of Ri? (JNTU Mar 06)

15. i. Define fff and fT and derive the relation between fff and fT .ii. The h-parameters of a transistor at Ic = 8mA, VCE = 10v, and at room temperature are hie = 1K , hoe = 2 x 10 -5 A/V, hfe = 50, hre = 2.5 x 10-4. At the same operating point, fT = 60 MHz, and Cob = 2PF. Compute the values of hybrid - ff parameters. (JNTU Mar 06)

16. i. Draw ac equivalent circuit for a CE amplifieri. with a bypassed emitter resistor and

ii. with an unbypassed emitter resistor. Briefly explain each circuit.ii. Using the approximate h-parameter model, derive expressions for current gain, input resistance, voltage gain and output admittance of a CE amplifier with a resistor in emitter circuit. (JNTU Nov 05)

17. i. Draw an approximate equivalent Hybrid ff circuit for the calculation of the short-circuit CE current gain and derive the same.ii. Derive the frequencies fff and fT from the above derivation (JNTU Nov 05)

18. i. Give the typical values for h-parameters of CC configuration. Prove that Yo = ho ffRs+Ri1 Rs+Rio ff

Where Ri1ff Ri for RL = 1,and Rioff Ri for RL = 0.ii. For a CE amplifier, what is the maximum value of Rs for which Ro differs by not more than 10%

of its value for Rs = 0 ? Given hie = 1.1K, hfe = 50, hre= 2.5 x 10-4, hoe = 25µA/V.iii. Derive the condition to obtain AV =1 in CC single stage amplifier. (JNTU Nov 05)

19. i. Draw the Hybrid-ff equivalent circuit of BJT and explain the significance of each parameter. Mention typical values of hybrid-ff parameters.

ii. Given the following transistor measurements made at IC = 5 mA, VCE 10V and at room temperature hfe = 100, hie= 600 , [Aie] = 10 at 10MHz, Ce = 3 Pf. Find fff, fT , Ce, rb0e and rbb0.

(JNTU Nov 05)

20. The CB amplifier circuit is shown in figure3.

21. Derive the expression for Ai, Ri, AV and Ro. 16Calculate Ai,Ri,Av and Ro for the above CB amplifier, with RL=5k, RS=500 ohms, hfe=50, hie=1k, hoe = 50k, RE = 10k and Re = 10k

(JNTU Nov 05)

22 The h-parameters of a transistor at Ic = 8mA, VCE = 10v, and at room temperature are hie = 1K , hoe = 2 x 10 -5 A/V, hfe = 50, hre = 2.5 x 10-4. At the same operating point, fT = 60 MHz, and Cob = 2PF. Compute the values of hybrid - ff parameters. Draw the circuit of an emitter follower and it’s equivalent circuit (JNTU Nov 05)

23 i. Classify amplifier circuits based on frequency range, type of coupling, power delivered and signal handled.

ii. Derive an expression for current gain and input impedance of CE amplifier circuit. Explain how the current gain is effected by source resistance. (JNTU Nov 04)

24. i. Define fβ and ft and derive the relation between fβ and ft.

ii. The h-parameters of a transistor at Ic = 8mA, VCE - 10v, and at room temperature are hje = 1KΩ,

hoe = 2 x 10-5 A/V, hfe = 50, hre = 2.5 x 10-4. At the same operating point, fr = 60 MHz, and C0b

= 2PF. Compute the values of hybrid - n parameters. (JNTU Nov 04)

25. i. Draw the circuit of an emitter follower and it’s equivalent circuit ii. Derive the expressions for its current gain, input resistance, voltage gain and output admittance

using CE h-parameters. (JNTU Nov 04)

26. i. Classify amplifier circuits based on frequency range, type of coupling, power delivered and signal handled.

ii. Derive an expression for current gain and input impedance of CE amplifier circuit. Explain how the rrent gain is effected by source resistance. (JNTU Nov 04)

27. i. Define fβ and ft and derive the relation between fβ and ft.

ii. The h-parameters of a transistor at Ic = 8mA, VCE - 10v, and at room temperature are hje = 1KΩ,

hoe = 2 x 10-5 A/V, hfe = 50, hre = 2.5 x 10-4. At the same operating point, fr = 60 MHz, and

C0b = 2PF. Compute the values of hybrid - n parameters.

(JNTU Nov 04)

28. i. The h-parameters of CE- amplifier are hie = 1100DΩ, hre = 2.5 x 10-4 ,

hfe = 50, hoe 24 A/V and Rs = 1KΩ, RL = 10KD. Find out current and voltage gains with and

without source resistance, input and output impedances. ii. Derive an expression for voltage gain of common drain amplifier circuit. (JNTU Apr 04)

29. i. Draw an approximate equivalent Hybrid π circuit for the calculation of the short-circuit CE current gain and derive the sameii. Derive the frequencies fβ and ft from the above derivation. (JNTU Apr 04)

30. Derive an expression for voltage gain of common drain amplifier circuit (JNTU Apr 04)

31. i. Sketch CS amplifier using JFET and draw its small signal equivalent circuit.ii. In the above circuit, if VDD = 20 V, IDSS = 3mA, VP = -2.4V, rd = 10 k, RD = 10 k, RG = 1 M,

RS = 470Ω, determine AV, gm, VDS, ID and VGS. (JNTU Apr 04)

32. i. Draw AC equivalent circuit for a CE amplifier (i) with a bypassed emitter resistor and (ii) with an unbypassed emitter resistor. Briefly explain each circuit.

ii. Using the approximate h-parameter model, derive expressions for current gain, input resistance, voltage gain and output admittance of a CE amplifier with a resistor in emitter circuit. (JNTU Apr 04)

33. i. Draw the basic circuit of CS amplifier with load resistor Rd in drain circuit and an additional

resistor Rs in the source to ground circuit.ii. Draw its small signal low frequency equivalent circuit.iii. Derive expressions for voltage gain and output resistance. (JNTU Apr 04)

34. i. Draw a typical CE amplifier and explain the function of each component in it.ii. Design a single stage CE amplifier to meet the following specifications, Ri = 1k, R0 = 2k, Av =

100, fL = 50 Hz, fH = 100 KHz. (JNTU

Apr 04)

35. i. Draw the typical Hydrid π model for a transistor in the CE configuration. Derive the hydrid π conductance in CE configuration.

ii. Show that the hydrid π model is valid for frequencies upto approximately fT/3. (JNTU Apr 04)

36. i. For the emitter follower with Rs = 0.5 K and RL = 5K, calculate Aj, Rj, Av, Avs and RO. Assume

hfe = 50, hie = IK, hoe = 25uA/V.

ii. Draw the circuit diagram and Low frequency equivalent circuit of common source amplifier and derive an expression for its voltage gain. (JNTU Nov 03)

37. i. Draw the Hybrid -π equivalent circuit of BJT and explain the significance of each parameter. Mention typical values of hybrid-Tt parameters.

ii. Given the following transistor measurements made at Ic = 5 mA, VCE 10V and at room

temperature hfe = 100, hie= 600Ω, [Aie] = 10 at 10MHz, Ce = 3 Pf. Find f β, ft, Ce, rb’e and

rbb’.(JNTU Nov 03)

38. i. What is swamping resistor? What are its effects when used in CS amplifier circuit? Explain clearly.

ii. Design 1 -stage emitter follower having Ri = 500 KΩ. and RO = 20Ω. Assume hfe = 50, hie = 1K, hoe = 25 micro-amp/ V. (JNTU Nov 03)

39. i. Derive the expressions for transconductance and input conductance of CE amplifier using HF model.

ii. The following LF parameters are known for a given transistor at Ic = 10 mA, VCE=5V and at

room temperature hie = 500Ω, hoe = 10-5A/V, hfe = 100, hre = 10-4. At the same operating point

ft = 50 MHz, and C0b = 3 PF, Compute the values of all the hybrid -π parameter. (JNTU

Nov 03)

40. A JFET with the following parameters is used in a single stage common source amplifier with a load resistance of 100 k. Calculate the high frequency cut off (upper 3 dB cut off frequency) of the amplifier? (JNTU Nov 03)

Gm = 2.0 mA/V

Ggd = 2.0 pF

rd= 100 k

Cgd=2.0 pF

Cgd=1.0 pF

41. In the MOSFET amplifier shown in Fig. below, the transistor has h fe =50 rd=10 kΩ, Cgs=5 pF,

Cgd = 1pF and Cds=2 pF. Draw a signal equivalent circuit for the amplifier for midband

frequencies and calculate its midband voltage gain. (JNTU Nov 03)

42. For the amplifier of Fig., IC=1.3 mA, RC=2k, RE=500 Ω, VT=T/q = 26 mV, hfe=100, VCC=15

V vs=0.001 sin (wt) V and Cb=Ce=10 F (JNTU Nov 03)

43. For the common emitter amplifier shown in Fig., draw the simplified high frequency equivalent circuit and derive approximate expression for the voltage gain and 3 dB frequency. (JNTU Nov 03)

44. i. What is swamping resistor? What are its effects when used in CS amplifier circuit? Explain clearly.

ii. Design 1 -stage emitter follower having Ri = 500 KΩ. and RO = 20Ω.Assume hfe = 50, hie = 1K, hoe = 25 micro-amp/ V. (JNTU Nov 03)

45. Given the following transistor measurements made at Ic = 5 mA, VCE 10V and at room

temperature hfe = 100, hie= 600Ω, [Aie] = 10 at 10MHz, Ce = 3 Pf. Find f β, ft, Ce, rb’e and

rbb’.(JNTU Nov 03)

46. The amplifier shown in figure1 utilizes an N-channel FET for which VP =-2v and IDSS= 0.8mA.It is desired to bias the circuit at ID=0.8mA using VDD=24v. Assume rd>>RD. Find VGS, gm , RS, Rd such that voltage gain is atleast 20dB with RS bypassed with a very large capacitance CS.

(JNTU Mar 06)

47. i. What is the order of magnitude of each resistance in the hybrid π-mode?ii. Explain why the 3dB frequency for current gain is not same as fH for voltage gain. (JNTU Mar

06)

48. Explain how the parameters of hybrid-π model varies with IC, VCE and temperature.(JNTU Mar 06)

49. Draw the small signal high frequency CE model of a transistor

50. Give the significance of two capacitors in hybrid II model giving their typical values

51. Explain the significance of all resistive components of hybrid II model and give their typical values

52. Derive the equation for gm which gives relation between gm, Ic and temperature.

53. Prove that a) hfe=gm rb’e b) hie = rbb’ + rb’e

54. Derive the expression for the CE short circuit current gain Ai as a function of frequency

55. Define fα , f ß,f T , and state the relation between f ß, fT

56. Derive the expression s for the CE current gain and voltage gain including source resistance Rs

57. Derive the expression of gain bandwidth product for voltage and current.

58. A transistor used in video applications is connected in the CE configuration with its collector to emitter voltage held constant at 1V, A 70 mV change in the base emitter voltage causes a change in collector current from 1 mA to 10 mA What is the approximate value of transistor gm ?

59. Draw AC equivalent circuit for a CE amplifier (i) with a bypassed emitter resistor and (ii) with an un bypassed emitter resistor. Briefly explain each circuit.

60. Define fff and fT and derive the relation between fff and fT .

UNIT – IV

1. a. What are the advantages and disadvantages of push pull configuration? Show that in Class-B push pull amplifier the maximum conversion efficiency is 78.5%.b. A transistor in a transformer coupled (Class – A) power amplifier has to deliver a maximum of 5

Watts to a load of 4Ω load. The quiescent point is adjusted for symmetrical swing, and the collector supply voltage is VCC = 20 Volts. Assume Vmin = 0 volts.i. What is the transformer turns ratio?ii. What is the peak collector current? (JNTU Feb 08)

2. a. Write short notes on requirement and types of heat sinks for power dissipation in large single amplifiers.

b. With the help of a neat circuit diagram, explain the operation of a complementary symmetry configured class B power amplifier.

c. Compare and contrast push-pull and complementary-symmetry configurations for class B power amplifier. (JNTU

Feb 08)

3. a. Classify large signal amplifiers based on their operating point. Distinguish these amplifiers in terms of the conversion efficiency.

b. Draw the complimentary symmetry class-B power amplifier and explain its operation.(JNTU Nov 07)

4. a. Classify large signal amplifiers based on its operating point. Distinguish these amplifiers in terms of the conversion efficiency.

b. Draw the push-pull power amplifier circuit. Derive the expression for the output current in push? Pull amplifier with abse current as ib = Ibm sim wt. (JNTU Feb 07)

5. i Explain why a power amplifier is always preceded by a voltage amplifier?

ii. Draw the circuit diagram of a single ended power amplifier? Explain the function of each component used in the circuit? (JNTU Mar 06)

6. i. Discuss the various types of distortions that exist in complementary symmetry class-B Power amplifier circuit.ii Derive the expression for total output power “P” delivered in class-B power amplifier including

the power added by higher harmonics. (JNTU Mar 06)

7. i. Explain about heat sinks. Explain the term Thermal Resistance. Give the sketches of heat sinks.ii. What is the Junction to ambient Thermal Resistance for a device dissipating600 mw into an ambient temperature of 500C and operating at a junction temperature of 1100C? (JNTU Mar 06)

8. i. Calculate the second harmonic distortion, if the output signal waveform of apush pull amplifier has measured values of VCEmin = 1 V; VCEmax = 24 Voltsand VCEQ = 14 V; using an oscilloscope.ii. Explain harmonic distortion and crossover distortions in power amplifiers (JNTU Mar 06)

9. i. Draw the circuit for class-B Push Pull amplifier and explain the operation with the help of waveforms.

ii. What are the advantages and disadvantages of class B Push Pull amplifier circuits. (JNTU Mar 06)

10. i. Explain the reasons for nonlinear distortion in power amplifiers.ii. Explain the reasons for Harmonic distortion in power amplifiers.iii. Explain the reasons for crossover distortion in class-B power amplifiers and suggest a suitable

circuit for its minimization (JNTU Mar 06)

11. i. Draw the circuit for class-B Push Pull amplifier and explain the operation with the help of waveforms.

ii. What are the advantages and disadvantages of class B Push Pull amplifier circuits. (JNTU Mar 06)

12. i. Explain the reasons for nonlinear distortion in power amplifiers.ii. Explain the reasons for Harmonic distortion in power amplifiers.iii. Explain the reasons for crossover distortion in class-B power amplifiers and suggest a suitable

circuit for its minimization. (JNTU Mar 06)

13. i Single ended power amplifier is not used in practical circuit. Instead a pushpull amplifier is used. Why?

ii. Draw a circuit diagram of a push pull amplifier circuit and explaini. how proper biasing is achieved giving circuit.ii. how AC power free from even harmonics is developed across the load. (JNTU Mar 06)

14. Derive the expression, with necessary diagrams, to calculate the total harmonic distortion ‘D’ in power amplifiers using the five-point method of analysis. (JNTU Mar 06)

15. State the expression relating the total output power ‘P’; total harmonic distortion ‘D’ and the fundamental power ‘P1’ in power amplifiers. If total distortion in the amplifier is 9%; calculate its contribution to the total power. (JNTU Mar 06)

16. Discuss the effect of the increase in the order of harmonic frequency in power amplifier stage used in an instrument for listening to music. (JNTU Mar 06)

17. i. Draw a simple series fed class A Amplifier circuit and derive a relationship for output power in terms of load resistance RL. (JNTU Nov 05)ii. Sketch the output waveforms for class A, class B and class C with respect to conduction angle.

18. i. What is thermal resistance? What is the unit of thermal resistance?ii Derive a relation to prove that the effective surface area of the transistor case could be increased,

the resistance of heat flow could be decreased. (JNTU Nov 05)

19. i. Briefly explains the operation of Transformer coupled class A power amplifier.ii. Calculate the effective load resistance RL seen looking into the primary of a10:1 transformer

connected to an output load of 16 ohms.iii. Define conversion effciency of an amplifier. (JNTU Nov 05)

20. i. Explain the method of determination of total harmonic distortion in push pull power amplifiers using 5 - point analysis.

ii. Calculate the harmonic distortion components for an output signal, in pushpull power amplifiers; having fundamental amplitude of 2.5 Volts, second harmonic amplitude of 0.25 Volts, third harmonic amplitude of 0.1 Volts, fourth harmonic amplitude of 0.05V. Also calculate the total harmonic distortion. (JNTU Nov 05)

21. i . Determine the input power, output power and efficiency for a class B power amplifier circuit with Vcc=30 V Im=1 Amp and RL=10 .

ii. Draw the circuit of transformer less pushpull amplifier circuit with loud speaker as the load resistance. Justify the circuit operation with “emitter follower”circuit working. (JNTU Nov 05)

22. i. Assume a graphical representation of a distorted output signal of a push pull power amplifier show the fundamental sinusoidal component second harmoniccomponent the third harmonic component on a graph paper to scale.ii. Explain ‘cross over’ distortion in class-B complementary symmetry amplifier. (JNTU Nov 05)

23. Show that in the case of series fed class A power amplifiers, maximum theoretical efficiency is 25%.

(JNTU Nov 05)

24. Draw the complementary - symmetry class-B power amplifier circuit with single power supply and explain its working. (JNTU Nov 05)

25. i. Explain about different types of distortions that occur in amplifier circuits. ii. When 2-stages of identical amplifiers are cascaded, obtain the expressions for overall voltage gain,

current gain and power gain. (JNTU Nov 04)

26. . Show that the even harmonics are eliminated in class B push-pull configuration. (JNTU Nov 04)

27. In complementary - symmetry class-B power amplifier circuit, Vcc=25 Volts; RL,-16 Q and

Imax=2 amps. Determine the input power, output power and efficiency. (JNTU

Nov 04)

28. i. Show that in the case of transformer coupled class A power amplifier, maximum theoretical efficiency is 50%.

ii. Compare series fed and transformer coupled class A power amplifiers. (JNTU Nov 04)

29. i. Discuss the effect of nonlinear region of IB-VBE characteristic of each transistor used in complementary - symmetry class-B power amplifiers, in detail.

ii. The power amplifier supplies 4 watts for 8 ohms load. The zero-signal d.c.Collector current is 35ma and it rises to 40ma when the signal is applied. Determine the percent second harmonic distortion. (JNTU Nov 04)

30. i. Draw the circuit for class A series fed amplifier and derive the expression for output power P0.

ii. Determine the component values of class A series fed amplifier to deliver 75 mw of output power to a load of 4O. Vcc=16V. At the operating point IB=200 uA. Po(Max) 200 mw. Assume

reasonable values of data wherever necessary.(JNTU Nov 04)

31. i. What is thermal resistance? What is the unit of thermal resistance? ii. Derive a relation to prove that the effective surface area of the transistor case could be increased;

the resistance of heat flow could be decrease. (JNTU Nov 04)

32. i. Derive the expression for maximum collector Power Dissipation Pc(Max) in the case of class B

power amplifiers. What is its maximum value?ii. Explain the term half wave symmetry? (JNTU Nov 04)

33. i. Calculate the second harmonic distortion, if the output signal waveform of a push pull amplifier has measured values of VCE min = 1V; VCE max = 24 volts and VCEQ = 14V; using an

oscilloscope.ii. Explain harmonic distortion and crossover distortions in power amplifiers. (JNTU Nov 04)

34. i. Derive the equation for maximum value of efficiency of a class A transformer coupled amplifier. (JNTU

Nov 04)

35. i. Explain the terms Impedance matching and cross over distortion.

ii. When are two transistors said to have Complementary Symmetry? Draw the circuit of a complementary symmetry push-Pull Class-B Power Amplifier and explain its operation together with characteristics of amplifier. (JNTU Apr 04)

36. i. Assume a graphical representation of a distorted output signal of a push pull power amplifier and show the fundamental sinusoidal component, second harmonic component and the third harmonic component on a graph paper to scale.ii. Explain ‘cross over’ distortion in class-B complementary symmetry amplifier. (JNTU Apr 04)

37. i. Derive the expression for efficiency of a transformer coupled class-A power amplifier.ii. In the case of a Class-A Power Amplifiers circuit, RL = 5Ω. Transistor ratings are PC(Max) =

10w, VCE(Sat) = 1 V, VCE(Max) = 60V. Transformer coupling is used with n=2. Determine

the efficiency of the amplifier.(JNTU Apr 04)

38. i. Explain the reasons for harmonic distortion in push pull power amplifiers.ii. Derive the expression for the power of output signal having distortion.iii. For harmonic distortions of D2 = 0.1; D3 = 0.02 and D4 = 0.01 with fundamental component of

output signal I1 = 4A and RL = 8Ω. Calculate the total harmonic distortion, fundamental power

component and total power.(JNTU Apr 04)

39. i. Explain about class A, class B, class AB & class C operation of power amplifiers.ii. Design a class B power amplifiers to deliver 25w to a load resistor RL=8Ω, using transformer

coupling. Vm=VCC=25V. Assume reasonable data wherever necessary.

(JNTU Nov 03)

40. i. Draw the circuit diagram of a complementary symmetry push pull amplifier and explain its working.

ii. Distinguish between cross over distortion and harmonic distortion. How they can be eliminated.(JNTU

Nov 03)

41. i. What are the two disadvantages of push pull Amplifiers.ii. Give schematic of class B pushpull amplifier with complementary symmetry and explain the

working of it. (JNTU Nov 03)

42. A class B transformer coupled amplifier is to supply 4 W to a 100 load. Available supply voltage VCC=30 V. The transformer efficiency is 75%. Specify the output transformer and the

output transistors. (IES 03)

43. A class C transistor amplifier is operating at 150 kHz. The transistor is conducting for 1 s in each cycle. The saturation values for the transistor are: IC(SAT)=100 mA; VCE(SAT)=0.2 V. (IES 04)

Assuming ideal pulse approximations and the output swinging over the entire load line, find the average power dissipation

44. Determine the component values of class A series fed amplifier to deliver 75 mw of output power to a load of 4O. Vcc=16V. At the operating point IB=200 uA. Po(Max) 200 mw. Assume

reasonable values of data wherever necessary.(IES 99)

45. a. Draw a FET amplifier with the load resistance 100KΩ , and Rg1=Rg2=1MΩ. Calculate the gain of the amplifier, If Rds=100 KΩ and gm=2mΩ . What are the advantages of this amplifier?b. A Transistor is used as an amplifier in a CB Configuration with a load resistance Rl=40 KΩ and

the source resistance =Rs=200 Ω . Find the voltage and the power gain of the amplifier. Given that hib=50 Ω ; hbe=0.2µΩ , hrb=c x 10-4 ; hfb= -0.99 .

c. A Two stage RC Coupled Transistor amplifier is providing a negative feedback, having a feedback factor of 1/100 . Draw the amplifier circuit. If the gain of the amplifier without feedback is 60dB .and it has a distortion of 10% in the output. Then calculate the gain and the distortion of the amplifier with feedback

46. Calculate the following:i. The common emitter current gain of a pnp transistor whose common base current gain is 0.99ii. The values of initial current in a series RL circuit with R=100 Ω , L=10H with a battery supply of

10 v and final current at 0.1 sec after the battery circuit is broken

47. a. Draw a high frequency equivalent circuit of a junction transistor and explain the significance of the different components used there in . Explain what you understand by the terms f ß fΓ fά and of the

transistorb. An npn transistor having Ln=0.98, Icbo=2μA.Ibeo=1.6μA is connected as a common emitter

switch with a +12v and a collector load of 4K Ω .What are the magnitudes of the ON state and OFF state currents in the switch? What is the minimum base current required by the transistor to enter the saturation? If the base signal is a rectangular pulse

48. Calculate the transformer turns ratio required to match a 8Ω speaker load to an amplifier so that the effective load resistance is 3.2 kΩ. (JNTU Nov 04)

49. When are two transistors said to have Complementary Symmetry? Draw the circuit of a complementary symmetry push-Pull Class-B Power Amplifier and explain its operation together with characteristics of amplifier.

(JNTU Apr 04)

50. Draw the circuit diagram of a single ended power amplifier? Explain the function of each component used in the circuit?

51. Derive the expression for total output power “P” delivered in class-B power amplifier including the power added by higher harmonics. Derive the expression for total output power “P” delivered in class-B power amplifier including the power added by higher harmonics. ?

52. Explain the working of the series fed directly coupled class A amplifier with the help of neat circuit diagram

53. Give the expression for dc power i/p ac power o/p and efficiency of a series fed , directly coupled class A amplifier

54. Prove that the maximum efficiency of a series fed directly coupled class A amplifier is just 25%.

55. When the power dissipation is maximum in class A amplifier? What is the power dissipation rating of a transistor.

56. Explain with neat circuit diagram the working of a transformer coupled class A power amplifier

57. Prove that the maximum efficiency of a transformer coupled class A amplifier is 50%

58. What is harmonic distortion? How the output signal gets distorted due to harmonic distortion

59. Explain the three point method of calculating the second harmonic distortion

60. What is a heat sink? What is its function?

61. In complementary - symmetry class-B power amplifier circuit, Vcc=25 Volts; RL,-16 Q and

Imax=2 amps. Determine the input power, output power and efficiency

62. Which amplifiers are classified as power amplifier? Explain the general features of a power amplifier

63. Explain the classification of power amplifiers based on class of operation

64. Compare the various classes of operation of power amplifiers based on (a) operating cycle (b) Position of Q point (c) Efficiency

UNIT – V

1. a. Why do we use tuned amplifiers in the IF and RF range?b. Explain in detail how you alter the bandwidth of an RF amplifier which is

i. Single tuned.ii. Double tuned.iii. Stagger tuned. (JNTU Feb 08)

2. Draw the high frequency equivalent circuit of a Tapped single tuned Capacitance coupled amplifier using BJT and derive the expressions for a. Voltage gain (A)b. Voltage gain at resonance (Ares) (JNTU Feb 08)

3. i. Explain the working of single tuned amplifier. (JNTU Mar 06)ii. Derive the expression to obtain universal resonance curve and explain its significance in practical

circuits? 4. i. Draw the circuit of a Common - Emitter amplifier that is converted to a tuned band pass amplifier;

using transformer coupling with tuned primary circuit.ii. In a single tuned amplifier with tuned primary circuit, Transistor has a transconductance of 30ms

at the resonant frequency and an output conductance composed of 100 K ohms in parallel with 5 pf of capacity. The transformer has a primary inductance of 80 µH, secondary inductance of 100 µH., coeffcient of coupling of 0.01; primary resistance of 10 and secondary resistance of 10 The primary is tuned with a 45- pf capacitor and 5 K resistor loads the secondary. Findi. the resonant frequency andii. the effective Q of the tuned circuit andiii. 3-db bandwidth. (JNTU Mar 06)

5. i. What is a tuned amplifier and how do you classify tuned amplifier.Briefly explain.ii. Briefly explain the capacitance coupled single tuned amplifier with its equivalent circuit.

(JNTU Mar 06)

6. i. What are the main advantages of class-C operating mode in RF applications?ii. Draw the circuit of class C radio frequency amplifier and explain its operation with necessary

waveforms (JNTU Mar 06)

7. i. Mention the three methods of stabilization of the double-tuned transformer coupled amplifier circuit performance against the feedback path through the parasitic capacity between input and output and also mention the reasons for neutralization schemes.ii. Mention the frequency ranges of application of the double tuned amplifiers with neutralization

schemesiii. Explain the method of adjusting the amplifiers for stabilization of the responses. (JNTU Mar 06)

8. i. Explain about synchronous tuning of Tuned amplifiers with a block diagram for the system concept.

ii. Draw the circuit of double-tuned transformer-coupled amplifier. Discuss the nature of responses of the amplifier for different values of KQ=1; KQ>1 and KQ<1. (JNTU Nov 05)

9. i. Draw the circuit of single tuned amplifier and explain its operation.ii. Draw the ideal and actual response characteristics of single tuned amplifiersiii. Discuss the significance of the pass band characteristic of tuned amplifiers when they are used in

Radio receivers (JNTU Nov 05)

10. The schematic circuit diagram of a basic class-C tuned amplifier is shown in the following figure4.

(JNTU Nov 05

11. i. Draw a simple BJT tuned amplifier circuit and its ideal response characteristic. ii. In the single tuned amplifier, the circuit bandwidth is 5 KHZ and the voltage gain has a maximum

value at 1000 KHZ, when the tuning capacitor is adjusted to 500 pf. Calculate the Q of the circuit and the coil inductance? (JNTU Nov 04)

12. i. Explain the principle of stagger tuning technique of transformer – coupled amplifier that is used to obtain band pass filter characteristic with pass band of 10 KHZ with all necessary diagrams for

illustration.ii. Also mention the class of operation of the amplifier for limiting the amplitude of gain to the

desired level (JNTU Nov 04)

13. i. Explain about synchronous tuning of Tuned amplifiers with an example of a block diagram for the system concept.

ii. Draw the circuit of double-tuned transformer- coupled amplifier. Discuss the nature of responses of the amplifier for different values of KQ=1; KQ>1 and KQ<1. (JNTU Nov 04)

14. i. State the functions and frequency ranges of operation of Tuned amplifiers with relevant reasons.ii. Draw the circuit of typical single tuned RF amplifier stage employing a transistor. Explain its

operations. If the tuned circuit contains L=200jH, C=126pf, RL=5 KΩ. Calculate the Bandwidth

of the amplifieriii. Explain the action of ‘swamping resistor’ in improving the bandwidth of tuned amplifiers.

(JNTU Nov 04)

15. i. What is a stagger tune amplifier and explain its working. (JNTU Nov 04)

ii. Derive the equation for the 3dB Bandwidth of capacitance coupled single tune amplifier.

16. Draw the circuit of Class-C Tuned amplifier. Explain its operation and derive that the efficiency of the amplifier is 100% making necessary assumptions. (JNTU Nov 04)

17. i. What is the importance of stagger tuning. Explain briefly about stagger tuned amplifiers.ii. In a class B amplifier VCE(min) = 2v and supply voltage Vcc = 15 V. Find collector circuit

efficiency.(JNTU Apr 04)

18. i. Explain the differences between the function of a transformer used in power amplifier and that used in a double tuned voltage amplifier.ii. State at least one electronic system where the tuned voltage amplifier is used. Also state its

function in that system.(JNTU Apr 04)

19. i. Mention the three methods of stabilization of the double-tuned transformer coupled amplifier circuit performance against the feedback path through the parasitic capacity between input and output and also mention the reasons for neutralization schemes.

(JNTU Apr 04)

20. i. Mention the frequency ranges of application of the double tuned amplifiers with neutralization schemes.

ii. Explain the method of adjusting the amplifiers for stabilization of the responses. (JNTU Apr 04)

21. Draw the circuit of a Common - Emitter amplifier that is converted to a tuned band pass amplifier; using transformer coupling with tuned primary circuit. (JNTU Apr 04)

22. In a single tuned amplifier with tuned primary circuit, Transistor has a trans-conductance of 30ms at the resonant frequency and an output conductance composed of 100 K ohms in parallel with 5 pf of capacity. The transformer has a primary inductance of 80 H, secondary inductance of 100 H., coefficient of coupling of 0.01; primary resistance of 10Ω and secondary resistance of 10Ω. The primary is tuned with a 45- pf capacitor and 5 KΩ resistor loads the secondary. Find

i. the resonant frequency and ii. the effective Q of the tuned circuit and iii. 3-db bandwidth. (JNTU Nov 03)

23. i. Draw the circuit of FET tuned voltage amplifier. Derive the necessary expression to draw the universal resonance curve with all necessary details.ii. Design the single stage FET tuned amplifier for fo = 12MHz.., bandwidth = 10KHz., mid band

voltage gain = -15. The FET parameters are gm = 4 ms, rd=25KΩ, Cgs = 30pf, Cgd = Cds = 5pf.

(JNTU Nov 03)

24. Explain the principle of stabilizing the double tuned transformer coupled amplifier response against the internal feedback.

(JNTU Nov 03)

25. Explain about synchronous tuning of tuned amplifiers with an example of a block diagram for the system concept. (JNTU Nov 03)

26. Explain the principle of stabilizing the double tuned transformer coupled amplifier response against the internal feedback.

(JNTU Nov 03)

27. Draw the circuit of typical single tuned RF amplifier stage employing a transistor. Explain its operations. If the tuned circuit contains L=200jH, C=126pf, RL=5 KΩ. Calculate the Bandwidth

of the amplifier (JNTU Nov 03)

28. Explain Neutralization and show how it can be realized. The circuit shown has an internal and stray wiring capacitance of 20 pF. If L1=80mH and L2=120 mH, determine to what value the

neutralizing capacitance CN should be set so as to neutralize Cinternal.

(IES 98)

29. Explain the following terms in briefi. Series resonance ii. Parallel resonanceiii. Figure of merit of a coil iv. Resonant frequency

30. Compare the series & parallel resonance circuits from the following points of viewi. Resonant frequency ii. Impedance at resonanceiii. Voltage across each component iv. Current in the circuitv. Bandwidth vi. Applications

31. Draw a series resonant circuit . plot curve showing the variations in circuit current with frequency. Explain why the current is maximum at resonant frequency? What is its phase angle with the input voltage at resonant frequency? Why does the current decrease off at resonance?

32. Write down the expression for the bandwidth of a tuned circuit in terms of its quality factor & the resonant frequency.

33. Draw a parallel resonant circuit. Provide a brief explanation of the same.34. Explain why the impedance of a parallel resonant circuit is maximum at resonance?

35. Explain the nature of a series LC circuit & a parallel LC circuiti. At resonance ii. Below resonant frequencyiii. Above resonant frequency

36. Prove that the impedance of a parallel resonant circuit at resonant frequency is approximately equal to Rs*Q*Q, where Rs is the series resistance of the coil & Q is its quality factor.

37. Explain the working of a single tuned amplifier.

38. Explain the working of a double tuned amplifier.

39. Explain in brief the advantage in using double tuned circuit over single tuned circuit.

40. Draw the circuit diagram of a double tuned amplifier. Explain how the frequency response of this amplifier is better than that of a single tuned amplifier.

41. State the main difference in the circuits of a tuned voltage amplifier & an audio-frequency voltage amplifier.

42. State at least one electronic system where the tuned voltage amplifier is used. Also state its function in that system.

43. a. Draw a high frequency equivalent circuit of a junction transistor and explain the significance of the different components used there in . Explain what you understand by the terms f ß fΓ fά and of the transistor An npn transistor having Ln=0.98, Icbo=2μA.Ibeo=1.6μA is connected as a common emitter switch with a +12v and a collector load of 4K Ω .What are the magnitudes of the ON

state and OFF state currents in the switch ? what is the minimum base current required by the transistor to enter the saturation ? If the base signal is a rectangular pulse

44. a. Draw and explain the circuit diagram of a Single tuned inductively coupled amplifier using BJT?b. Draw its High frequency circuit and explain it? (JNTU Feb 07)

45. What is meant by the term Tuned amplifier and briefly explain the various methods of classification of tuned amplifiers?

46. A constant generator drives a parallel tuned circuit consisting of a loss less capacitor ‘C’ and coil ‘L’ (having small resistance ‘R’). Derive the expression for the frequency of resonance? (JNTU Feb 07)

47. Explain what happens to the gain because of the presence of feedback capacitance from collector to base in single tuned BJT amplifier circuit? (JNTU Feb 07)

48. Explain in detail the Unilateralisation technique with the help of circuit diagram? (JNTU Feb 07)

49. Explain the difference between Neutralization and Unilateralisation techniques? (JNTU Feb 07)

UNIT – VI

1. a. What are the main advantages of class-C operating mode in RF applications?b. Draw the ciruit of class-C radio frequency amplifier and explain its operation with necessary

waveforms? (JNTU Feb 08)

2. Explain what you mean by Synchornous tuning of tuned amplifiers? Draw the frequency response of a synchronously tuned amplifiers? Draw the frequency response of a synchronously tuned amplifier showing the response of individual stages and overall response? (JNTU Feb 08)

3. a What is synchronous tunning? Derive an expression for bandwidth of an n-stage synchronously tuned amplifier?

b. Show that for an ‘n’ stage synchronously tuned amplifier, maximum bandwidth is obtained when the single stage gain is 4.34dB. (JNTU Feb 07)

4. a. With the help of neat circuit diagram, explaini the operation of BJT shunt voltage regulator.b. What is a voltage reference? Why is it needed?c. What is the function of a series pass transistor? (JNTU Feb 07)

5. Explain in detail the effect of cascading tuned amplifiers and derive the expression for bandwidth of n-stage amplifier. Also draw the frequency response and explain what happens as the number of stages increase. (JNTU Feb 07)

6. Explain in detail the effect of cascading tuned amplifiers and hence derive the expression for bandwidth of n-stage amplifier . Also draw the frequency response3 and explain what happens as the number of stages increases. (JNTU Feb 07)

7. Explain as to how you can increase the selectivity of single tuned amplifier. Draw the circuit diagram and explain its operation and also draw its frequency response (JNTU Feb 07)

8. Explain the working of single tuned amplifier. (JNTU Mar 06)

9. Derive the expression to obtain universal resonance curve and explain its significance in practical circuits? (JNTU Mar 06)

10. i. What is the importance of stagger tuning. Explain briefly about stagger tuned amplifiers.ii. In a class B amplifier VCE(min) = 2v and supply voltage Vcc = 15 V. Find collector circuit

efficiency.(JNTU Apr 04)

11. Mention the three methods of stabilization of the double-tuned transformer coupled amplifier circuit performance against the feedback path through the parasitic capacity between input and output and also mention the reasons for neutralization schemes.

(JNTU Apr 04)

12. Mention the frequency ranges of application of the double tuned amplifiers with neutralization schemes. (JNTU Apr 04)

13. Explain the method of adjusting the amplifiers for stabilization of the responses. (JNTU Apr 04)

14. Explain the principle of stagger tuning technique of transformer – coupled amplifier that is used to obtain band pass filter characteristic with pass band of 10 KHZ with all necessary diagrams for illustration. (JNTU Nov 04)

15. Also mention the class of operation of the amplifier for limiting the amplitude of gain to the desired level (JNTU Nov 04)

16. Explain about synchronous tuning of Tuned amplifiers with an example of a block diagram for the system concept. (JNTU Nov 04)

17. Explain the principle of stabilizing the double tuned transformer coupled amplifier response against the internal feedback.

(JNTU Nov 03)

18. Explain about synchronous tuning of tuned amplifiers with an example of a block diagram for the system concept. (JNTU Nov 03)

19. Explain the principle of stabilizing the double tuned transformer coupled amplifier response against the internal feedback.

(JNTU Nov 03)

20. Draw the circuit of typical single tuned RF amplifier stage employing a transistor. Explain its operations. If the tuned circuit contains L=200jH, C=126pf, RL=5 KΩ. Calculate the Bandwidth

of the amplifier (JNTU Nov 03)21. Explain Neutralization and show how it can be realized. The circuit shown has an internal and

stray wiring capacitance of 20 pF. If L1=80mH and L2=120 mH, determine to what value the

neutralizing capacitance CN should be set so as to neutralize Cinternal. (JNTU

Nov 03)

22. What is a stagger tune amplifier and explain its working. (JNTU Nov 03)

23. Discuss the significance of the pass band characteristic of tuned amplifiers when they are used in Radio receivers (JNTU Mar 06)

24. Explain the frequency response of stagger tuning.

25. Bring out the differences between the narrow band amplifier and wide band amplifier.

26. Explain the reason why the tune amplifiers are preferable in class-C amplifiers.

27. Bring out the characteristics of the narrow band amplifiers.

28. In a tune circuit, the secondary circuit has the capacitor of 100 PF the reflected value of this is 25 PF determine the turns ratio.

29. Bring out the main applications the tuned amplifiers and explain them.

30. Bring out the advantages and disadvantages of Neutralization.

31. Explain about the tuned amplifier in stability.

32. Explain about the Unilateralization stabilization technique.

33. Write short notes oni. Neutralization technique ii. Mismatch technique

34. i. What are the different types of tuned amplifiers?ii. How are tuned amplifiers classified?

35. Explain about the tuned circuits in detail

36. Explain briefly the operation of class-C tuned amplifier with a neat sketch

37. Explain briefly the operation of class-B tuned amplifier.

38. Derive the expression for selectivity of stagger tuned amplifier.

39. Bring out the differences between the stagger tuned amplifier and single tuned amplifier.

40. What is the main advantage of employing stagged tuned amplifier in tuned circuits.

41. What is synchronous tuning. Explain briefly.

42. Bring out the differences between stagger tuning and syncrhonous tuning.

43. Explain about the instabilities in tuned amplifiers.

44. Give reason why the parallel circuits are used in tuned amplifier

45. Explain about the inductor are the coil losses.

46. Draw the circuit of stagger tuned amplifier and explain its working

47. Explain the effect of cascading on tuned amplifiers.

UNIT – VII

1. a. With the help of a neat circuit diagram, explain the operation of BJT shunt voltage regulator.b. What is a voltage reference? Why is it needed?c. What is the function of a series pass transistor? (JNTU Feb 08)

2. a. What is catcher diode and explain the necessity of cathes diode ini Switch Regulator with the help of circuit diagram.b. List the operating ratings and electrical characteristics of IC 723. (JNTU Feb 08)

3. a. Explain the operation of a Zener diode Voltage Regulator.b. Discuss about the satability factor of zener diode voltage regulator. (JNTU Feb 08)

4. i. Design a series regulated power supply with following specifications.Unregulated input voltage Vi = 30V and r0 = 8 ohmsRegulated output voltage = 12 VMaximum load current = 200 ma.Control transistor hfe = 100, hie = 200 ohmsAmplifier transistor hfe= 200, hie = 1000 ohmsReference voltage VR = 6VZener resistance Rz = 10 ohmsZener current = 20 mA

ii. Also calculate its stability factor and output resistanceiii. Also draw the complete circuit diagram with the designed component values. (JNTU Mar

06)

5. i. Give the internal block schematic and pin configurations of 723 - voltage regulator.ii. Draw circuit diagram of 7812 voltage regulator along with current boosting

circuit and explain its operation. Derive expression for load current. (JNTU Mar 06)

6. i. With reference to voltage regulators discuss abouti. Output resistanceii. Load regulationiii. Line regulation

ii. Explain the limitations of unregulated power supplies. To derive regulated DC output from AC mains, what are the important building blocks required. Explain about each block. (JNTU Mar 06)

7. i. List out the important features of three terminal regulators.ii. Draw the circuit diagram of a three terminal regulator as a current source and explain its working.iii. Draw the circuit diagram of a voltage doubler circuit and explain its operation and sketch the input

and output waveforms. (JNTU Mar 06) 8. i. With reference to voltage regulators discuss about

i. Output resistanceii. Load regulatioiii. Line regulation

ii. Explain the limitations of unregulated power supplies. To derive regulated DC output from AC mains, what are the important building blocks required. Explain about each block (JNTU Mar 06)

9. i. Give the internal block schematic and pin configurations of 723 - voltage regulator.ii Draw circuit diagram of 7812 voltage regulator along with current boosting circuit and explain its

operation. Derive expression for load current. (JNTU Mar 06)

10. With reference to voltage regulators discuss abouti. Output resistanceii. Load regulationiii. Line regulationiv. Explain the limitations of unregulated power supplies. To derive regulated DC output from AC mains, what are the important building blocks required. Explain about each block.

(JNTU Mar 06)

11. i. List out the important features of three terminal regulators.ii. Draw the circuit diagram of a three terminal regulator as a current source and explain its working.iii Draw the circuit diagram of a voltage doubler circuit and explain its operation and sketch the

input and output waveforms. (JNTU Mar 06)

12. With reference to voltage regulators discuss abouti. Output resistanceii. Load regulationiii . Line regulationiv. Explain the limitations of unregulated power supplies. To derive regulated DC output from AC

mains, what are the important building blocks required. Explain about each block. (JNTU Nov 05)

13. i. Draw the circuit of 7805 voltage regulator IC and explain its working. (JNTU Nov 05)

ii. Using 7805 IC voltage regulator, design current source to deliver 0.25A current to 48 ohms, 10 watts load.

14. List out the advantages of a voltage regulator circuit over unregulated power supply. Define the following terms.

i. Line regulationii. Load regulationiii. Draw the circuit of a simple Zener regulator circuit and state how to determine the component

value. Explain the operation of the circuit with the help of load characteristics. (JNTU Nov 05)

15. i. Draw the circuit of a half-wave voltage doubler circuit and explain its operation. Sketch the input and output waveforms. What is its output voltage under no load conditions?ii. Draw the circuit of 7815 voltage regulator circuit along with unregulated circuit. Derive expression for load current. (JNTU Nov 05)

16. Define the following terms.i. Load regulationii. Line regulationiii. Temperature Stability. (JNTU

Nov 05)iv. Give the circuit of a short circuit overload protection that is to be provided in a voltage regulator

circuit and explain its working.

17. i. Draw the circuit for 7805 voltage regulator along with unregulated power supply and explain its working.

ii. Explain how 78XX can be used as a current source. Draw the circuit and explain.(JNTU Nov 05)

18. i. Draw and explain a series voltage regulated power supply. Calculate stability factor and output resistance.

ii. What are the merits and limitations of series regulators? (JNTU Nov 05)

19. i. Draw the circuit of a half-wave voltage doubler circuit and explain its operation. Sketch the input and output waveforms. What is its output voltage under no load conditions?ii Draw the circuit of 7815 voltage regulator circuit along with unregulated circuit. Derive

expression for Load current. (JNTU Nov 05)

20. Draw the circuit of a full-wave voltage doubler circuit and explain its operation. Mention the PIV of each diode. (JNTU Nov 04)

21. i. List out different types of voltage regulators, what are the advantages and disadvantages of each type.

ii. Give a schematic diagram, design methodology and working of Zener regulator circuit. (JNTU Nov 04)

22. i. List out the important features of three terminal regulators?ii. What are the limitations of linear regulators over switched mode power supplies?iii. Draw the circuit diagram of ± 15V regulated output voltage using three terminals regulators and

explain its working. (JNTU Nov 04)

23. i. Determine the following terms:i. Line regulationii. Load regulation (JNTU Nov 04)

ii. Draw the circuit of a single Zener regulator and explain its operation with the help of load characteristics.

24. i. Give the internal block schematic and pin configurations of 723 – voltage regulator.ii. Draw the circuit diagram of 7812 voltage regulator, along with current boosing circuit and explain

its operation. Derive expression for load current. (JNTU Nov 04)

25. Two power supplies A & B are available in the market. Power supply A has no load and full load voltages of 30 V and 25 V respectively whereas these values are 30 V & 29V for power supply B. Which is better power supply? (JNTU Apr 04)

26. i. Draw the circuit diagram of series regulator circuit and explain its operation. (JNTU Apr 04)ii. Explain with the help of circuit diagram. How short circuit/overload protection circuit will work.

27. i. Draw the circuit for 7805 voltage regulator, along with unregulated power supply and explain its working.

ii. Modify the circuit to boost the current and explain how it works. (JNTU Apr 04)

28. i. Draw and explain a series voltage regulated power supply. Calculate stability factor and output resistance

ii. What are the merits and limitations of series regulators? (JNTU Apr 04)

29. i. What is the limitation of three terminal regulators?ii. Draw the circuit diagram of a dual power supply using three terminal regulators to obtain +12 V

and -15V regulated DC output voltage and explain the operation of the circuit. (JNTU Apr 04)

30. i. Compare the merits and demerits of Zener regulator over series regulator and shunt regulator. ii. Draw the circuit of a shunt regulator circuit and explain its operation. (JNTU Apr 04)

31. i. What are the draw backs of three terminal regulators?ii. Draw the circuit diagram of a dual power supply using three terminal regulators to obtain ±15 V

output voltage and explain the operation of the circuit. (JNTU Apr 04)

32. i. Draw the circuit diagram of half wave voltage doubler circuit and explain its operation. Sketch the input and output waveforms. Mention what is the PIV of diode. What is its output voltage under no load conditions?

ii. Why regulator is necessary for power supplies - Give reasons. (JNTU Nov 03)

33. What is meant by voltage multiplier? List out the names of four different multipliers.

(JNTU Nov 03)

34. A series voltage regulator is required to supply a current of 1 Amp at a constant voltage of 6 v. If the supply voltage is 10V & the zener operates in the breakdown region, design the circuit. Assume beta=50, Vbe=0.5V & minimum zener current =10 mA.

35. In the circuit diagram of a series feedback voltage regulator if R1=2Kohm, R2=1Kohm, V2=6V & Vbe=0.7 V. What is the regulated output voltage?

36. In the series feedback circuit, if R1=30 Kohm, R2=10Kohm. What is the closed loop voltage gain.

37. What do you understand by unregulated power supply? Draw the circuit of such a supply.

38. What are the limitations of unregulated power supply?

39. What do you understand by regulated power supply? Draw the block diagram of such a supply?

40. Write a short note on need for regulated power supply?41. Explain the action of a zener voltage regulator with neat diagram.

42. What are the limitations of transistorized power supplies?

43. Draw the circuit of a most practical value operated power supply and explains its working.

UNIT – VIII

1. a. Using three pin voltage regulator, design a current source that will deliver 0.25A current to 48 ohms 10W load. From data sheet IQ = 4.2 mA and VR = 5A.

b. Compare IC 723 and IC78XX Voltage Regulators.c. What is UPS and explain how it differs from regulated power supply? (JNTU Feb 08)

2. a. What is catcher diode and explain the necessity of catches diode in Switch Regulator with the help of circuit diagram.

b. List the operating ratings and electrical characteristics of IC 723. (JNTU Nov 07)

3. Give the internal block schematic and pin configurations of 723 - voltage regulator.(JNTU Mar 06)

4. List out the important features of three terminal regulators. (JNTU Mar 06)

5. Draw the circuit diagram of a three terminal regulator as a current source and explain its working.(JNTU

Mar 06)

6. Give the internal block schematic and pin configurations of 723 - voltage regulator.(JNTU Mar 06)

7 Draw circuit diagram of 7812 voltage regulator along with current boosting circuit and explain its operation. Derive expression for load current. (JNTU Mar 06)

8. What are the limitations of linear regulators over switched mode power supplies?(JNTU Nov 04)

9. Draw the circuit diagram of ± 15V regulated output voltage using three terminals regulators and explains its working. (JNTU Nov 04)

10. i. Give the internal block schematic and pin configurations of 723 – voltage regulator.

ii. Draw the circuit diagram of 7812 voltage regulator, along with current boosting circuit and explain its operation. Derive expression for load current. (JNTU Nov 04)

11. What are the limitations of three terminal regulators? (JNTU Apr 04)

12 Draw the circuit diagram of a dual power supply using three terminal regulators to obtain +12 V and -15V regulated DC output voltage and explain the operation of the circuit. (JNTU Apr 04)

13. i. What is meant by voltage multiplier? List out the names of four different multipliers. ii. Draw the circuit of a full-wave voltage doublers circuit and explain its operation. Mention the

PIV of each diode. (JNTU Nov 03)

14. Draw the circuit for 7805 voltage regulator along with unregulated power supply and explain its working.

15. Explain how 78XX can be used as a current source. Draw the circuit and explain. (JNTU Nov 05)

16. Draw the circuit diagram of a dual power supply using three terminal regulators to obtain +12 V and -15V regulated DC output voltage and explain the operation of the circuit. (JNTU Apr 04)

17. Explain the block diagram of 7805 voltage regulator. (JNTU Nov 03)

18. Give the specifications of IC 78XX and 79XX voltage regulators.

19. What are the important of features of three terminal regulators?20. Why regulator is necessary for power supplies. Give reasons.

21. Draw the block diagram switching regulator and explain each block in detail.

22. Explain LM317 adjustable regulator in detail.

23. Due the internal block schematic and pin configuration of 723 voltage regulator IC.

24. What is the advantage of switching regulator over series regulator?

25. Draw the circuit of 7806 voltage regulator and explain its working.

26. Explain about the merits and demerits of switching regulators.

27. Compare series and shunt regulators.

28. Explain about the internal block schematic and pin configuration of LM337 voltage regulator.

29. Explain about various types of switching regulators.

30. Explain about step-up switching regulator with a neat block diagram

31. Explain about step-down switching regulator with a neat sketch.

32. Explain about the various types of three terminal fixed voltage regulators.

33. Explain how 78XX acts as a current source.

34. Bring out the output voltage for LM317 voltage regulator.

35. Write down the important characteristics of LM723 voltage regulator.

36. If V reference = 10v, R1 = 10 ohms then determine the reference current and the output voltage of LM317 voltage regulator.

37. Bring out the advantages of IC voltage regulator over voltage regulator.

38. Explain the operation switching regulator with a neat block diagram and waveforms.

39. Explain the disadvantages of series regulators and the advantages of switching regulators.

40. Bring out the expression for output voltage of the switching regulator.

41. State the important features of IC 723

42. Draw and explain block diagram of IC 723

43. Explain the various applications of IC 723

44. State the advantages of IC Voltage regulators

45. With suitable schematic diagram how will you see IC 7805 as a. Power supply supplying 5v o/p with high current capacityb. Power supply supplying 12v o/p with good load regulation c. Constant current source providing a current of 200Ma

46. Draw and explain block diagram of 3 terminal IC Voltage regulators

47. How to boost regulator o/p current

48. Write a note on 3 terminal adjustable IC regulators LM 317

49. Writ e a note on LM 340 series

50. How to obtain fixed regulator using LM 340

51. How to obtain adjustable regulator using LM 340 52. How to obtain current regulator using LM 340

53. Write short notes on dual power supply

54. Write short notes on dual tracking regulators

55. Explain a need of SMPS. State the limitations of linear regulators

56. Explain the working principle of basic switching regulator

57. Draw and explain the block diagram of SMPS

58. Explain the working principle of basic switching regulator

59. Explain the need for UPS in modern days

60. Explain very basic principle of UPS.

61. Draw the circuit diagram of three terminal regulators as a current source and explain the operation.

62. What are the merits and demerits of three terminal regulators?