Dong Li, Mingyuan Chen, Zhengzong Sun, Peng Yu, Zheng Liu ... · I o ed. © M Publisher L S N A eserved. SUPPLEMENTARY INFORMATION DOI: 10.1038/NNANO.2017.104 NATURE NANOTECHNOLOGY

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SUPPLEMENTARY INFORMATIONDOI: 10.1038/NNANO.2017.104

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Supplementary Information for

Two-dimensional nonvolatile programmable p-n junctions

Dong Li, Mingyuan Chen, Zhengzong Sun, Peng Yu, Zheng Liu, Pulickel M. Ajayan,

Zengxing Zhang

http://dx.doi.org/10.1038/nnano.2017.104




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Table of content

Fig. S1Schematic fabrication process of the SFG-FETs.. .......................................... 3

Fig. S2Statement of the schematic device configuration. ........................................... 4

Fig. S3Raman spectra of the WSe2/h-BN/Graphene heterostructure. ........................ 6

Fig. S4AFM results of the WSe2/h-BN/Graphene heterostructure. ............................ 7

Fig. S5Retention performance of the WSe2 p-n junction. .......................................... 9

Fig. S6Electrical behaviors of the WSe2 in the SFG-FET device. ........................... 10

Fig. S7 FET characterization of a WSe2 based device ........................................... 11

Fig. S8-S10Detailed band alignments measurements ............................................... 12

Fig. S11Estimation of the stored charges in the graphene semi-floating gate .......... 18

Fig. S12Estimation of the trapped charges’ retention.. ............................................. 20

Fig. S13Electrical properties of the WSe2 in the SFG-FET device with negative voltage pulses applied on the Si control gate.. ............................................................. 21

Fig. S14Retention performance of the SFG-FET device for the logic rectifier........ 23

Fig. S15ISC and VOC as a function of the incident laser power. ................................ 23

Table S1Physical parameters of the resulted WSe2 p-n junctions. ........................... 24

Table S2Photovoltaic parameters of the resulted WSe2 p-n junction .. ................... 25

Fig. S16Nonvolatile programmable monolayer WSe2 p-n junction obtained in the monolayer WSe2/h-BN/Graphene SFG-FET. .............................................................. 26

Fig. S17Nonvolatile programmable WSe2 p-n junction obtained in the WSe2/h-BN/Graphene SFG-FET with monolayer graphene embedded ...................... 28

Table S3Performance of the device with different graphene thicknesses. ............... 29

Table S4Performance of the device with different h-BN thicknesses. ..................... 30

Table S5Performance of the device with different WSe2 thicknesses ..................... 31

Fig. S18Nonvolatile programmable WSe1.2Te0.8 p-n junction obtained in the WSe1.2Te0.8/h-BN/Graphene SFG-FET. ...................................................................... 32

Fig. S19-28Nonvolatile programmable black phosphorus (BP) p-n junction obtained in the BP/h-BN/Graphene SFG-FET. .......................................................................... 34

Table S6Photovoltaic parameters of the resulted BP p-n junction.. ......................... 46

References:.................................................................................................................. 46





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Supplementary Figure 1 Schematic fabrication process of the 2D crystal

heterostructure based semi-floating gate field-effect transistors (SFG-FETs). a, A

graphene flake is first transferred on a Si/SiO2 substrate with a mechanical exfoliation

method. b, An h-BN flake is first transferred on a transparent PDMS film with the

mechanical exfoliation method. Under the help of an optical microscope, the h-BN is

aligned on the graphene flake. c and d, After the PDMS is lifted off, the h-BN is left

on the graphene just like stamping a pattern with a stamp. e to g, With the same

method, a WSe2 (or BP) flake is transferred on the h-BN. h, Finally, e-beam

lithography (EBL) is used to define Au/Cr electrodes on the obtained heterostructures.

Here the graphene is the semi-floating gate, the h-BN and SiO2 are the dielectric, the

WSe2 (or BP) serves as the field-effect transistor channel, and the Si plays as the





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control gate. Only part of the WSe2 (or BP) channel is aligned over the graphene,

resulting in a semi-floating gate configuration.

Supplementary Figure 2 Statement of the schematic device configuration. a,

Schematic of the device configuration. b, Possible band structure of the created p-n

junction with the WSe2 bent over the edge of the graphene. c, AFM surface

morphology of a WSe2/h-BN/Graphene device. d, Height profiles along the different

2D crystals as indicated in Fig. S2c. Theoretically, in the device structure, WSe2/h-BN

should be bent over the edge of the graphene gate. It is just across the interface of the

p-type and n-type WSe2 and thus in the space-charge region. The bend often leads to a

tensile strain. Previous studies indicate that the tensile strain can decrease the bandgap

of the WSe21. We can simply regard the bent WSe2 with a smaller bandgap as another

semiconductor (abbr. S-WSe2). Therefore, the p-n junction gets to be

p-WSe2/S-WSe2/n-WSe2. It should have a band structure as Fig. S2b2. Such band

structure should affect the behaviors of the p-n junction. Due to a small bandgap





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induced in the space-charge region, the current across the p-n junction should be a

little bigger than the conventional p-n junction. As we all know, for photovoltaics, the

charge carriers are mainly generated and separated in the space-charge region. The

light absorption is dependent on the bandgap width. The decrease of the bandgap

should make the light with smaller energy absorbed. It indicates that the light

absorption should be redshifted and the range should be enlarged. In our experiment,

the used graphene often includes a few layers. Typically it is no more than 4 nm. We

used AFM to characterize the surface morphologies of the 2D crystals. As shown in

Fig. S2c&d, the thickness of the graphene can be clearly identified (3.5 nm). However,

the surfaces of the h-BN and WSe2 over the edge seem to be flat with reasonable

roughness in a large scale (5 µm). It should be due to that the thickness of the

graphene is too small to bend the upper 2D crystals. This indicates that the possible

bend over the edge of the graphene should be neglected. Therefore, for electrical

transport study, we did not consider the possible bend over the edge of the graphene.

For schematic, in order to make the structure clear, the thickness of the graphene is

enlarged and the bending is exaggerated.





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Supplementary Figure 3 Raman spectroscopy characterization of the

WSe2/h-BN/Graphene heterostructure. a, False colored SEM image of the device

shown in the paper. Scale bar, 5 µm. b, Raman spectra of the different parts as indicated

in the device. In Fig. b, Gr denotes graphene. The four Raman spectra correspond to the

four different parts as indicated. The Raman spectra exhibit typical features of the

WSe2 (six peaks at 249 cm-1, 259 cm-1, 308 cm-1, 360 cm-1, 373 cm-1 and 395 cm-1)3,4,5,

h-BN (one peak at 1365 cm-1)6 and few-layer graphene (two peaks at 1581 cm-1 and

2723 cm-1)7, respectively, indicating that all of them are few-layer structures.





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Supplementary Figure 4 Atomic force microscopy (AFM) characterization of

the WSe2/h-BN/Graphene heterostructure. a, False colored SEM image of the

device shown in the paper. Scale bar, 5 µm. b to d, AFM images of the different parts as

indicated in the device. The results indicate that the WSe2, h-BN and graphene are 2.5

nm, 9.6 nm, 1.5 nm in thickness, respectively, indicating that the WSe2 should include

3 layers3, the h-BN includes 20-30 layers6, and the graphene is about 3 layers8. The

AFM images also indicate that bubbles (spots) are trapped in the 2D crystals. The

bubbles are often present in the transferred 2D samples, like graphene9,10, WSe211,

black phosphorus (BP)12, and so on, which contain air, residues and other

contaminants13. As reported, the formation of the bubbles is often due to the

contaminants7 and the strain in the 2D materials14. In our experiment, the samples were





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fabricated with an all-dry transfer process15. The 2D layers were first exfoliated on

elastomeric PDMS stamps by using Scotch tape, and then aligned and transferred on

the position as needed. During the exfoliation and transfer process, pressure on the

PDMS is inevitable. Since the PDMS is elastomeric, strain happens in the interface of

the PDMS and 2D crystals. It leads to the bubbles in the 2D samples14. The PDMS

residue and other inevitable contaminants, like nanoparticles from the surroundings

should be another reason for the bubbles. The bubbles often make spatial charge

inhomogeneities in 2D crystals and decrease their mobility9,13. For our devices, the

bubbles should decrease the electrical transport and affect the efficiency of the

field-induced charge doping in the WSe2. For further applications, better methods

should be developed to avoid such bubbles to increase the performance of the devices.





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Supplementary Figure 5 Retention performance of the resulted WSe2 p-n

junction in the WSe2/h-BN/Graphene heterostructure based SFG-FET device excited

by a positive voltage pulse of +40 V applied on the control gate. With a bias voltage VDS

of +1 V, the device is on the high forward current state, while a bias voltage VDS of –1 V

makes the device working on the low reverse current state. After 1200 s, there are no

significant variations on the currents, indicating that the resulted p-n junction is

nonvolatile.





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Supplementary Figure 6 Electrical transport characterization of the WSe2 in

the designed WSe2/h-BN/Graphene SFG-FET device without any gate voltage

applied on the Si control gate, with a positive voltage pulse applied on the Si control

gate and with the graphene semi-floating gate grounded, respectively. The results

indicate that the positive voltage pulse makes a rectifying behavior and the graphene

grounded leads to the disappearance of the rectifying characteristic. In the figure, Gr

denotes graphene.





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Supplementary Figure 7 Field-effect transistor (FET) characterization of a

typical few-layer WSe2 flake based device with a bias voltage of +1 V applied

between the drain (D) and source (S). The result indicates that the simple pure

WSe2 FET exhibits a high on/off ratio ~106. While the back gate voltage is scanned

from -40 to 40 V, the current first decreases to a minimum point at ~-18 V, and then

increases with the gate voltage increasing. This indicates that the hole and electron

doping can be both achieved in the WSe2 flake, and it is intrinsically n-doped. The

inset is an optical microscopy image of the WSe2 FET device, where the WSe2 is

fabricated on a Si substrate with a 300-nm-thick thermal oxide film.





12

Detailed band alignments of the WSe2/h-BN/Graphene device (Figures S8-10).

Supplementary Figure 8 Estimation of the bandgaps of the WSe2 and h-BN. a.

The WSe2/h-BN/Graphene device used for measurement. Scale bar: 5 µm. Gr denotes

graphene. b, AFM characterization of the device. The thickness of the WSe2 is 3.1 nm,

which includes four layers3. c, Photoluminescence (PL) spectrum of the WSe2,

indicating that the bandgap of the WSe2 is 1.44 eV, which is consistent to the reported

results16. The two peaks over 1.8 eV are the Raman peaks of the bottom graphene. d.

UV-vis reflectance spectrum of the h-BN, indicating that the bandgap of the h-BN is

5.54 eV.





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Supplementary Figure 9 Kelvin probe force microscopy (KPFM)

characterization of the WSe2/h-BN/Graphene device. a, KPFM measurement result

of the device. b and c are corresponding to the yellow and white line in a. In the

figures, Gr denotes graphene.





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Supplementary Figure 10 Estimation of the band structure of the WSe2. a,

Transfer curve of the four-layer WSe2 FET measured in the atmosphere. b, Transfer

curve of the four-layer WSe2 FET measured in the vacuum. c, Simulated Fermi level

dependent on the VG and band structure.

To confirm the detailed band alignments, we need to know the bandgap widths

and electron affinities. In our experiment, the used WSe2 is 3.1 nm in thickness, which

includes four layers (Fig. S8a). We first used photoluminescence (PL) spectroscopy

method to measure the bandgap of the WSe2. As shown in Fig. S8c, the PL spectrum

indicates that the four-layer WSe2 has a bandgap of ~1.44 eV, which is consistent to

the reported literature16. For the h-BN, we confirmed the bandgap through the UV-vis

reflectance spectrum. As shown in Fig. S8d, the result indicates that the bandgap of

the h-BN is ~5.54 eV, which accords with the previous work well17. It should be





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noted here that we use the h-BN powder for the measurement. Since the used h-BN

for the FETs includes tens of layers, which should have a similar bandgap to the h-BN

powder. For graphene, it is a semimetal so that it is not necessary to measure the

bandgap.

We used the Kelvin probe force microscopy (KPFM) method to measure the work

function and affinities. Theoretically, by using KPFM, we can get the Fermi levels in

the semiconductors and the work function of the graphene. Then by combining

simulations, we can get the electron affinities of the semiconductors. Fig. S9 shows

the measured KPFM results. The work function of Au is 5.10 eV18. We can thus get

the work function of the graphene is 4.69 eV. The Fermi levels of the WSe2 and h-BN

are 4.94 and 4.66 eV, respectively. For the h-BN, it is an insulator. Here we simply

assume that it is intrinsic and the Fermi level is at the middle. Combining the bandgap

width of 5.54 eV, we can thus get the bottom of the conductance band (CB, electron

affinity) is 1.89 eV and the maximum valence band (VB) is 7.43 eV.

For the WSe2, to get the CB and VB, it is a little complicated. We obtained them

based on the following method. For a field-effect transistor (FET), while a voltage is

applied on the gate electrode, electrons or holes would be charged into the

semiconductor channel. The addition of the charge carriers should induce the shift of

the Fermi levels (Ef), which can be determined by the equation19,20 of

, (1)

, (2)

G ( ) / /D f i sV V E E q n q C

h

0 0( ) ( )(1 )v

c

s eE

E

n n p

d f d d f d





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where .

In the equations, VG is the applied gate voltage, VD is the gate voltage for the

semiconductor at the intrinsic state (corresponding to the intrinsic Fermi level Ei), q is

the electron charge, C is the gate dielectric capacitance per unit area, ns is the net

charge carrier concentration that is the difference of the electron (ne) and hole (ph)

concentration, m is the effective mass of the electrons or holes, kB is the Boltzmann

constant, d(Ɛ) is the density of states (for the two dimensional, it is independent on the

energy), f0 is the Fermi-Dirac function, T is the temperature (300 K here). Here the

FET is fabricated with a 19-nm-thick h-BN as the dielectric and a graphene fake as

the gate electrode. For the h-BN, ϵr=3.5. We can thus get that C=ϵrϵ0/d is about

1.6×10-3 F/m2.

Due to the KPFM measurement was performed in the atmosphere, we also

measured the WSe2 FET in the atmosphere. As shown in Fig. S10a, the WSe2 exhibits

a p-type behavior with the Dirac point at ~0.85 V. The p-type behavior is due to the

dopants from the atmosphere (moisture, oxygen, and so on)21. While we put the

device in the vacuum, it gets to be n-type again (Fig. S10b). For the four-layer WSe2,

the bandgap is 1.44 eV, as we obtained in the beginning. Based on our simulations,

we can get the band structure of the WSe2, as shown in Fig. S10c, where the bottom of

the CB is 3.61 eV, and the maximum VB is 5.05 eV.

In conclusion, with this method, we get that the bandgaps of the WSe2 and h-BN

are 1.44 and 5.54 eV, respectively. Their electron affinities are 3.61 and 1.89 eV,

respectively. The work function of the graphene is ~4.69 eV. The results are close to

021( ) ,

exp( ) 1F

B

md f E Ek T





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the reported work3,16,22-24. However, it is worth noting that our experiment was

performed in the atmosphere that should affect the results. In the main text, we use the

data from the literatures, since our results are close to them and the bandgap of the 2D

crystals often varies with the change of the thickness.





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Supplementary Figure 11 Estimation of the stored charges in the graphene

semi-floating gate. a, False colored SEM image of the used WSe2/h-BN/Graphene

floating-gate field-effect transistor (FG-FET) memory device for estimation. Inset:

Schematic plane of the FG-FET device. Different from SFG-FET, here the whole

WSe2 channel is over the graphene floating gate. Scale bar, 5 µm. b, Transfer

characteristic curves with VDS of +1 V. In order to estimate the charges stored in the

graphene semi-floating gate, we used the WSe2/h-BN/Graphene FG-FET memory to

do the calculation. Since the WSe2/h-BN/Graphene FG-FET has a similar energy band





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structure to the WSe2/h-BN/Graphene SFG-FET, it is reasonable to use such method

for the estimation. The amount of the charges stored in the graphene floating gate can

be estimated by the equation of 𝑛𝑛 = (𝛥𝛥𝛥𝛥 × 𝐶𝐶𝑐𝑐𝑐𝑐−𝑓𝑓𝑐𝑐)/𝑒𝑒, where e is the electron charge,

ΔV is the threshold voltage shift (55 V here for the scanning range of -40 to +40 V).

𝐶𝐶𝑐𝑐𝑐𝑐−𝑓𝑓𝑐𝑐 = Ɛ0Ɛ𝑆𝑆𝑆𝑆𝑆𝑆2/𝑑𝑑𝑆𝑆𝑆𝑆𝑆𝑆2 is the capacitance between the control gate and floating gate,

where Ɛ0 is the vacuum permittivity, ƐSiO2 and dSiO2 are the relative dielectric constant

(~3.9) and thickness (300 nm) of the SiO2, respectively25. We can get that the amount

of the stored charges is about 3.8×1012 cm-2.





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Supplementary Figure 12 Estimation of the trapped charges’ retention. The

image shows the retention curve of the threshold voltage of the FG-FET device. Inset:

Transfer characteristic curves (ID vs. VCG) obtained in different time intervals. The

voltage pulse applied on the control gate is +40 V and the duration time is 5 s. Here

we use a traditional method for FG-FET memories to estimate the retention of the

trapped charges in SFG-FETs25,26. Since the WSe2/h-BN/Graphene FG-FET has a

similar energy band structure to the WSe2/h-BN/Graphene SFG-FET, it is reasonable

to use such method for the estimation. The threshold voltages are dependent on the

trapped charges in FG-FET devices. It means that we can estimate the trapped charges’

retention based on the variation of the threshold voltage. As shown in the image, the

threshold voltage is almost exponentially dependent on the time. We can thus estimate

that 14.9±2.3% trapped charges would disappear after 10 years. The uncertainties are

obtained based on 10 measurements.





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Supplementary Figure 13 Electrical transport characterization of the WSe2 in

the WSe2/h-BN/Graphene based SFG-FET device with negative voltage pulses

applied on the Si control gate. a, ID-VDS curves across the WSe2 with different

negative voltage pulses applied on the Si control gate, exhibiting obviously rectifying

characteristics. b, The corresponding ID-VDS curves in logarithm scale. c, Charge

doping state and the corresponding energy band diagram of the heterostructure with a

negative voltage applied on the Si control gate (left in e). d, Charge doping state and

the corresponding energy band diagram of the heterostructure after the negative voltage

removed from the Si control gate (right in e). f, Energy band diagram along the WSe2

after the negative voltage removed from the control gate. While a negative voltage is

applied on the Si control gate, holes are accumulated in the WSe2 flake due to the field

effect. The applied voltage between the control gate and the WSe2 channel also leads to





22

a negative potential between the graphene and the WSe2, which makes the accumulated

holes tunnel from the WSe2 to the graphene. After the negative control gate voltage is

removed, the accumulated holes in the WSe2 disappear. However, the tunneled holes

are still trapped in the graphene due to the potential barrier of the h-BN. At this

situation, the trapped holes in the graphene induce electrons accumulated in the part of

the WSe2 over the graphene. WSe2 is intrinsically n-doped. The accumulated electrons

make the part over the graphene more deeply n-doped (we define this as n+-doped). It

means that the Fermi level in the WSe2 over the graphene is closer to the conductance

band (CB) than the other part. The alignment of the Fermi levels along the whole WSe2

channel produces a barrier height, resulting in the rectifying behaviors in Fig. S13A

(rectifying ratio is about 103). Different from p-n junctions, the transport here is

dominated by major charge carriers of electrons and the resulted barrier height is not

as high as that in p-n junctions. Therefore, it can be seen from Fig. S13B that the

reverse currents are still high. The results also indicate that the transport can be

modulated by varying the control gate voltage pulse.





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Supplementary Figure 14 Retention performance of the WSe2/h-BN/Graphene

SFG-FET device for the logic rectifier. With a voltage pulse of +40 V, the WSe2

behaves as a p-n diode and exhibits a rectifying characteristic with the negative bias

voltage filtered. The device indicates an excellent retention behavior.

Supplementary Figure 15 ISC and VOC as a function of the incident laser power,

where the device is operated with a +20 V voltage pulse applied on the Si control gate.

a, ISC as a function of the incident power, indicating that the ISC is almost linearly

dependent on the incident laser power. b, VOC as a function of the incident power,

indicating that the VOC is almost linearly dependent on the log(PLaser).





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Supplementary Table 1 Physical parameters of the resulted WSe2 p-n

junctions in the WSe2/h-BN/Graphene SFG-FET device excited by different

voltage pulses applied on the Si control gate. The results indicate that the ideality

factor n is around 2, the reverse saturation current I0 is from 10-2 to 5 fA, and the

series resistance RS is from several MΩ to several hundred MΩ. The physical

parameters can be calculated from the electrical transport (ID-VDS curve) across p-n

diodes expressed with the Shockley equation of

𝐼𝐼𝐷𝐷 =𝑛𝑛𝑉𝑉𝑇𝑇𝑅𝑅𝑠𝑠

𝑊𝑊 [𝐼𝐼0𝑅𝑅𝑆𝑆𝑛𝑛𝑉𝑉𝑇𝑇𝑒𝑒𝑒𝑒𝑒𝑒 (𝑉𝑉𝐷𝐷𝑆𝑆+𝐼𝐼0𝑅𝑅𝑆𝑆𝑛𝑛𝑉𝑉𝑇𝑇

)] − 𝐼𝐼027, (3)

where VT=kBT/e is the thermal voltage at the temperature T, kB is the Boltzmann

constant, e is the electron charge, I0 is the reverse saturation current, W is the Lambert

W function, n is the ideality factor and RS is the series resistance.





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Supplementary Table 2 Photovoltaic parameters of the resulted WSe2 p-n

junction in the WSe2/h-BN/Graphene SFG-FET device with a +40 V voltage

pulse applied on the control gate. The results indicate that the produced open-circuit

voltage VOC is ~0.8 V, the fill factor FF is over 0.53, the electrical power conversion

efficiency ηEPCE

is dependent on the incident laser power and up to 5.26% at 7.3 nW,

and the photovoltage responsivity is up to 0.8×109 V/W for 0.9 nW laser.





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Supplementary Figure 16 Nonvolatile programmable monolayer WSe2 p-n

junction based on the monolayer WSe2/h-BN/Graphene SFG-FET device

architecture, indicating that the monolayer WSe2 has similar behaviors. a, Optical

microscopy image of the monolayer WSe2 based SFG-FET device. b,

Photoluminescence (PL) spectrum of the monolayer WSe2 in Fig. S16a. c, Transfer

characteristic (ID-VCG) curves of the monolayer WSe2/h-BN/Graphene SFG-FET

device with different bias voltages VDS of ±2 V. d, Evolution of the currents (ID) across

the monolayer WSe2 with different voltage pulses (VCG-Pulse) applied on the control gate

and different bias voltages (VDS) on the monolayer WSe2. e, ID-VDS curve across the

monolayer WSe2 recorded at a -60 V voltage pulse applied on the Si control gate. f,

ID-VDS curve across the monolayer WSe2 recorded at a +60 V voltage pulse applied on





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the Si control gate. g, ID-VDS curves across the resulted monolayer WSe2 p-n junction

under the light illumination with different incident powers, indicating that the electrical

power is produced by the device under the light illumination. Here the p-n junction is

obtained with a 60 V voltage pulse. h, Produced electrical power (PEL) as a function of

the bias voltage (VDS) at different incident light powers. The monolayer of the WSe2 is

identified by the PL spectrum. As shown in Fig. S16b, the PL spectrum exhibits a single

prominent peak located at ~1.65 eV, which is consistent to the reported monolayer

WSe23.





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Supplementary Figure 17 Nonvolatile programmable WSe2 p-n junction based

on the WSe2/h-BN/Graphene SFG-FET device architecture with a monolayer

graphene embedded, indicating that the device has similar behaviors. a, Optical

microscopy image of the monolayer graphene based SFG-FET device. Here Gr denotes

graphene. b, Raman spectrum of the monolayer graphene in Fig. S17a. c, Transfer

characteristic (ID-VCG) curves of the SFG-FET device with different bias voltages VDS

of ±1 V. d, Evolution of the currents (ID) across the WSe2 with different voltage pulses

(VCG-Pulse) applied on the control gate and different bias voltages (VDS) on the WSe2. e,

ID-VDS curve across the WSe2 recorded at a -40 V voltage pulse applied on the Si

control gate. f, ID-VDS curve across the WSe2 recorded at a +40 V voltage pulse applied

on the Si control gate. g, ID-VDS curves across the resulted WSe2 p-n junction under the

light illumination with different incident powers, indicating that the electrical power is





29

produced by the device under the light illumination. Here the p-n junction is obtained

with a 40 V voltage pulse. h, Produced electrical power (PEL) as a function of the bias

voltage (VDS) at different incident light powers. The monolayer of the graphene is

identified by the Raman spectrum. As shown in Fig. S17b, the Raman spectrum

includes two symmetric peaks located at 1585 and 2693 cm-1, indicating the graphene is

monolayer7,8.

Supplementary Table 3 The performance of the device with different graphene

thicknesses, where the 1L stands for that the 2D crystal includes 1 layer, and so forth.

All of the p-n junctions are obtained with a 40 V voltage pulse. Here we used the

WSe2 with 3 or 4 layers and ~10 nm h-BN for the comparison. As shown in the table, it

seems that the rectifying ratio of the created p-n junctions decreases with the graphene

thickness increasing. That is to say, to get high-performance devices, a thinner

graphene should be embedded in the device architecture. In the table, Gr denotes

graphene.





30

Supplementary Table 4 The performance of the device with different h-BN

thicknesses, where the 6L stands for that the 2D crystal includes 6 layers, and so forth.

All of the p-n junctions are obtained with a 40 V voltage pulse. For the 6-layer WSe2

and 9-layer graphene, the rectifying ratio of the device decreases with the h-BN

thickness increasing. For the 4-layer WSe2, although the graphene thickness is a little

different, it can also be seen that the rectifying ratio decreases with the h-BN thickness

increasing. Thus, to obtain high-performance devices, a thinner h-BN should be

embedded in the device architecture. In the table, Gr denotes graphene.





31

Supplementary Table 5 The performance of the device with different WSe2

thicknesses, where the 7L stands for that the 2D crystal includes 7 layers, and so forth.

All of the p-n junctions are obtained with a 40 V voltage pulse except for the monolayer

WSe2 with a 60 V voltage pulse. 2D WSe2 is the transport channel in the device

architecture. The device performance should be affected by the WSe2 greatly. The

above table is the obtained results. As shown in the table, the monolayer and bilayer

WSe2 have obvious low rectifying ratios in comparison to the multiple layers. This

should be due to the larger bandgap of the monolayer and bilayer WSe2. As we all know,

the bandgap of the WSe2 increases with the thickness decreasing. The same trapped

charges in the semi-floating gate should have a slighter effect on the WSe2 with the

larger bandgap. On this principle, monolayer or bilayer WSe2 are not attractive for

rectifiers. However, it can be seen that the VOC obviously decreases with the thickness

increasing. This is also due to the thickness-dependent bandgap. Thus, for

optoelectronic devices in a photovoltage mode, monolayer and bilayer WSe2 should be

promising. In the table, Gr denotes graphene.





32

Supplementary Figure 18 Nonvolatile programmable WSe1.2Te0.8 p-n junction

based on the WSe1.2Te0.8/h-BN/Graphene SFG-FET device architecture, indicating

that the ambipolar WSe1.2Te0.8 has similar behaviors with such device architecture. a,

Optical microscopy image of the WSe1.2Te0.8/h-BN/Graphene based SFG-FET device.

b, AFM image of the device. c, Raman spectrum of the WSe1.2Te0.8. d, Transfer

characteristic (ID-VCG) curves of the SFG-FET device with different bias voltages VDS

of ±1 V. e, Evolution of the currents (ID) across the WSe1.2Te0.8 with different voltage

pulses (VCG-Pulse) applied on the control gate and different bias voltages (VDS) on the

WSe1.2Te0.8. f, ID-VDS curve across the WSe1.2Te0.8 recorded at a -40 V voltage pulse

applied on the Si control gate. g, ID-VDS curve across the WSe1.2Te0.8 recorded at a +40

V voltage pulse applied on the Si control gate. h, ID-VDS curves across the resulted

WSe1.2Te0.8 p-n junction under the light illumination with different incident powers,





33

indicating that the electrical power is produced by the device under the light

illumination. Here the p-n junction is obtained with a 40 V voltage pulse. i, Produced

electrical power (PEL) as a function of the bias voltage (VDS) at different incident light

powers. WSe1.2Te0.8 is a newly produced 2D TMD material, which exhibits ambipolar

behaviors28. The results indicate that the ambipolar WSe1.2Te0.8 exhibits similar

nonvolatile programmable p-n junction behaviors while it is embedded in the SFG-FET

device architecture. Different from the WSe2, the generated VOC is about 0.5 V, which is

a little smaller than the WSe2 due to the smaller bandgap.





34

Black phosphorus (BP) nonvolatile programmable p-n junction based on the

BP/h-BN/Graphene SFG-FET device. Few-layer BP is a newly exploited 2D

material29,30. It is a semiconductor with a direct bandgap regardless of its thickness.

Few-layer BP often exhibits an ambipolar behavior with a remarkable mobility up to

1,000 cm2V-1s-1 while it serves as a field-effect transistor. Based on such ambipolar

behavior, nonvolatile p-n junction memories were also successfully achieved in

few-layer BP flakes using our designed BP/h-BN/Graphene SFG-FET device structure.

Supplementary Figure 19 Field-effect transistor (FET) characterization of a

typical few-layer BP flake based device with a bias voltage of 50 mV applied

between the drain (D) and source (S). The result indicates that the simple pure BP

FET exhibits a high on/off ratio over 104. While the back gate voltage is swept from

-40 V to 40 V, the current first decreases to a minimum point at ~+12 V, and then

increases with the gate voltage increasing. This indicates that the hole and electron

doping can be both achieved in the BP flake, and it is intrinsically p-doped. The inset





35

is an optical microscopy image of the BP FET device, where the BP is fabricated on a

Si substrate with a 300-nm-thick thermal oxide film.

Supplementary Figure 20 Schematic SFG-FET device configuration based on

stacked BP/h-BN/Graphene van der Waals heterostructures, where the bottom Si

serves as the control gate (CG), graphene serves as the semi-floating gate (SFG), BP

serves as the p-n channel, SiO2 and h-BN serve as the dielectric. Only part of the BP

channel is aligned over the graphene.





36

Supplementary Figure 21 A typical BP/h-BN/Graphene heterostructure based

SFG-FET device. a, Optical microscopy image of the fabricated BP/h-BN/Graphene

SFG-FET. Scale bar, 8 µm. Gr denotes graphene. b, ID-VDS curve across the BP without

any gate voltage applied, indicating that the Au/Cr electrodes make good an ohmic

contact to the BP flake. c, Raman spectroscopy characterization of the

BP/h-BN/Graphene heterostructure. The three spectra correspond to the three different

parts as indicated. The Raman spectra exhibit typical features of the few-layer BP

(three peaks at 361 cm-1, 440 cm-1 and 468 cm-1)31, h-BN (one peak at 1365 cm-1)6 and

few-layer graphene (two peaks at 1582 cm-1 and 2707 cm-1)7, respectively, indicating

all of them are few-layer structures.





37

Supplementary Figure 22 Atomic force microscopy (AFM) characterization of

the BP/h-BN/Graphene heterostructure. The results indicate that the BP, h-BN and

graphene are 5 nm, 9 nm, 2.5 nm in thickness, respectively, indicating that all of them

include a few layers. The AFM images also indicate that bubbles (spots) are trapped

in the 2D crystals. The formation of the bubbles should have a similar mechanism to

the WSe2/h-BN/Graphene heterostructure shown in Fig. S4c. They contain air,

residues and other inevitable contaminants, like nanoparticles from the surroundings.





38

Supplementary Figure 23 Electrical transport characterization of the BP in the

BP/h-BN/Graphene based SFG-FET device with negative voltage pulses applied

on the Si control gate. a, ID-VDS curve across the BP recorded at a -40 V voltage pulse

applied on the Si control gate. Inset: Schematic energy band diagram of the resulted p-n

junction. b, I-V curves across the BP with different negative voltage pulses applied on

the control gate. c, Charge doping state of the heterostructure with a negative voltage

applied on the control gate. d, Charge doping state of the heterostructure after the

negative voltage removed from the control gate. e, Schematic energy band diagrams of

the BP/h-BN/Graphene heterostructure at different states. Left to right: with a negative

voltage applied on the control gate, flat energy band diagram and after the negative





39

voltage removed from the control gate, respectively. Few-layer BP is a semiconductor

with an electron affinity of ~4.13 eV and a direct bandgap of ~0.3 eV dependent on the

thickness32,33. Few-layer graphene has a work function around 4.6 eV24. However,

h-BN has a large bandgap (5.2-5.9 eV) and a small electron affinity (2-2.3 eV)23.

Therefore, there are potential barriers for both electrons and holes between the

graphene and the BP in the designed heterostructure (Middle in Fig. S23e). While a

negative voltage is applied on the Si control gate, holes are accumulated in the BP flake

due to the field effect. The applied voltage between the control gate and the BP channel

also leads to a negative potential between the graphene and the BP, which makes the

accumulated holes tunnel from the BP to the graphene (Fig. S23c and Left in Fig. S23e).

After the negative voltage is removed, the accumulated holes in the BP disappear.

However, the holes are still trapped in the graphene due to the potential barrier of the

h-BN. Under this situation, the trapped holes in the graphene would induce electrons in

the part of the BP over the graphene, making the part of the BP over the graphene

n-doped (Fig. S23d and Right in Fig. S23e). As discussed above, BP is intrinsically

p-doped. By this way, p-n junction is achieved along the BP flake. Fig. S23a shows an

obvious p-n junction rectifying behavior while a -40 V voltage pulse is applied on the

Si control gate. Fig. S23b exhibits that the rectifying behavior can be modulated by

varying the voltage pulse applied on the Si control gate due to that the control gate

voltage can be used to tune the trapped holes in the graphene semi-floating gate.





40

Supplementary Figure 24 Electrical transport characterization of the BP in the

BP/h-BN/Graphene based SFG-FET device with positive voltage pulses applied

on the Si control gate. a, ID-VDS curve across the BP with a +40 V voltage pulse

applied on the Si control gate. b, ID-VDS curves across the BP with different positive

voltage pulses applied on the Si control gate. c, Charge doping state and the

corresponding energy band diagram of the heterostructure (left in e) with a positive

voltage applied on the Si control gate. d, Charge doping state and the corresponding

energy band diagram of the heterostructure (right in e) after the positive voltage

removed from the Si control gate. f, Energy band diagram along the BP after the

positive voltage removed from the control gate. While a positive voltage is applied on

the Si control gate, electrons are accumulated in the BP flake due to the field effect. The

applied voltage between the control gate and the BP channel also leads to a positive





41

potential between the graphene and the BP, which makes the accumulated electrons

tunnel from the BP to the graphene. After the positive control gate voltage is removed,

the accumulated electrons in the BP disappear. However, the tunneled electrons are still

trapped in the graphene due to the potential barrier of the h-BN. At this situation, the

trapped electrons in the graphene induce holes accumulated in the part of the BP over

the graphene. BP is intrinsically p-doped. The accumulated holes make the part over the

graphene more deeply p-doped (we define this as p+-doped). It means that the Fermi

level in the BP over the graphene is closer to the valence band (VB) than the other part.

The alignment of the Fermi levels along the whole BP channel produces a barrier height.

It is noted here that the bandgap of the few-layer BP is only 0.3 eV32,33, which is so

small that the resulted barrier height is pretty low, leading to the rectifying behavior is

not obvious, as shown in Fig. S24a. The transport can also be modulated by the control

gate voltage pulse (Fig. S24b).





42

Supplementary Figure 25 Transfer characteristics of the BP/h-BN/Graphene

SFG-FET device (current across the BP ID vs. voltage applied on the Si control

gate VCG) at different bias voltages applied on the BP of +0.5 V and -0.5 V. Due to

the charge trapping in the graphene semi-floating gate, the transfer characteristics

exhibit an obvious large hysteresis that can be developed for memories. Moreover, the

results indicate that the characteristic of the current across the BP with VDS of +0.5 V

and -0.5 V is different. It is noted that the characteristics are also reverse to that of the

WSe2/h-BN/Graphene SFG-FETs due to that here the +0.5 V is the reverse bias voltage

and the -0.5 V is the forward bias voltage, which are different from the

WSe2/h-BN/Graphene devices due to the BP is p-type.





43

Supplementary Figure 26 Evolution of the currents across the BP with different

voltage pulses applied on the Si control gate and VDS on the BP channel. The

results indicate that the currents can be kept well after 1200 seconds (s). A +20 V

positive voltage pulse on the Si control gate makes the BP over the graphene p+-doped

(the BP is p+-p junction). At this situation, the currents across the BP at the positive and

negative bias voltage are both at high levels (“on” state for memories). A -20 V

negative voltage pulse makes the BP as a p-n junction. At this situation (“off” state), the

currents across the BP at the positive and negative bias voltage are obviously different.

The positive bias voltage is a reverse bias voltage, leading to a pretty low current state,

while the negative bias voltage is a forward bias voltage, leading to a higher current

state.





44

Supplementary Figure 27 Switching behavior between the erase (“ON”) and

program (“OFF”) state of the BP/h-BN/Graphene SFG-FET based memory

device.





45

Supplementary Figure 28Photovoltaic characterization of the produced BP p-n

junction in the BP/h-BN/Graphene SFG-FET with a -40 V voltage pulse applied

on the Si control gate. a, ID-VDS curves across the BP at different incident light powers.

b, Electrical power (PEL) vs. bias voltage (VDS) at different incident light powers. The

light used here is a laser with a wavelength of 638 nm. Its power can be tuned

continually. The results indicate that the achieved p-n junction exhibits an obvious

photovoltaic behavior.





46

Supplementary Table 6 Photovoltaic parameters of the resulted BP p-n

junction in the BP/h-BN/Graphene SFG-FET device with a -40 V voltage pulse

applied on the control gate. The results indicate that the produced open-circuit

voltage VOC is ~0.1 V, the fill factor FF is ~0.3, and the electrical power conversion

efficiency ηEPCE

is dependent on the incident laser power and up to 0.07% at ~0.50

μW, which is competitive to the reported BP p-n junctions12.

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Dong Li, Mingyuan Chen, Zhengzong Sun, Peng Yu, Zheng Liu ... · I o ed. © M Publisher L S N A eserved. SUPPLEMENTARY INFORMATION DOI: 10.1038/NNANO.2017.104 NATURE NANOTECHNOLOGY