DIGITAL ELECTRONICS d flip FLOP

8/14/2019 DIGITAL ELECTRONICS d flip FLOP

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Chapter 14

Sequential logic, Latches andSequential logic, Latches and

FlipFlip--FlopsFlops


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Ch14L6-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2

Lesson 6

D- Flip Flop and D-Latch


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D- Flip-Flop + ve edge triggered

Output Q

and Q

Q

Q

D

Q

QD D-FF

Clock

D

+ve Edgetriggered

circuit


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D- Flip-Flop + ve edge triggered

with clear and preset Output Q

and Q

Q

Q

D

Q

QD D-FF

Clock

D

+ve Edgetriggered

circuit

R

SPreset

CLR

clear

PR


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D- Flip Flop

1. It has edge trigger clock input so that the output

state changes only on a clock edge2. The NANDs S input of level clocked SR latch is

called D- input and R input given input after a

not operation on the D-input.

3. Second input of both NANDs is common

4. Clock input has an additional circuitry to make

the transition of Q as per D at an instance

corresponding to an edge at the clock- input


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D- Flip Flop

Three input cross coupled NANDs

Third input of lower NAND connects the Q

output

Third input of upper NAND connects the Qoutput.

There is no unstable condition in D-FF

state table


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Clock edge Symbolicrepresentation

Up side arrow corresponds +ve edgeinstance (0 to 1 transition only)


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Timing Diagram

Refer Text


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D = 0 at edge transition (Q = D after a

delay)

Output Q resets to 0 and Qn becomes = 1

after a propagation delay when +ve edgeoccurs because J = 0 and K = 1

Output Q sets to 1 and Qn becomes = 0

after a propagation delay when +ve edgeoccurs because J = 1 and K = 0

Q becomes same as D after a clock edge.

Qn+1 D


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+ve edge triggered D FF

Inputs Output State

CLK Qn D Qn+1 Qn+1

X means either 1 or 0 input, Qn+1 means next

state after nth clock input

1 0 1 Qn Qn No change

0 1 0 Qn Qn No change

X D D Q same as D

X X Qn Qn No change


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D- Latch (Level clocked D)

Output Q

and Q

Q

Q

D

Q

QD D-latch

Clock

D

Levelclocked


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D- Latch

1. It has level clocking input so that the

output state changes only during level 12. The NANDs S input of level clocked SR

latch is called D- input and R input given

input after a not operation on the D-input.3. Second input of both NANDs is common

4. Clock input has no additional circuitry tomake the transition of Q as per D at levelcorresponding to 1 at the clock - input


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D- Latch (D- Transparent latch)

There is no unstable condition in D-latch state table

Q- is transparent to D during clock =

1


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Clock level Symbolic

representation

corresponds level 1 clocking input


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Timing Diagram

Refer Text


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D = 0 or 1 at clock = 1 transition (Q = D

after a delay)

Output Q resets to 0 and Qn becomes = 1

after a propagation delay during clock = 1

because D = 0

Output Q sets to 1 and Qn becomes = 0after a propagation delay during clock = 1

because D = 1

Q becomes same as D during clock = 1.

Qn+1 D


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D Latch

Inputs Output State

D Clock Qn+1 Qn+1

X means either 1 or 0 input, Qn+1 means next

state after nth clock input

X 0 Qn Qn No change

1 1 1 0 Qn+1 D

0 1 0 1 Qn+1 D


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D- Latch with D input from Q

Output Q

and Q

Q

QD

Q

QD

1

D-Latch

Clock

D

Levelclocked


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D input with feedback from Qn

When clock = 1, the output changes 1 to 0and 0 to 1 at regular intervals with interval

= propagation delay of the D-latch. We get

the pulses at the output

When clock = 0, the output freeze, Q

cannot change when clock = 0


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Summary


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We learnt that in D- edge triggered FF:

Because K is always complement of J,

and D input is at J, the output of D-flip-flops changes to same state as D input on

edge at D-input. [After a period equal to

propagation delay.]

D-latch has no third input at the cross-

coupled NANDs


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End of Lesson 6 on

D- Flip Flop and D-Latch


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THANK YOU

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DIGITAL ELECTRONICS d flip FLOP