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LatchesFlip-Flops

VHDL Descriptions

Latches and Flip-Flops

Dr DC Hendry

March 6, 2006

Dr DC Hendry Latches and Flip-Flops
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LatchesFlip-Flops

VHDL Descriptions

1 LatchesSR LatchClocked SR LatchD LatchSchematic Symbols

2 Flip-Flops

3 VHDL Descriptions

The D LatchThe D Flip-FlopSet and Reset lines

http://find/


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LatchesFlip-Flops

VHDL Descriptions

SR LatchClocked SR LatchD LatchSchematic Symbols

SR Latch

The basic SR latch can be constructed as:

Q

QR

S

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LatchesFlip-Flops

VHDL Descriptions


SR Latch


Q

QR

S

and exhibits the behaviour:

1 Setting S(Set) to 0 with Rat 1 causes Qto become1and Qto become 0.


SR L h
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LatchesFlip-Flops

VHDL Descriptions


SR Latch


Q

QR

S



2 Setting R(Reset) to 0 with Sat 1 causes Qto become 0and Qto become 1.


SR L t h
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LatchesFlip-Flops

VHDL Descriptions


SR Latch


Q

QR

S




3 When S and Rare at 1 Q and Q retain their last values.


SR Latch


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LatchesFlip-Flops

VHDL Descriptions


SR Latch


Q

QR

S




3 When S and Rare at 1 Q and Q retain their last values.

4 S and Rshould not both be 0 at the same time.


SR Latch
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LatchesFlip-Flops

VHDL Descriptions


SR Latch Waveform

For an SR latch the following waveform applies. No logic delaysare shown in this diagram:

S

R


SR Latch
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LatchesFlip-Flops

VHDL Descriptions


SR Latch Waveform

For an SR latch the following waveform applies. No logic delaysare shown in this diagram:

S

R

Q

Q


L hSR Latch
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LatchesFlip-Flops

VHDL Descriptions


Clocked SR Latch

1 While the SR latch is used in some simple circuits, it isprimarily used as a building block for clocked latches.


L t hSR Latch
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LatchesFlip-Flops

VHDL Descriptions

Clocked SR LatchD LatchSchematic Symbols

Clocked SR Latch


2 In a clocked latch, the S and R inputs are only obeyedwhenthe clock signal is active.


LatchesSR Latch
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LatchesFlip-Flops

VHDL Descriptions


Clocked SR Latch



3 For a positivelatch the clock is considered active whenit is1, and 0 for a negative latch.


LatchesSR Latch
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LatchesFlip-Flops

VHDL Descriptions


Clocked SR Latch



3 For a positivelatch the clock is considered active whenit is1, and 0 for a negative latch.

4 Schematic for a Clocked SR Latch:

Q

Q

R

S

ClkDr DC Hendry Latches and Flip-Flops

LatchesSR LatchC S
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LatchesFlip-Flops

VHDL Descriptions


Waveform of Clocked SR Latch

Waveform (positive latch):

Clk

S

R

Q

Q


Latches SR LatchCl k d SR L h
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LatchesFlip-Flops

VHDL Descriptions


D Latch

1 By far the most important of the clockedlatches however isthe clocked D latch.


Latches SR LatchCl k d SR L t h


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Flip-FlopsVHDL Descriptions


D Latch


2 This latch has a single data line, D, as input.


Latches SR LatchClocked SR Latch


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D Latch



3 The effect is that D is only copied to theoutput Q when the

clock is active.


Latches SR LatchClocked SR Latch
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D Latch



3 The effect is that D is only copied to theoutput Q when the

clock is active.

4

Q

Q

Clk

D


LatchesFli Fl

SR LatchClocked SR Latch


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Waveforms for D Latch:

Clk

D

Q

Q


LatchesFli Fl

SR LatchClocked SR Latch
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Schematic Symbols

The schematic symbol for aclocked SR latch is:

Clk

Q

QR

S

For the basic SR latch, omit theClk terminal.

and the schematic symbol for aD latch is:

Clk

Q

Q

D


LatchesFlip Flops
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Master Slave Flip-Flop

The master-slave flip-flop is perhaps theeasiest to understand.The circuit diagram, build with two D latches is as follows:


LatchesFlip Flops
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Master Slave Flip-Flop

The master-slave flip-flop is perhaps theeasiest to understand.The circuit diagram, build with two D latches is as follows:

Clk

Q

Q

D

Clk

Q

Q

DD Q

Clk

Q

Q


LatchesFlip-Flops
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D Flip-Flop Waveforms

Clk

Q

Q

D

Clk

Q

Q

DD Q

Clk

Q

Q

Clk

Clk

D

Q

Q


LatchesFlip-Flops
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Flip FlopsVHDL Descriptions

Flip-Flop Schematic Symbols

The sampling nature of the flip-flop is denoted by asmalltriangle on the clock line of the device. The presence of anegation bubble indicates a negative edge triggered device.


LatchesFlip-Flops
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p pVHDL Descriptions

Flip-Flop Schematic Symbols

The sampling nature of the flip-flop is denoted by asmalltriangle on the clock line of the device. The presence of anegation bubble indicates a negative edge triggered device.

Symbol for a positive edgetriggered flip-flop:

Q

Q

D

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LatchesFlip-Flops

The D LatchThe D Flip-Flop


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VHDL Descriptions Set and Reset lines

The D Latch

The following code describes a D latch. Note that bothof theinputs to the circuit, clk and D are in the sensitivity list of theprocess.

library ieee;use ieee.std logic 1164.all;

entity dlatch is

port( clk : in std logic;d : in std logic;

q : out std logic;qbar : out std logic);

end entity dlatch;


LatchesFlip-Flops

The D LatchThe D Flip-FlopS
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The D Latch

The following code describes a D latch. Note that bothof theinputs to the circuit, clk and D are in the sensitivity list of theprocess.


entity dlatch is

port( clk : in std logic;d : in std logic;

q : out std logic;qbar : out std logic);

end entity dlatch;

architecture rtl of dlatch is

begin

dl : process (clk, d)begin

if clk = 1 thenq


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The D Flip-flop


entity dff is

port(clk : in std logic;d : in std logic;q : out std logic;qbar : out std logic);

end entity dff;


LatchesFlip-Flops

VHDL D i ti

The D LatchThe D Flip-FlopS t d R t li
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The D Flip-flop


entity dff is

port(clk : in std logic;d : in std logic;q : out std logic;qbar : out std logic);

end entity dff;

architecture rtl of dff is

begin

ff : process (clk)begin

if clkevent and clk = 1 thenq


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Coding the D Flip-flop

Note the following points about this code:

1 The code clkevent and clk = 1 denotes a risingedge

on the clock signal.


LatchesFlip-Flops

VHDL Descriptions

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1 The code clkevent and clk = 1 denotes a risingedge

on the clock signal.2 On a rising edge d is copied to q, and the inverse to qbar.


LatchesFlip-Flops

VHDL Descriptions



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1 The code clkevent and clk = 1 denotes a risingedgeon the clock signal.

2 On a rising edge d is copied to q, and the inverse to qbar.

3 Note that we must use qbar


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1 The code clkevent and clk = 1 denotes a risingedgeon the clock signal.

2 On a rising edge d is copied to q, and the inverse to qbar.

3 Note that we must use qbar


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p

Set and Reset Lines

Many flips-flops (and latches) need to beplaced into aspecificstart up state. When powered up a flip-flop or latch takes arandom state. Therefore many flip-flops include a setline, a reset

line, or both.


LatchesFlip-Flops

VHDL Descriptions

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Set and Reset Lines


line, or both.1 A setline when active causes the flip-flop qoutput togo to

1.


LatchesFlip-Flops

VHDL Descriptions



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Set and Reset Lines



1.

2 A resetline when active causes the flip-flop qoutput togo to

0.


LatchesFlip-Flops

VHDL Descriptions

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Set and Reset Lines



1.

2 A resetline when active causes the flip-flop qoutput togo to

0.3 Such lines may be either synchronousorasynchronous.


LatchesFlip-Flops

VHDL Descriptions



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D Flip-Flop with Synchronous Set

The VHDL code for a D flip-flop with active low synchronous set:


entity dffs is

port(clk : in std logic;set n : in std logic;d : in std logic;q : out std logic;qbar : out std logic);

end entity dffs;


LatchesFlip-Flops

VHDL Descriptions



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D Flip-Flop with Synchronous Set

The VHDL code for a D flip-flop with active low synchronous set:


entity dffs is

port(clk : in std logic;set n : in std logic;d : in std logic;q : out std logic;qbar : out std logic);

end entity dffs;

architecture rtl of dffs is

begin

ff : process(clk)begin

if clkevent and clk = 1 theif set n = 0 then

q


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Waveform for synchronous set

Clk

set n

q

Note that effect of the set n line does occur until the next activeedge of the clock signal.


LatchesFlip-Flops

VHDL Descriptions

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D Flip-Flop with AsynchronousReset

The VHDL code for a D flip-flop with active low asynchronousreset:


entity dffr is

port(clk : in std logic;rst n : in std logic;d : in std logic;

q : out std logic;qbar : out std logic);end entity dffr;


LatchesFlip-Flops

VHDL Descriptions



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D Flip-Flop with AsynchronousReset

The VHDL code for a D flip-flop with active low asynchronousreset:


entity dffr is

port(clk : in std logic;rst n : in std logic;d : in std logic;

q : out std logic;qbar : out std logic);end entity dffr;

architecture rtl of dffr is

begin

ff : process(clk, rst n)begin

if rst n = 0 thenq


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Waveforms for asynchronous reset

Clk

rst n

q

For the asynchronous reset line, the effect is immediate.


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