DIGITAL ELECTRONICS JK FLIP FLOP

8/14/2019 DIGITAL ELECTRONICS JK FLIP FLOP

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Chapter 14

Sequential logic, Latches andSequential logic, Latches and

FlipFlip--FlopsFlops


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Ch14L4-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2

Lesson 4

JK Flip Flop


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JK Flip-Flop ve edge triggered

Output Q

and Q

Q

Q

K

J

Q

QJ

K

SR Latch

Clock

Clock

-ve Edgetriggered

circuit

R

SPreset

clear

PRCLR


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JK Flip-Flop + ve edge triggered

Output Q

and Q

Q

Q

K

J

Q

QJ

K

JK

FFClock

Clock

+ve Edgetriggered

circuit

R

SPreset

clear

PR

CLR


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JK Flip Flop

1. It has edge trigger clock input so that the outputstate changes only on a clock edge

2. The NANDs S input of level clocked SR latch

labeled asJinput andR input as Kinput.3. Second input of both NANDs is common

4. Clock input has an additional circuitry to make

the J and K inputs transparent at an instancecorresponding to an edge at the clock input


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JK Flip Flop

Three input cross coupled NANDs

Third input of lower NAND connects the Q

output

Third input of upper NAND connects the Qoutput.

There is no unstable condition in J-K FF

state table


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Clock Symbolic representation

A bubble followed by a triangle at a clock

input represents negative edge triggeredclock and output will correspond to the J

and K inputs at that -ve edge instance only

A triangle at a clock input represents

positive edge triggered clock and output

will correspond to the J and K inputs atthat +ve edge instance only


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Clock edge Symbolicrepresentation

Down side arrow corresponds -ve edgeinstance (0 to 1 transition only)

Up side arrow corresponds +ve edge

instance (1 to 0 transition only)


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J = 0 and K = 0 No change state Output Q remains same as before

even after the clock edge when J = 0and K =0


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J = 0, K = 0

Inputs Output State

Clock Qn J Qn K Qn+1 Qn+1

X means either 1 or 0 or +ve edge or -ve edge

input, Qn+1 means next state after nth clock input

X 0 0 1 0 Qn Qn No change

X 1 0 0 0 Qn Qn No change


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J = 1 and K = 0 (Q set to 1) Output Q sets to 1 and Qn becomes =

0 after the clock edge when J = 1 andK =0


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J = 1, K = 0 -ve edge triggered JK

Inputs Output State


X means either 1 or 0 input, Qn+1 means next

state after nth clock input

1 0 1 1 0 Qn Qn No change


X 1 X 0 Qn Qn No change

X 1 X 0 1 0 Sets to 1


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J = 0 and K = 1 (Q reset to 1) Output Q resets to 0 and Qn becomes

= 1 after the clock edge when J = 0and K = 1


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Inputs Output State





0 1 0 0 1 Qn

Qn No change


X 0 X 1 0 1 Resets to 0


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J = 1 and K = 1 (Q Toggles) Output Q resets to 0 and Qn becomes = 1

in case Q was 1 earlier Qnwas 0 and after

the clock edge when J = 1 and K = 1

Output Q sets to 1 and Qn becomes = 0

in case Q was 0 earlier Qn was 1 and afterthe clock edge when J = 1 and K = 1

Q toggles (complements the nth state after

the nth clock transition)

Qn+1Qn


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Inputs Output State





0 1 1 0 1 Qn

Qn No change


1 1 Qn Qn Toggles


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Use of Clear and Preset Inputs

JK FF may have connections to the twoinputs of cross coupled NANDs. It can be

used as R (clear) and S (preset), to preset Q

to 1 or to reset Q to 0.


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Summary


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We learnt that in JK edge triggered FF:

When J = 1 and K =1, the output of flip-flop

toggles (changes to opposite state) on clockedge.

When J = 0 and K =0, the output of flip-flop

does not change on clock edge. When J = 0 and K =1, the output Q resets to 0

after clock edge.

When J = 1 and K =0, the output Q sets to 1after clock edge


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End of Lesson 4 on

JK Flip Flop


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THANK YOU

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DIGITAL ELECTRONICS JK FLIP FLOP