Flip-Flop Electronics) - Wikipedia, The Free Encycloped

An RS latch, constructed from a pair

of cross-coupled NOR gates. Red and

black mean logical '1' and '0',

respectively.

Flip-flop (electronics)From Wikipedia, the free encyclopedia

In electronics, a flip-flop or latch is a circuit that has two stable statesand can be used to store state information. The circuit can be made tochange state by signals applied to one or more control inputs and willhave one or two outputs. Flip-flops and latches are a fundamentalbuilding block of digital electronics systems used in computers,communications, and many other types of systems.

Flip-flops and latches are used as data storage elements. Such datastorage can be used for storage of state, and such a circuit is described assequential logic. When used in a finite-state machine, the output andnext state depend not only on its current input, but also on its currentstate (and hence, previous inputs.) It can also be used for counting ofpulses, and for synchronizing variably-timed input signals to somereference timing signal.

Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered); the simple

ones are commonly called latches.[1] The word latch is mainly used for storage elements, while clocked devices

are described as flip-flops.[2]

Contents

1 History2 Implementation3 Flip-flop types

3.1 Simple set-reset latches3.1.1 SR NOR latch3.1.2 SR NAND latch3.1.3 JK latch

3.2 Gated latches and conditional transparency3.2.1 Gated SR latch3.2.2 Gated D latch3.2.3 Earle latch

3.3 D flip-flop3.3.1 Classical positive-edge-triggered D flip-flop3.3.2 Master–slave pulse-triggered D flip-flop3.3.3 Edge-triggered dynamic D flip-flop

3.4 T flip-flop3.5 JK flip-flop

4 Metastability5 Timing considerations

5.1 Setup and hold times5.2 Propagation delay

Flip-flop (electronics) - Wikipedia, the free encyclopedia http://en.wikipedia.org/wiki/Flip-flop_(electronics)

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Flip-flop schematics from the Eccles and Jordan

patent filed 1918, one drawn as a cascade of

amplifiers with a positive feedback path, and the

other as a symmetric cross-coupled pair

6 Generalizations7 See also8 References

History

The first electronic flip-flop was invented in 1918 by

William Eccles and F. W. Jordan.[3][4] It was initially calledthe Eccles–Jordan trigger circuit and consisted of two

active elements (vacuum tubes).[5] Such circuits and theirtransistorized versions were common in computers evenafter the introduction of integrated circuits, though flip-flops

made from logic gates are also common now.[6][7]

Early flip-flops were known variously as trigger circuits ormultivibrators. A multivibrator is a two-state circuit; theycome in several varieties, based on whether each state isstable or not: an astable multivibrator is not stable in eitherstate, so it acts as a relaxation oscillator; a monostablemultivibrator makes a pulse while in the unstable state, thenreturns to the stable state, and is known as a one-shot; abistable multivibrator has two stable states, and this is theone usually known as a flip-flop. However, this terminologyhas been somewhat variable, historically. For example:

1942 – multivibrator implies astable: "Themultivibrator circuit (Fig. 7-6) is somewhat similarto the flip-flop circuit, but the coupling from theanode of one valve to the grid of the other is by acondenser only, so that the coupling is not

maintained in the steady state."[8]

1942 – multivibrator as a particular flip-flopcircuit: "Such circuits were known as 'trigger' or'flip-flop' circuits and were of very greatimportance. The earliest and best known of thesecircuits was the multivibrator."[9]

1943 – flip-flop as one-shot pulse generator: "Itshould be noted that an essential difference between the two-valve flip-flop and the multivibrator is

that the flip-flop has one of the valves biased to cutoff."[10]

1949 – monostable as flip-flop: "Monostable multivibrators have also been called 'flip-flops'."[11]

1949 – monostable as flip-flop: "... a flip-flop is a monostable multivibrator and the ordinary

multivibrator is an astable multivibrator."[12]

According to P. L. Lindley, a JPL engineer, the flip-flop types discussed below (RS, D, T, JK) were firstdiscussed in a 1954 UCLA course on computer design by Montgomery Phister, and then appeared in his book

Logical Design of Digital Computers.[13][14] Lindley was at the time working at Hughes Aircraft under Dr.Eldred Nelson, who had coined the term JK for a flip-flop which changed states when both inputs were on. The


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A traditional flip-flop circuit based on bipolar

junction transistors

other names were coined by Phister. They differ slightly from some of the definitions given below. Lindleyexplains that he heard the story of the JK flip-flop from Dr. Eldred Nelson, who is responsible for coining theterm while working at Hughes Aircraft. Flip-flops in use at Hughes at the time were all of the type that came tobe known as J-K. In designing a logical system, Dr. Nelson assigned letters to flip-flop inputs as follows: #1: A &B, #2: C & D, #3: E & F, #4: G & H, #5: J & K.

Implementation

Flip-flops can be either simple (transparent) or clocked; the

transparent ones are commonly called latches.[1] The wordlatch is mainly used for storage elements, while clocked

devices are described as flip-flops.[2]

Simple flip-flops can be built around a pair of cross-coupledinverting elements: vacuum tubes, bipolar transistors, fieldeffect transistors, inverters, and inverting logic gates have allbeen used in practical circuits. Clocked devices are speciallydesigned for synchronous systems; such devices ignore theirinputs except at the transition of a dedicated clock signal(known as clocking, pulsing, or strobing). Clocking causesthe flip-flop to either change or retain its output signal basedupon the values of the input signals at the transition. Someflip-flops change output on the rising edge of the clock, others on the falling edge.

Since the elementary amplifying stages are inverting, two stages can be connected in succession (as a cascade)to form the needed non-inverting amplifier. In this configuration, each amplifier may be considered as an activeinverting feedback network for the other inverting amplifier. Thus the two stages are connected in anon-inverting loop although the circuit diagram is usually drawn as a symmetric cross-coupled pair (both thedrawings are initially introduced in the Eccles–Jordan patent).

Flip-flop types

Flip-flops can be divided into common types: the SR ("set-reset"), D ("data" or "delay"[15]), T ("toggle"), andJK types are the common ones. The behavior of a particular type can be described by what is termed thecharacteristic equation, which derives the "next" (i.e., after the next clock pulse) output, Qnext, in terms of theinput signal(s) and/or the current output, Q.

Simple set-reset latches

SR NOR latch

When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and Rstand for set and reset. It can be constructed from a pair of cross-coupled NOR logic gates. The stored bit ispresent on the output marked Q.

While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant state, with Q thecomplement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced high, andstays high when S returns to low; similarly, if R is pulsed high while S is held low, then the Q output is forced


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An RS latch, constructed from a pair

of cross-coupled NOR gates (an

animated picture). Red and black mean

logical '1' and '0', respectively.

The symbol for

an SR NOR latch

An SR latch

low, and stays low when R returns to low.

SR latch operation

S R Action

0 0 No Change

0 1 Q = 0

1 0 Q = 1

1 1 Restricted combination

The R = S = 1 combination is called a restricted combination or aforbidden state because, as both NOR gates then output zeros, it breaksthe logical equation Q = not Q. The combination is also inappropriate in circuits where both inputs may go lowsimultaneously (i.e. a transition from restricted to keep). The output would lock at either 1 or 0 depending onthe propagation time relations between the gates (a race condition). In certain implementations, it could alsolead to longer ringings (damped oscillations) before the output settles, and thereby result in undetermined values(errors) in high-frequency digital circuits. Although this condition is usually avoided, it can be useful in someapplications.

To overcome the restricted combination, one can add gates to the inputs that would convert (S,R) = (1,1) toone of the non-restricted combinations. That can be:

Q = 1 (1,0) – referred to as an S-latchQ = 0 (0,1) – referred to as an R-latchKeep state (0,0) – referred to as an E-latch

Alternatively, the restricted combination can be made to toggle the output. The result is the JK latch.

Characteristic: Q+ = R'Q + R'S or Q+ = R'Q + S.[16]

SR NAND latch

This is an alternate model of the simple SR latch built with NAND (notAND) logic gates. Set and reset now become active low signals, denotedS and R respectively. Otherwise, operation is identical to that of the SRlatch. Historically, SR-latches have been predominant despite the

notational inconvenience of active-low inputs.[citation needed]


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Symbol for an

SR NAND latch

SR latch operation

S R Action

0 0 Restricted combination

0 1 Q = 1

1 0 Q = 0

1 1 No Change


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A gated SR latch circuit diagram constructed from

NOR gates.

JK latch

The JK latch is much less used than the JK flip-flop. The JK latch follows the following state table:

JK latch truth table

J K Qnext Comment

0 0 Q No change

0 1 0 Reset

1 0 1 Set

1 1 Q Toggle

Hence, the JK latch is an SR latch that is made to toggle its output when passed the restricted combination of11. Unlike the JK Flip-Flop, in the JK latch, this is not a useful state because the speed of the toggling is not

directed by a clock.[17]

Gated latches and conditional transparency

Latches are designed to be transparent. That is, input signal changes cause immediate changes in output; whenseveral transparent latches follow each other, using the same clock signal, signals can propagate through all ofthem at once. Alternatively, additional logic can be added to a simple transparent latch to make itnon-transparent or opaque when another input (an "enable" input) is not asserted. By following atransparent-high latch with a transparent-low (or opaque-high) latch, a master–slave flip-flop is implemented.

Gated SR latch

A synchronous SR latch (sometimes clocked SR flip-flop)can be made by adding a second level of NAND gates to theinverted SR latch (or a second level of AND gates to thedirect SR latch). The extra gates further invert the inputs sothe simple SR latch becomes a gated SR latch (and a simpleSR latch would transform into a gated SR latch withinverted enable).

With E high (enable true), the signals can pass through theinput gates to the encapsulated latch; all signal combinationsexcept for (0,0) = hold then immediately reproduce on the(Q,Q) output, i.e. the latch is transparent.

With E low (enable false) the latch is closed (opaque) and remains in the state it was left the last time E washigh.

The enable input is sometimes a clock signal, but more often a read or write strobe.


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Symbol for a

gated SR latch

A D-type transparent latch based on an SR NAND

latch

A gated D latch based on an SR NOR latch

Symbol for a

gated D latch

Gated SR latch operationE/C Action

0 No action (keep state)

1 The same as non-clocked SR latch

Gated D latch

This latch exploits the fact that in the two active inputcombinations (01 and 10) of a gated SR latch R is thecomplement of S. The input NAND stage converts the twoD input states (0 and 1) to these two input combinations forthe next SR latch by inverting the data input signal. The lowstate of the enable signal produces the inactive "11"combination. Thus a gated D-latch may be considered as aone-input synchronous SR latch. This configurationprevents from applying the restricted combination to theinputs. It is also known as transparent latch, data latch, orsimply gated latch. It has a data input and an enable signal(sometimes named clock, or control). The word transparentcomes from the fact that, when the enable input is on, thesignal propagates directly through the circuit, from the inputD to the output Q.

Transparent latches are typically used as I/O ports or inasynchronous systems, or in synchronous two-phase systems(synchronous systems that use a two-phase clock), wheretwo latches operating on different clock phases prevent datatransparency as in a master–slave flip-flop.

Latches are available as integrated circuits, usually withmultiple latches per chip. For example, 74HC75 is a quadruple transparent latch in the 7400 series.

Gated D latch truth tableE/C D Q Q Comment

0 X Qprev Qprev No change

1 0 0 1 Reset

1 1 1 0 Set


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Earle latch uses complementary Enable inputs: Enable active

Low (E_L) and Enable active H (E_H)

D flip-flop

symbol

The truth table shows that when the enable/clock input is 0, the D input has no effect on the output. When E/Cis high, the output equals D.

Earle latch

The classic gated latch designs have some

undesirable characteristics.[18] They requiredouble-rail logic or an inverter. The input-to-outputpropagation may take up to three gate delays. Theinput-to-output propagation is not constant – someoutputs take two gate delays while others take three.

Designers looked for alternatives.[19] A successful

alternative is the Earle latch.[20] It requires only asingle data input, and its output takes a constant twogate delays. In addition, the two gate levels of theEarle latch can be merged with the last two gatelevels of the circuits driving the latch. Merging thelatch function can implement the latch with no

additional gate delays.[18]

The Earle latch is hazard free.[21] If the middle NAND gate is omitted, then one gets the polarity hold latch,

which is commonly used because it demands less logic.[22][21] Intentionally skewing the clock signal can avoid

the hazard.[22]

D flip-flop

The D flip-flop is the most common flip-flop in use today. It is better known as data ordelay flip-flop (as its output Q looks like a delay of input D).

The Q output takes on the state of the D input at the moment of a positive edge at the clock

pin (or negative edge if the clock input is active low).[23] It is called the D flip-flop for thisreason, since the output takes the value of the D input or data input, and delays it by oneclock cycle. The D flip-flop can be interpreted as a primitive memory cell, zero-order hold,or delay line. Whenever the clock pulses, the value of Qnext is D and Qprev otherwise.

Truth table:

Clock D Q Qprev

Rising edge 0 0 X

Rising edge 1 1 X

Non-Rising X Qprev

('X' denotes a Don't care condition, meaning the signal is irrelevant)

Most D-type flip-flops in ICs have the capability to be forced to the set or reset state (which ignores the D and


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4-bit serial-in, parallel-out (SIPO)

shift register

A positive-edge-triggered D flip-flop

clock inputs), much like an SR flip-flop. Usually, the illegal S = R = 1 condition is resolved in D-type flip-flops.By setting S = R = 0, the flip-flop can be used as described above.

Inputs Outputs

S R D > Q Q'

0 1 X X 0 1

1 0 X X 1 0

1 1 X X 1 1

These flip-flops are very useful, as they form the basis for shift registers,which are an essential part of many electronic devices. The advantage ofthe D flip-flop over the D-type "transparent latch" is that the signal onthe D input pin is captured the moment the flip-flop is clocked, andsubsequent changes on the D input will be ignored until the next clockevent. An exception is that some flip-flops have a "reset" signal input,which will reset Q (to zero), and may be either asynchronous orsynchronous with the clock.

The above circuit shifts the contents of the register to the right, one bit position on each active transition of theclock. The input X is shifted into the leftmost bit position.

Classical positive-edge-triggered D flip-flop

This clever circuit[24] consists of two stages implemented by SR NANDlatches. The input stage (the two latches on the left) processes the clockand data signals to ensure correct input signals for the output stage (thesingle latch on the right). If the clock is low, both the output signals ofthe input stage are high regardless of the data input; the output latch isunaffected and it stores the previous state. When the clock signalchanges from low to high, only one of the output voltages (depending onthe data signal) goes low and sets/resets the output latch: if D = 0, thelower output becomes low; if D = 1, the upper output becomes low. Ifthe clock signal continues staying high, the outputs keep their statesregardless of the data input and force the output latch to stay in thecorresponding state as the input logical zero remains active while theclock is high. Hence the role of the output latch is to store the data onlywhile the clock is low.

The circuit is closely related to the gated D latch as both the circuits convert the two D input states (0 and 1) totwo input combinations (01 and 10) for the output SR latch by inverting the data input signal (both the circuitssplit the single D signal in two complementary S and R signals). The difference is that in the gated D latch simpleNAND logical gates are used while in the positive-edge-triggered D flip-flop SR NAND latches are used for thispurpose. The role of these latches is to "lock" the active output producing low voltage (a logical zero); thus thepositive-edge-triggered D flip-flop can be thought of as a gated D latch with latched input gates.

Master–slave pulse-triggered D flip-flop


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A master–slave D flip-flop. It responds

on the negative edge of the enable

input (usually a clock)

An implementation of a master–slave

D flip-flop that is triggered on the

positive edge of the clock

A CMOS IC implementation of a True Single Phase

edge-triggered flip-flop with reset

A master–slave D flip-flop is created by connecting two gated D latches in series, and inverting the enable inputto one of them. It is called master–slave because the second latch in the series only changes in response to achange in the first (master) latch.

The term pulse-triggered means that data is entered on the rising edge of the clock pulse, but the output doesnot reflect the change until the falling edge of the clock pulse.

For a positive-edge triggered master–slave D flip-flop, when the clocksignal is low (logical 0) the "enable" seen by the first or "master" D latch(the inverted clock signal) is high (logical 1). This allows the "master"latch to store the input value when the clock signal transitions from lowto high. As the clock signal goes high (0 to 1) the inverted "enable" ofthe first latch goes low (1 to 0) and the value seen at the input to themaster latch is "locked". Nearly simultaneously, the twice inverted"enable" of the second or "slave" D latch transitions from low to high (0to 1) with the clock signal. This allows the signal captured at the risingedge of the clock by the now "locked" master latch to pass through the"slave" latch. When the clock signal returns to low (1 to 0), the output ofthe "slave" latch is "locked", and the value seen at the last rising edge ofthe clock is held while the "master" latch begins to accept new values inpreparation for the next rising clock edge.

By removing the leftmost inverter in the circuit at side, a D-type flip flopthat strobes on the falling edge of a clock signal can be obtained. Thishas a truth table like this:

D Q > Qnext

0 X Falling 0

1 X Falling 1

Edge-triggered dynamic D flip-flop

A more efficient way to make a D flip-flop is not so easy tounderstand, but it works the same way. While themaster–slave D flip-flop is also triggered on the edge of aclock, its components are each triggered by clock levels.The "edge-triggered D flip-flop" does not have themaster–slave properties.

Edge-triggered D flip-flops are often implemented inintegrated high-speed operations using dynamic logic. Thismeans that the digital output is stored on parasitic devicecapacitance while the device is not transitioning. This design of dynamic flip flops also enable simple resettingsince the reset operation can be performed by simply discharging one or more internal nodes. A commondynamic flip-flop variety is the True Single Phase Clock (TSPC) which performs the flip flop operation withlittle power and at high speeds. However these types of dynamic flip-flops will not work at static or low clockedspeeds, since given enough time the parasitic capacitance will discharge through leakage paths and will cause


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A circuit symbol

for a T-type

flip-flop

A circuit symbol

for a positive-

edge-triggered

JK flip-flop

the logic levels to enter invalid states.

T flip-flop

If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input isstrobed. If the T input is low, the flip-flop holds the previous value. This behavior isdescribed by the characteristic equation:

(expanding the XOR operator)

and can be described in a truth table:

T flip-flop operation[25]

Characteristic table Excitation table

T Q Qnext Comment Q Qnext T Comment

0 0 0 hold state (no clk) 0 0 0 No change

0 1 1 hold state (no clk) 1 1 0 No change

1 0 1 toggle 0 1 1 Complement

1 1 0 toggle 1 0 1 Complement

When T is held high, the toggle flip-flop divides the clock frequency by two; that is, if clock frequency is4 MHz, the output frequency obtained from the flip-flop will be 2 MHz. This "divide by" feature has applicationin various types of digital counters. A T flip-flop can also be built using a JK flip-flop (J & K pins are connectedtogether and act as T) or D flip-flop (T input and Qprevious is connected to the D input through an XOR gate). AT flip-flop can also be built using an edge-triggered D flip-flop with its D input fed from its own inverted output.

JK flip-flop

The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpretingthe S = R = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1,K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to resetthe flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e.,change its output to the logical complement of its current value. Setting J = K = 0 doesNOT result in a D flip-flop, but rather, will hold the current state. To synthesize a Dflip-flop, simply set K equal to the complement of J. The JK flip-flop is therefore auniversal flip-flop, because it can be configured to work as an SR flip-flop, a D flip-flop, ora T flip-flop.

NOTE: The flip-flop is positive-edge triggered (rising clock pulse) as seen in the timingdiagram.

The characteristic equation of the JK flip-flop is:

and the corresponding truth table is:


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JK flip-flop timing diagram

Flip-flop setup, hold and clock-

to-output timing parameters

JK Flip Flop operation[25]

Characteristic table Excitation table

J K Qnext Comment Q Qnext J K Comment

0 0 Q hold state 0 0 0 X No change

0 1 0 reset 0 1 1 X Set

1 0 1 set 1 0 X 1 Reset

1 1 Q toggle 1 1 X 0 No change

Metastability

Flip-flops are prone to a problem called metastability, which can happen when two inputs, such as data andclock or clock and reset, are changing at about the same time, such that the resulting state would depend on theorder of the input events. When the order is not clear, within appropriate timing constraints, the result is that theoutput may behave unpredictably, taking many times longer than normal to settle to one state or the other, oreven oscillating several times before settling. Theoretically, the time to settle down is not bounded. In acomputer system, this metastability can cause corruption of data or a program crash, if the state is not stablebefore another circuit uses its value; in particular, if two different logical paths use the output of a flip-flop, onepath can interpret it as a 0 and the other as a 1 when it has not resolved to stable state, putting the machine into

an inconsistent state.[26]

Timing considerations

Setup and hold times

Setup time is the minimum amount of time the data signal should beheld steady before the clock event so that the data are reliably sampledby the clock. This applies to synchronous circuits such as the flip-flop.

Hold time is the minimum amount of time the data signal should be heldsteady after the clock event so that the data are reliably sampled. Thisapplies to synchronous circuits such as the flip-flop.

To summarize: Setup time -> Clock flank -> Hold time.

The metastability in flip-flops can be avoided by ensuring that the dataand control inputs are held valid and constant for specified periodsbefore and after the clock pulse, called the setup time (tsu) and the holdtime (th) respectively. These times are specified in the data sheet for thedevice, and are typically between a few nanoseconds and a few hundredpicoseconds for modern devices.

Unfortunately, it is not always possible to meet the setup and hold criteria, because the flip-flop may beconnected to a real-time signal that could change at any time, outside the control of the designer. In this case,the best the designer can do is to reduce the probability of error to a certain level, depending on the required


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reliability of the circuit. One technique for suppressing metastability is to connect two or more flip-flops in achain, so that the output of each one feeds the data input of the next, and all devices share a common clock.With this method, the probability of a metastable event can be reduced to a negligible value, but never to zero.The probability of metastability gets closer and closer to zero as the number of flip-flops connected in series isincreased.

So-called metastable-hardened flip-flops are available, which work by reducing the setup and hold times asmuch as possible, but even these cannot eliminate the problem entirely. This is because metastability is morethan simply a matter of circuit design. When the transitions in the clock and the data are close together in time,the flip-flop is forced to decide which event happened first. However fast we make the device, there is alwaysthe possibility that the input events will be so close together that it cannot detect which one happened first. It istherefore logically impossible to build a perfectly metastable-proof flip-flop.

Propagation delay

Another important timing value for a flip-flop (F/F) is the clock-to-output delay (common symbol in data sheets:tCO) or propagation delay (tP), which is the time the flip-flop takes to change its output after the clock edge. Thetime for a high-to-low transition (tPHL) is sometimes different from the time for a low-to-high transition (tPLH).

When cascading F/Fs which share the same clock (as in a shift register), it is important to ensure that the tCO ofa preceding F/F is longer than the hold time (th) of the following flip-flop, so data present at the input of thesucceeding F/F is properly "shifted in" following the active edge of the clock. This relationship between tCO andth is normally guaranteed if the F/Fs are physically identical. Furthermore, for correct operation, it is easy toverify that the clock period has to be greater than the sum tsu + th.

Generalizations

Flip-flops can be generalized in at least two ways: by making them 1-of-N instead of 1-of-2, and by adaptingthem to logic with more than two states. In the special cases of 1-of-3 encoding, or multi-valued ternary logic,

these elements may be referred to as flip-flap-flops.[27]

In a conventional flip-flop, exactly one of the two complementary outputs is high. This can be generalized to amemory element with N outputs, exactly one of which is high (alternatively, where exactly one of N is low). Theoutput is therefore always a one-hot (respectively one-cold) representation. The construction is similar to a

conventional cross-coupled flip-flop; each output, when high, inhibits all the other outputs.[28] Alternatively,more or less conventional flip-flops can be used, one per output, with additional circuitry to make sure only one

at a time can be true.[29]

Another generalization of the conventional flip-flop is a memory element for multi-valued logic. In this case the

memory element retains exactly one of the logic states until the control inputs induce a change.[30] In addition, a

multiple-valued clock can also be used, leading to new possible clock transitions.[31]

See also

MultivibratorPositive feedbackDeadlockPulse transition detector


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References

^ a b Volnei A. Pedroni (2008). Digital electronicsand design with VHDL (http://books.google.com/books?id=-ZAccwyQeXMC&pg=PA329&dq=latches+flip-flops+transparent+clock&hl=en&ei=shr7TJ3EOJL2swPF-rj3DQ&sa=X&oi=book_result&ct=result&resnum=10&ved=0CGYQ6AEwCQ#v=onepage&q=latches%20flip-flops%20transparent%20clock&f=false) . Morgan Kaufmann. p. 329.ISBN 9780123742704. http://books.google.com/books?id=-ZAccwyQeXMC&pg=PA329&dq=latches+flip-flops+transparent+clock&hl=en&ei=shr7TJ3EOJL2swPF-rj3DQ&sa=X&oi=book_result&ct=result&resnum=10&ved=0CGYQ6AEwCQ#v=onepage&q=latches%20flip-flops%20transparent%20clock&f=false.

1.

^ a b Latches and Flip Flops(http://rfic.eecs.berkeley.edu/ee100/pdf/lect24.pdf)(EE 42/100 Lecture 24 from Berkeley) "...Sometimesthe terms flip-flop and latch are usedinterchangeably..."

2.

^ William Henry Eccles and Frank Wilfred Jordan,"Improvements in ionic relays(http://v3.espacenet.com/origdoc?DB=EPODOC&IDX=GB148582&F=0&QPN=GB148582) " Britishpatent number: GB 148582 (filed: 21 June 1918;published: 5 August 1920).

3.

^ W. H. Eccles and F. W. Jordan (19 September1919) "A trigger relay utilizing three-electrodethermionic vacuum tubes," The Electrician, vol. 83,page 298. Reprinted in: Radio Review, vol. 1, no. 3,pages 143–146 (December 1919).

4.

^ Emerson W. Pugh, Lyle R. Johnson, John H.Palmer (1991). IBM's 360 and early 370 systems(http://books.google.com/?id=MFGj_PT_clIC&pg=PA10&dq=eccles-jordan-trigger+vacuum&q=eccles-jordan-trigger%20vacuum) . MIT Press.p. 10. ISBN 9780262161237.http://books.google.com/?id=MFGj_PT_clIC&pg=PA10&dq=eccles-jordan-trigger+vacuum&q=eccles-jordan-trigger%20vacuum.

5.

^ Earl D. Gates (2000). Introduction to electronics(http://books.google.com/books?id=IwC5GIA0cREC&pg=PA299&dq=%22flip-flop%22+circuit+transistors+gates&hl=en&ei=YRP7TLqJDo-4sQP24OX2DQ&sa=X&oi=book_result&ct=result&resnum=6&ved=0CDwQ6AEwBQ#v=onepage&q=%22flip-flop%22%20circuit%20transistors%20gates&f=false) (4th ed.). Delmar Thomson (Cengage)Learning. p. 299. ISBN 9780766816985.

6.

http://books.google.com/books?id=IwC5GIA0cREC&pg=PA299&dq=%22flip-flop%22+circuit+transistors+gates&hl=en&ei=YRP7TLqJDo-4sQP24OX2DQ&sa=X&oi=book_result&ct=result&resnum=6&ved=0CDwQ6AEwBQ#v=onepage&q=%22flip-flop%22%20circuit%20transistors%20gates&f=false.^ Max Fogiel and You-Liang Gu (1998). TheElectronics problem solver, Volume 1(http://books.google.com/books?id=Zpwtq_SjKSoC&pg=PA1223&dq=%22flip-flop%22+circuit+transistors+gates&hl=en&ei=YRP7TLqJDo-4sQP24OX2DQ&sa=X&oi=book_result&ct=result&resnum=7&ved=0CEEQ6AEwBg#v=onepage&q=%22flip-flop%22%20circuit%20transistors%20gates&f=false) (revised ed.). Research & Education Assoc..p. 1223. ISBN 9780878915439.http://books.google.com/books?id=Zpwtq_SjKSoC&pg=PA1223&dq=%22flip-flop%22+circuit+transistors+gates&hl=en&ei=YRP7TLqJDo-4sQP24OX2DQ&sa=X&oi=book_result&ct=result&resnum=7&ved=0CEEQ6AEwBg#v=onepage&q=%22flip-flop%22%20circuit%20transistors%20gates&f=false.

7.

^ Wilfred Bennett Lewis (1942). Electrical counting:with special reference to counting alpha and betaparticles. CUP Archive. p. 68.

8.

^ The Electrician 128. Feb. 13, 1942.9.^ Owen Standige Puckle and E. B. Moullin (1943).Time bases (scanning generators): their design anddevelopment, with notes on the cathode ray tube.Chapman & Hall Ltd. p. 51.

10.

^ Britton Chance (1949). Waveforms (Vol. 19 ofMIT Radiation Lab Series ed.). McGraw-Hill BookCo. p. 167.

11.

^ O. S. Puckle (Jan. 1949). "Development of TimeBases: The Principles of Known Circuits". WirelessEngineer (Iliffe Electrical Publications) 26 (1): 139.

12.

^ P. L. Lindley, Aug. 1968, EDN (magazine), (letterdated June 13, 1968).

13.

^ Montgomery Phister (1958). Logical Design ofDigital Computers. (http://books.google.com/?id=Ri1IAAAAIAAJ&q=inauthor:phister+j-k-flip-flop&dq=inauthor:phister+j-k-flip-flop) . Wiley.p. 128. http://books.google.com/?id=Ri1IAAAAIAAJ&q=inauthor:phister+j-k-flip-flop&dq=inauthor:phister+j-k-flip-flop.

14.

^ Sajjan G. Shiva (2000). Computer design andarchitecture (http://books.google.com

15.


14 of 16 8/25/2011 4:25 PM

/books?id=kKQFttdG7hcC&pg=PA81&dq=%22delay-flip-flop%22+%22data-flip-flop%22&hl=en&ei=Yz37TO_PAoX6sAOPoan3DQ&sa=X&oi=book_result&ct=result&resnum=2&ved=0CCgQ6AEwAQ#v=onepage&q=%22delay-flip-flop%22%20%22data-flip-flop%22&f=false)(3rd ed.). CRC Press. p. 81. ISBN 9780824703684.http://books.google.com/books?id=kKQFttdG7hcC&pg=PA81&dq=%22delay-flip-flop%22+%22data-flip-flop%22&hl=en&ei=Yz37TO_PAoX6sAOPoan3DQ&sa=X&oi=book_result&ct=result&resnum=2&ved=0CCgQ6AEwAQ#v=onepage&q=%22delay-flip-flop%22%20%22data-flip-flop%22&f=false.^ Langholz, Gideon; Kandel, Abraham; Mott (1998),Foundations of Digital Logic Design(http://books.google.com/books?id=4sX9fTGRo7QC&pg=PA344&lpg=PA344&dq=sr+characteristic+latch+equation&source=web&ots=9WdHN5uzTF&sig=ewGWuNX8g_4KozJuL5VyAS2yErc#v=onepage&q=sr%20characteristic%20latch%20equation&f=false) , Singapore: World Scientific Publishing Co.Ptc. Ltd., p. 344, ISBN 978-981-02-3110-1,http://books.google.com/books?id=4sX9fTGRo7QC&pg=PA344&lpg=PA344&dq=sr+characteristic+latch+equation&source=web&ots=9WdHN5uzTF&sig=ewGWuNX8g_4KozJuL5VyAS2yErc#v=onepage&q=sr%20characteristic%20latch%20equation&f=false

16.

^ Hassan A. Farhat (2004). Digital design andcomputer organization, Volume 1(http://books.google.com/books?id=QypINJ4oRI8C&pg=PA274&dq=%22jk+latch%22+oscillate&hl=en&ei=ADb7TN7gMpLAsAOVzJD3DQ&sa=X&oi=book_result&ct=result&resnum=3&ved=0CC8Q6AEwAg#v=onepage&q&f=false) .CRC Press. p. 274. ISBN 9780849311918.http://books.google.com/books?id=QypINJ4oRI8C&pg=PA274&dq=%22jk+latch%22+oscillate&hl=en&ei=ADb7TN7gMpLAsAOVzJD3DQ&sa=X&oi=book_result&ct=result&resnum=3&ved=0CC8Q6AEwAg#v=onepage&q&f=false.

17.

^ a b Kogge, Peter M. (1981), The Architecture ofPipelined Computers, McGraw-Hill, pp. 25–27,ISBN 0-07-035237-2

18.

^ Cotten, L. W. (1965), "Circuit Implementation ofHigh-Speed Pipeline Systems", AFIPS Proc. FallJoint Computer Conference: 489–504

19.

^ Earle, J. (March, 1965), "Latched Carry-SaveAdder", IBM Technical Disclosure Bulletin 7 (10):909–910

20.

^ a b Omondi, Amos R. (1999), The21.

Microarchitecture of Pipelined and SuperscalarComputers (http://books.google.com/books?id=Pf2ZbKM2-5MC&pg=PA39&lpg=PA39&dq=%22earle+latch%22&source=bl&ots=oB2eLzJgiN&sig=HR7T142isxJ2cLIo9xH6zX9lwa8&hl=en&ei=BnMFTKKRN47ANYLitDs&sa=X&oi=book_result&ct=result&resnum=9&ved=0CDkQ6AEwCA#v=onepage&q=%22earle%20latch%22&f=false) , pp. 40–42,ISBN 978-0792384632, http://books.google.com/books?id=Pf2ZbKM2-5MC&pg=PA39&lpg=PA39&dq=%22earle+latch%22&source=bl&ots=oB2eLzJgiN&sig=HR7T142isxJ2cLIo9xH6zX9lwa8&hl=en&ei=BnMFTKKRN47ANYLitDs&sa=X&oi=book_result&ct=result&resnum=9&ved=0CDkQ6AEwCA#v=onepage&q=%22earle%20latch%22&f=false^ a b Kunkel, Steven R.; Smith, James E. (May1986), "Optimal Pipelining in Supercomputers"(http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.99.2773&rep=rep1&type=pdf) , ACM SIGARCH Computer ArchitectureNews (ACM) 14 (2): 404–411,doi:10.1145/17356.17403 (http://dx.doi.org/10.1145%2F17356.17403) , ISSN 0163-5964(http://www.worldcat.org/issn/0163-5964) ,http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.99.2773&rep=rep1&type=pdf

22.

^ The D Flip-Flop (http://www.play-hookey.com/digital/d_nand_flip-flop.html)

23.

^ SN7474 TI datasheet (http://focus.ti.com/lit/ds/symlink/sn7474.pdf)

24.

^ a b Mano, M. Morris; Kime, Charles R. (2004).Logic and Computer Design Fundamentals, 3rdEdition. Upper Saddle River, NJ, USA: PearsonEducation International. pp. pg283.ISBN 0-13-1911651.

25.

^ Thomas J. Chaney and Charles E. Molnar (April1973). "Anomalous Behavior of Synchronizer andArbiter Circuits" (http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1672323) . IEEETransactions on Computers C-22 (4): 421–422.doi:10.1109/T-C.1973.223730 (http://dx.doi.org/10.1109%2FT-C.1973.223730) . ISSN 0018-9340(http://www.worldcat.org/issn/0018-9340) .http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1672323.

26.

^ Often attributed to Don Knuth (1969) (see MidhatJ. Gazalé (2000). Number: from Ahmes to Cantor(http://books.google.com/?id=hARkwMkeliUC&pg=PA57&dq=flip-flap-flop+knuth&q=flip-flap-flop%20knuth) . Princeton University Press.p. 57. ISBN 9780691005157.

27.


15 of 16 8/25/2011 4:25 PM

http://books.google.com/?id=hARkwMkeliUC&pg=PA57&dq=flip-flap-flop+knuth&q=flip-flap-flop%20knuth.), the term flip-flap-flop actuallyappeared much earlier in the computing literature, forexample, Edward K. Bowdon (1960). The design andapplication of a "flip-flap-flop" using tunnel diodes(Master's thesis) (http://books.google.com/?id=0pA7AAAAMAAJ&q=flip-flap-flop+core&dq=flip-flap-flop+core) . University of North Dakota.http://books.google.com/?id=0pA7AAAAMAAJ&q=flip-flap-flop+core&dq=flip-flap-flop+core.^ "Ternary "flip-flap-flop""(http://www.goldenmuseum.com/1411FlipFlap_engl.html) .http://www.goldenmuseum.com

28.

/1411FlipFlap_engl.html.^ US 6975152 (http://v3.espacenet.com/textdoc?DB=EPODOC&IDX=US6975152)

29.

^ Irving, Thurman A. and Shiva, Sajjan G. andNagle, H. Troy (March 1976). "Flip-Flops forMultiple-Valued Logic". Computers, IEEETransactions on C-25 (3): 237–246.doi:10.1109/TC.1976.5009250 (http://dx.doi.org/10.1109%2FTC.1976.5009250) .

30.

^ Wu Haomin and Zhuang Nan (1991). "Researchinto ternary edge-triggered JKL flip-flop". Journal ofElectronics (China) 8 (Volume 8, Number 3 / July,1991): 268–275. doi:10.1007/BF02778378(http://dx.doi.org/10.1007%2FBF02778378) .

31.

Retrieved from "http://en.wikipedia.org/wiki/Flip-flop_(electronics)"Categories: Digital electronics | Electronic engineering | Digital systems | Logic gates | Computer memory

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