April 21, 2008

Presentationby

C.R ManojPhD Student, EE Dept, IIT Bombay

Device Design & Optimization of Device Design & Optimization of NanoscaleNanoscale FinFETsFinFETs using 3D TCAD simulationsusing 3D TCAD simulations

April 21, 2008

Outline

• TCAD Tuning for FinFETs• High-K FinFETs Simulations • Bulk FinFETs Optimisation study• Fin pitch and Parasitcs• FinFET vs Planar parasitics• Conclusions

April 21, 2008

TCAD Tuning for FinFETs

• FinFETs current flow plane different from conventional planar MOSFETs

• TCAD tool use default 100 plane mobility

• So tuning the mobilty to account for plane of conduction is essential for FinFETs.

• µ & ρ are tuned mainly to achieve matching

0.0 0.2 0.4 0.6 0.8 1.0

0.0

2.0x10-5

4.0x10-5

6.0x10-5

8.0x10-5

1.0x10-4

1.2x10-4

10-9

10-8

10-7

10-6

10-5

10-4

I D i

n lo

g sc

ale

(A/u

m)

I D in

line

ar sc

ale

(A/u

m)

VG (V)

default after tuning experimental

April 21, 2008

3D process structure & 2D cut plane

3D and 2D view of the process simulated FinFET structure

April 21, 2008

Circuit Simulations• LUT was generated for

the matched devices.• Sequel simulations done

for RO• Parasitic capacitance was

extracted from the layout, ploy resistance was estimated from the length of the poly and its doping level.

• Simulations matched close to expt result

April 21, 2008

High-K FinFET simulation Results

• K=3.9 (SiO2), 7.8 (Si3N4), 11.7 ( Al2O3), 15 (LaAlO3), 25 (HfO2) and 40 (TiO2 ) with EOT being 1.1 nm simulated

• SCE effects worsen due to Fringing Fields, (more noticeable for higher- K values)

• Needs Vt adjustment to make iso-Ioff comparison0 5 10 15 20 25 30 35 40 45

1.05

1.10

1.15

1.20

1.25

1.30

1.35

100

1000

10000

100

200

300

400

500

600

80

100

120

140

160

180

200

220

Ion

Ion

(mA

/um

) (l

inea

r sc

ale)

Dielectric Constant (K)

B

Ioff Io

ff (n

A/u

m)

(log

scal

e)

DIBL

DIB

L (m

V/V

)

Subthreshold Swing

Sub

Thr

esho

ldd

Swin

g (m

V/d

ecad

e)

April 21, 2008

• Fin doping, Fin width & work function adjusted to keep iso-Ioff

• Fin width scaling gives the optimum K for high –K circuit applications

• Work function range required may be large.

0 5 10 15 20 25 30 35 40 45

1x1018

2x1018

3x1018

4x1018

5x1018

6x1018

7x1018

2

4

6

8

10

124.5

4.6

4.7

4.8

4.9

5.0

5.1

5.2

4.0

4.1

4.2

4.3

4.4

4.5

4.6

4.7

Fin Doping

Fin

dopi

ng (

#/cm

3 )

Dielectric Constant (K)

Work function for P type

Fin Width F

in w

idth

(nm

)

Work Function for N type

Wor

k Fu

nctio

n, N

MO

S (V

)

Wor

k Fu

nctio

n, P

MO

S(V

)

High-K FinFET simulation Results

April 21, 2008

Impact of High- K on FinFET Circuit Performance

• Degradation in Noise Margins for Digital Applications

• Improved Speed compared to SiO2

• Optimum K is around 20-25, (Hafnium )

0 5 10 15 20 25 30 35 40 45

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.20.0 0.2 0.4 0.6 0.8 1.0 1.2

0.0

0.2

0.4

0.6

0.8

1.0

Inve

rter

Del

ay (p

s)

Dielectric Constant (K)

fin-doping fin-width work-function

Inverter Input Voltage (V)

Inve

rter

Out

put V

olta

ge (

V)

K=3.9 K=7.8 K=10 K=15 K=25 K=40

IEEE Electron Device Letters, April 2007

April 21, 2008

Bulk FinFETs

• They are very leaky without anti punch through (body doping)

• So body doping has been proposed as make it viable from leakage perspective

IEDM 2006

April 21, 2008

-0.04 0.00 0.04 0.08

1E17

1E18

1E19

Lower FinDeep Bulk Upper Fin

Dop

ing

#/c

m3

Depth (um)

(ii) (i) (iii)

Body doping profiles

Optimized doping profile can give better Ioff in Bulk FinFETs

April 21, 2008

• Reported profiles show heavy leakage current due to BTBT

• Profile (ii) and (iii) gives much better DC performance

0.0 0.2 0.4 0.6 0.8 1.010-8

10-7

10-6

1x10-5

1x10-4

1.0x10-4

2.0x10-4

3.0x10-4

4.0x10-4

5.0x10-4

6.0x10-4

7.0x10-4

I d-Vg ,

log

( A/u

m)

Vg (V)

profile (i) profile (ii) profile (iii)

Lg=65nm Wfin=22nm Hfin=60nm

Id-V

g , l

in (A

/um

)

Body doping profiles

April 21, 2008

1E16 1E17 1E18 1E1940

45

50

55

60

65

70

75

80

45

60

75

90

105

120

135

150

DIB

L (m

V/V)

Doping ( # /cm3)

DIBL

Sub

thre

shol

d Sw

ing

,SS

(mV/

deca

de)

SS

1E16 1E17 1E18 1E19

6.0x10-4

7.0x10-4

Ion

Ion

(A/u

m)

Doping (#/cm3)

1E-7

1E-6 Ioff

Ioff

(A/u

m)

Optimum body doping

Higher anti punch through (APT) doping always not beneficial. There exists an optimum APT doping owing to BTBT

April 21, 2008

FinFET’s Transient Performance

50 100 150 200-0.4-0.20.00.20.40.60.81.01.21.4

Volta

ge (v

olts

)

Time (ps)

SOI Input Bulk

Bulk FinFETs have same performance as SOI FinFETunlike planar counter parts. Verified by layout rule based

calculations.

IEEE Trans. on Electron Devices2008 FEB

April 21, 2008

FinFET’s Transeint Performance

10 20 30 40 50 604

8

12

16

20

24

28

4

8

12

Abs

olut

e de

lay

(ps)

Fin height (nm)

SOI Bulk

Lg=32nm Wfin=11nm

% delay difference

% d

elay

diff

eren

ce o

f SO

I & B

ulk

FinF

ET

Performance advantage significant for taller fins, owing to lesser junction capacitance.

April 21, 2008

0 20 40 60 80 100 120 140 16020.0a

30.0a

40.0a

50.0a

60.0a

70.0a

80.0a

24.0a

26.0a

28.0a

30.0a

32.0a

34.0a

36.0a

Cif with dopingCif without doping

Cof + Cpar with dopingCof +Cpar without doping

Cif (

F)

Cof

+ C

par (F

)

Insulator Thickness, Tins (nm)

white symbols --with dopingdark symbols --without body doping

Lg=32nm Wfin=11nm Hfin=60nm Lsp=16nm

Impact of STI height

April 21, 2008

Impact of STI height

-0.2 -0.1 0.0 0.1 0.20.0

2.0x104

4.0x104

6.0x104

8.0x104

1.0x105

E at

the

cent

er o

f the

fin

(Vol

ts/m

)

height (nm)

nd150 nd2 nd50 nd100

0 20 40 60 80 100 120 140 160

100

200

300

400

500

600

700

800

Lg=32nm Wfin=11nm

Ioff

(nA

/um

)

Isolation Oxide Height ,Tins (nm)

Without body doping With body doping

April 21, 2008

Parasitics Modeling

sin

21 2

1

2 [ 2 ];

2ln(1 )[2 ]

2 ln(1 )[2 ]2

4ln(1 )[ 2 2 ]

ln( )[ 2 ]; ,2 2

ox sdpp f ox g sd

extsp g

ff f foxfox

if f fox

sp gpf f ox g

extg extext

bf ox f

HC P W T T HL

TC H W

TT

C H WT

LC P W T T

LL LLdC P T W d d

d

β

ε

επεβεπ

εθ

= − − >

= + +

= + +

= + − − −

+= − − = =

Simulation =8.151e-17

Modeling=8.8e-17

For P=200nm

April 21, 2008

Fin Pitch Parasitics

Cbf

Cpp

Cpf

Cff

Lg

Tg

GATE

Source/Drain

HSD

BOX

P

April 21, 2008

Impact of Pitch

6.0e−17

7.0e−17

8.0e−17

9.0e−17

100 120 140 160 180 200 220 240 260

8.5

9

9.5

Ga

te C

ap

acita

nce

: C

gg

(F

)

Inve

rte

r d

ela

y:

(ps)

CggDelay

Pitch : P (nm)

2 [ ]2

4 [ln(1 )]2

2 [ln(1 )]2

para fringe pp

gox g

gox

extn

gox

extn

C C CP P P

LT

Lext

LL

TL

δ δ δδ δ δε

επ

επ

= +

+=

+

+

+

+Slope =0.2124fF/um

Model=0.275 fF/um

April 21, 2008

Patterned gate

8.4e+01

8.8e+01

9.2e+01

9.6e+01

20 25 30 35 40 45 50 55 60 65 70

Fre

qu

en

cy:

f (G

Hz)

Gate Thickness: Tg (nm)

fmax

April 21, 2008

Bulk FinFET Process Flow ..

April 21, 2008

Epi thickness vs Delay

FinFETs fringe parasitics (Cfr) almost 100% more than equivalent planar devices!. But junction capacitance is lesser than planar device.

April 21, 2008

Additional Parasitics in 3D

• Extra increase in Cfr is clear from the 3D picture.

• Cof1 & Cof3 are extra in FinFETs.

• In planar these additional components will get normalized by Weff. (effective width). But in FinFET they simply gets added to the total Cfr.

April 21, 2008

Delay/ Fringe Comparison

• Current ITRS picth(110nm ) over estimates the dealy.

• Aggressive fin pitch reduction essential for making FinFETsperformance competent.

1fin with 110nm pitch gives poor performance than planar. 2fin with 70 nm pitch makes it superior.

April 21, 2008

Impact of Cfr- Comparison FinFET/Planar (22nm node)

• Enhanced Cfr will cause the performance of FinFETs to be inferior to eqvt planar device (22nm node).

• More serious issue for large fanout circuits

April 21, 2008

Comparison with planar

FinFET Planar

April 21, 2008

Solutions -Spacer Fins

Packing two or more fins in a single pitch will reduce the total parasitics

April 21, 2008

• Bottom fins are difficult to be doped as uniform as the top fin.

• Insufficient doping increases ON resistance• SIMS may fail in thin fins• We need a easier method to profile the

doping value at the fin bottom

Electrical Method for Bottom Fin Doping Extraction

April 21, 200829

0.0 0.2 0.4 0.6 0.8 1.0 1.210-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

0.00000

0.00005

0.00010

0.00015

0.00020

0.000250.0 0.2 0.4 0.6 0.8 1.0 1.2

10-11

10-10

10-9

10-8

10-7

10-6

10-5

0.000000

0.000002

0.000004

0.0 0.2 0.4 0.6 0.8 1.0 1.210-1210-1110-1010-910-810-710-610-510-410-3

0.000000.000020.000040.000060.000080.000100.000120.000140.000160.00018

0.0 0.2 0.4 0.6 0.8 1.0 1.210-11

10-10

10-9

10-8

10-7

10-6

10-5

0.000000

0.000001

0.000002

0.000003

0.000004

0.000005

0.000006

X Axis Title

Tilt 10 Tilt 45

LG = 10um

LG = 110nm

VBG=-40 to 40V

Vd = 50mV

VBG=-40 to 40V VBG=-40 to 40V

VBG=-40 to 40V

Electrical Method for Bottom Fin Doping Extraction

FinFETs Id-Vg with substrate voltage varied from -40 to +40V

April 21, 200830

Conceptual Model: NMOS

N+ extensionhigh dose at the

top

• A positive (negative) bias on the back gate causes accumulation (depletion) of electrons at the extension – BOX interface• The channel is fully under gate control when the fins are narrow enough

Vback = 0 Vback +ve

April 21, 2008

Verification by 3D simulations

Depletion in bottom fin changes resistance and thus Ion (but not Ioff as channel not affected).

April 21, 2008

Extension Doping Implants

D03 5keV , 10o

D05 5keV , 45o

D08 5keV , 45o, , HDD ti

D09 1.5keV , 0o

D03 1.6keV , 10o

-40 -20 0 20 40200

300

400

500

600

700

800

900

Rto

tal (

ohm

s)

Vback-gate (V)

5keV, extn ti 10 5keV, extn ti 45 5keV, extn ti 45, HDD ti 45 1.5keV, extn ti 0 1.6keV, extn ti 10

Rsd sensitivity for different wafer lots with different energy and tilt

April 21, 200833

First Order Model

finfin

spextext Wh

LR

ρ=

finDfin

spextext Whh

LR

)( −=

ρ

silicide silicide

Extension with a negative bias on the back gate

Extension with a positive bias on the back gate

hFIN

hD

extR

extρ

spL

- Extension resistance

- Spacer length

- Average resistivity of the extension.- It is assumed that the current flows through the entire extension in the absence of depletion- Also that the average resistivity does not change with hD

April 21, 200834

First Order Model

finfin

ccont Wh

R ρ=

finDfin

ccont Whh

R)( −

=ρ

silicide silicide

Extension with a negative bias on the back gate

Extension with a positive bias on the back gate

hFIN

hD

contR

cρ

- contact resistance

- Average resistivity of the contacts.- It is assumed that the fin is fully silicided (for simplicity)- Also that the contact resistivity does not change along the fin height

April 21, 200835

First Order Model

finfin

cspexttot Wh

LR

)(2min

ρρ +=−

)(2 contexttot RRR +=

finsubDfin

cspextsubtot WVhh

LVR

))(()(2

)(−

+=

ρρ

fin

subD

subtot

tothVh

VRR )(1

)(min −=−

The highest value of resistance is reached when hD is the maximum => maximum “equivalent” depletion width at the bottom interface

hD-max can then be used to calculate an “equivalent average” doping at the bottom part of the fin

April 21, 2008

Doping extraction

Extracted doping exactly matched with the actual profiles in the fin bottom.

IEDM 2008 Submitted

3rd-APS-Manoj, march 17, 2008

Conclusions

• Proper TCAD tuning essential for meaningful FinFET simulations

• Optimum High-K dielctric for FinFETs propsed, from the performance perspective.

• Bulk FinFETs are optimized for better DC performance.• Reported that Bulk FinFETs are equally attractive from the

performance perspective unlike the conventional perception..

• Compared the FinFET fringe parasitics with equivalent planar and propose solutions to optimise the enhanced FinFET fringe parasitics.

• Proposed a novel approach for extracting the bottom fin doping in ultra thin fins.

3rd-APS-Manoj, march 17, 2008

Publications• C.R.Manoj, V. Ramgopal Rao, “Impact of High K Gate Dielectrics on the Device and Circuit

Performance of Nanoscale FinFETs”, IEEE Electron Device Letters, Vol. 28, Issue: 4, p.295, April 2007.

• C.R.Manoj, et al, “Device Design & Optimization Considerations for Bulk FinFETs”, IEEE Transactions on Electron Devices, Vol. 55, No.2, p. 609-615, February 2008

• A. B. Sachid, C.R. Manoj., Dinesh K. Sharma, V. Ramgopal Rao, “Gate Fringe Induced Barrier Lowering in Underlap FinFET Structures and its Optimization”, IEEE Electron Device Letters, Vol. 29, Issue 1, pp.128-130, January 2008.

• Yusuke K., C. R. Manoj, Kazuo Tsutsui, Venkanarayan Hariharan, Kuniyuki Kakushima, V. Ramgopal Rao, Parhat Ahmet, and Hiroshi Iwai, “Parasitic effects in multi-gate MOSFETs”, IEICE Transactions on Electronics (Japan), Vol. E90-C, No.10, October 2007.

• C.R. Manoj, V.Ramgopal Rao, Chang Yun Chang and Clement-Wann, “Enahnced Fringe Capacitance Parasitcs in 22nm Bulk FinFETs and its Optimisation”, To be submitted to IEEE TED 2008.

• C.R. Manoj, Meenakshi. N, Dhanya V. and V.Ramgopal Rao, “Optimization of Nano-scale Bulk FinFETs”, Proceedings of the 14 th International Workshop on the Physics of Semiconductor Devices, Mumbai, December 16-20, 2007

• C.R Manoj, N. Meenekshi, V.Ramgopal Rao, “Optimum Body Doping for Improving the Bulk FinFETs Performance”, Proceedings of the 14th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 11-13 July 2007, Bangalore, India

• Manoj C.R, Abhinav Mangal, V.Ramgopal Rao, Hiroshi Iwai,”Parasitic Effects in Multi-gate MOSFETs”, International Workshop on Nano CMOS, Jan 30- Feb 1, 2006, Mishima, Shizuoka prefecture, Japan (Invited)

• `