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Physical Design and FinFETs. Rob Aitken ARM R&D San Jose, CA (with help from Greg Yeric, Brian Cline, Saurabh Sinha, Lucian Shifren, Imran Iqbal, Vikas Chandra and Dave Pietromonaco). What’s Ahead?. The Scaling Wall?. EUV around the corner?. Slope of multiple patterning. - PowerPoint PPT Presentation
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Physical Design and FinFETsRob AitkenARM R&DSan Jose, CA(with help from Greg Yeric, Brian Cline, Saurabh Sinha, Lucian Shifren, Imran Iqbal, Vikas Chandra andDave Pietromonaco)##
Whats Ahead?EUV around the corner?Scaling getting roughThe Scaling Wall?Slope of multiplepatterningTrade off area, speed, power, and (increasingly) costAvalanches from resistance,variability, reliability, yield, etc.Crevasses of Doom#20nm: End of the Line for BulkBarring something close to a miracle, 20nm will be the last bulk nodeConventional MOSFET limits have been reachedToo much leakage for too little performance gainBulk replacement candidatesShort term:FinFET/Tri-gate/Multi-gate, or FDSOI (maybe)Longer term (below 10nm):III-V devices, GAA, nanowires, etc.
I come to fully deplete bulk, not to praise it#A Digression on Node NamesProcess names once referred to half metal pitch and/or gate lengthDrawn gate length matched the node namePhysical gate length shrunk fasterThen it stopped shrinkingObservation: There is nothing in a 20nm process that measures 20nm
Node1X Metal PitchIntel 32nm112.5nmFoundry 28nm90nmIntel 22nm80nmFoundry 20-14nm64nmSources: IEDM, EE Times
Source: ASML keynote, IEDM 12#40nm Past Its Prime?
28!20?16??Source: TSMC financial reports#Technology Scaling Trends19801990200020101970ComplexityTransistorsPatterningInterconnectAl wiresNMOS2020Planar CMOSHKMGStrainCU wiresPMOSLE, ~lLE,