computer architecture and organization 110215201832 Phpapp01 120221041908 Phpapp02

7/25/2019 computer architecture and organization 110215201832 Phpapp01 120221041908 Phpapp02

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COMPUTER

ORGANIZATIONANDARCHITECTURE

BadrinathM. Kadam

Department of Computer Science,

Yogeshwari Colloge, Ambajogai.


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What is Computer Organization

a very wide semantic gap between the intended behavior andthe worings of the underlying electronic devices that will

actually do all the wor.

!he forerunners to modern computers attempted to assemblethe raw devices "mechanical, electrical, or electronic# into aseparate purpose$built machine for each desired behavior.

Electronic

Devices

Desired

Behavior

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Ro!e o" Genera! PurposeComputers

A general purpose computer is lie an island that

helps span the gap between the desired behavior"application# and the basic building blocs "electronicdevices#.

Electronic

Devices

Desired

Behavior

General

Purpose

Computer

computer

organization software



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Computer Ar#hite#ture $De%nition

Computer Architecture % &SA ' ()

&nstruction Set Architecture What the e*ecutable can +see as underlying

hardware -ogical iew

(achine )rgani/ation Ho& the hardware implements &SA 0 1hysical iew



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Impa#t o" #hanging I'A

2arly 3445s Apple switched instructionset architecture of the (acintosh

6rom (otorola 78555$based machines

!o 1ower1C architecture

&ntel 85*87 6amily9 manyimplementations of same architecture

program written in 34:8 for 8587 can be runon latest 1entium chip



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(a#tors a)e#ting I'A

Computer

Ar#hite#ture

Te#hno!og* Programming+anguages

Operating'*stems

Histor*

App!i#ations



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I'A, Criti#a! Inter"a#e

instru#tion set

so"t&are

har-&are

2*amples9 85*87 ;5,555,555 vs. (&1S ;;55,555 000

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Designing Computers

All computers more or less based onthe same basic design, the on


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!he on "Arithmetic?-ogic >nit#

Control >nit

&nput ? )utput System "&?)#

@# 1rogram is stored in memory during

e*ecution.http://www.badrinathkadam.


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!he on


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Simplied Architecture

Source: Wikipedia

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(emory Subsystem

(emory, also called A( "andomAccess (emory#, Consists of many memory cells "storage units#

of a *ed si/e.

2ach cell has an address associated with it9 5, 3,

All accesses to memory are to a speciedaddress.A cell is the minimum unit of access "fetch?store

a complete cell#.!he time it taes to fetch?store a cell is the

same for all cells.

Ehen the computer is running, both

1rogramhttp://www.badrinathkadam.


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3F

A(


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(emory Si/e ? Speed

!ypical memory in a personal computer"1C#9 7F(H $ @;7(H

(emory si/es9 Iilobyte "IH# % @35 % 3,5@F

bytes J 3 thousand (egabyte"(H# % @@5% 3,5F8,;:7

bytes J 3 million

Kigabyte "KH# % @5

% 3,5:,:F3,8@Fbytes J 3 billion

(emory Access !ime "read from? write tomemory# ;5$:; nanoseconds "3 nsec. % 5.555555553

sec.#http://www.badrinathkadam.


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)perations on (emory

6etch "address#9 6etch a copy of the content of memory cell with the

specied address.


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Structure of the (emory

Subsystem 6etch"address# -oad address into (A.

Decode the address in

(A. Copy the content of

memory cell with speciedaddress into (D.

Store"address, value# -oad the address into (A. -oad the value into (D.

Decode the address in (A

Copy the content of (Dinto memory cell with thehttp://www.badrinathkadam


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&nput ? )utput Subsystem

Gandles devices that allow thecomputer system to9 Communicate and interact with the

outside world Screen, eyboard, printer, ... Store information "mass$storage#

Gard$drives, Loppies, CD, tapes,

(ass$Storage Device Access(ethods9 Direct Access Storage Devices "DASDs#

Gard$drives, Loppy$diss, CD$)(s, ...

SeBuential Access Storage Deviceshttp://www.badrinathkadam.


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&?) Controllers

Speed of &?) devices is slowcompared to A( A( J ;5 nsec. Gard$Drive J 35msec. % "35,555,555

nsec# Solution9

&?) Controller, a special purposeprocessor9

Gas a small memory buMer, and a controllogic to control &?) device "e.g. move disarm#.

Sends an interrupt signal to C1> when doneread?write.

Data transferred between A( andhttp://www.badrinathkadam.


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Structure of the &?)Subsystem



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!he A-> Subsystem

!he A-> "Arithmetic?-ogic >nit#performs mathematical operations "', $, *, ?, #

logic operations "%, N, O, and, or, not, ...# &n todayPs computers integrated into

the C1>

Consists of9 Circuits to do the arithmetic?logic

operations.

egisters "fast storage units# to store

intermediate computational results.http://www.badrinathkadam.c


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Structure of the A->

egisters9 ery fast local memory cells,

that store operands ofoperations and intermediateresults.

CC "condition coderegister#, a special purposeregister that stores theresult of N, % , O operations

A-> circuitry9 Contains an array of circuitsto do mathematical?logicoperations.

Hus9

Data path interconnectinghttp://www.badrinathkadam.com


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!he Control >nit

1rogram is stored in memory as machine language instructions, in

binary

!he tas of the control unit is toe*ecute programs by repeatedly9 6etch from memory the ne*t instruction

to be e*ecuted.

Decode it, that is, determine what is tobe done.

2*ecute it by issuing the appropriate

signals to the A->, memory, and &?)subsystems.http://www.badrinathkadam


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(achine -anguage&nstructions

A machine language instructionconsists of9 )peration code, telling which

operation to perform Address eld"s#, telling the memoryaddresses of the values on which theoperation wors.

2*ample9 ADD Q, Y "Add content ofmemory locations Q and Y, and store bac inmemory location Y#.

Assume9 opcode for ADD is 4, and addressesQ%44, Y%355

,,,,,, ,,,,,,,,,,,, ,,,,,,,,,,,,,

Opcode (1 $its) Address (2 $its) Address . (2 $its)



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&nstruction Set Design

!wo diMerent approaches9 educed &nstruction Set Computers

"&SC# &nstruction set as small and simple as

possible.

(inimi/es amount of circuitry $$O fastercomputers

Comple* &nstruction Set Computers"C&SC# (ore instructions, many very comple*

2ach instruction can do more wor, buthttp://www.badrinathkadam.


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!ypical (achine &nstructions


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(achine &nstructions "cont.#

Arithmetic ADD Q, Y, RC)


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(achine &nstructions "cont.#

HranchT>(1 Q -oad ne*t instruction from memory

loc. Q

T>(1K! Q -oad ne*t instruction from memoryloc. Q only if K! Lag in CC isset, otherwise load statementfrom ne*t seBuence loc. as

usual.

T>(12, T>(1-!, T>(1K2, T>(1-2,T>(1


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2*ample

1seudo$code9 Set A to H ' C Assuming variable9

A stored in memory cell 355, H stored

in memory cell 3;5, C stored inmemory cell 3;3

(achine language "really in binary#

-)AD 3;5 ADD 3;3

S!)2 355

or

"ADD 3;5, 3;3, 355#http://www.badrinathkadam


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Structure of the Control >nit 1C "1rogram Counter#9

stores the address of ne*t instruction tofetch

& "&nstruction egister#9

stores the instruction fetched from memory

&nstruction Decoder9 Decodes instruction and activates necessary

circuitry

Instruction

Decoder

IR

+1

PC



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von Neumann

Architecture

von Neumann

Architecture


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Gow does this all wortogether0

1rogram 2*ecution9 1C is set to the address where the

rst program instruction is stored inmemory.

epeat until GA-! instruction or fatalerror

6etch instruction

Decode instruction

2*ecute instruction

2nd of loohttp://www.badrinathkadam.


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1rogram 2*ecution "cont.#

6etch phase 1C $$O (A "put address in 1C into

(A#

6etch signal "signal memory to fetchvalue into (D#

(D $$O &"move value to &nstructionegister#

1C ' 3 $$O 1C "&ncrease address inprogram counter#

Decode 1hase & $O &nstruction decoder "decode

instruction in http://www.badrinathkadam.


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1rogram 2*ecution "cont.#

2*ecute 1hase DiMers from one instruction to the ne*t.

2*ample9 -)AD Q "load value in addr. Q intoregister# &Uaddress $O (A

6etch signal (D $$O

ADD Q left as an e*ercise

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&nstruction Set for )ur on in -e#ima! notation> #ontent o" mem;!o#; /

3333 HA+T 'top program e:e#ution



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(un-amenta! Components o"Computer

!he C1> "A->, Control >nit, egisters# !he (emory Subsystem "Stored Data# !he &?) subsystem "&?) devices#

&?) DeviceSubsystem

Address Hus

Data Hus

Control Hus

C1>(emorySubsystem



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Ea#h o" these Components are#onne#te- through 5uses;

H>S $ 1hysically a set of wires. !hecomponents of the Computer areconnected to these buses.

Address Hus Data Hus Control Hus



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A--ress 5us

>sed to specify the address of thememory location to access.

2ach &?) devices has a uniBue address.

"monitor, mouse, cd$rom# C1> reads data or instructions from other

locations by specifying the address of itslocation.

C1> always outputs to the address busand never reads from it.



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Data 5us

Actual data is transferred via the databus.

Ehen the cpu sends an address tomemory, the memory will send data viathe data bus in return to the cpu.



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Contro! 5us

Collection of individual control signals. Ehether the cpu will read or write data.

C1> is accessing memory or an &?)device

(emory or &?) is ready to transfer data



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I


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5us Organisation

Processor

Control

Datapath

Memory Devices

Input

Output

Cache

Registers

Bus



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(un-amenta! Con#epts

1rocessor "C1>#9 the active part of thecomputer, which does all the wor"data manipulation and decision$maing#.

Datapath9 portion of the processorwhich contains hardware necessary toperform all operations reBuired by the

computer "the brawn#. Control9 portion of the processor "also

in hardware# which tells the datapathwhat needs to be done "the brain#.



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(un-amenta! Con#epts 0?1

&nstructione*ecution cycle9fetch, decode,e*ecute.

6etch9 fetch ne*tinstruction "using 1C#from memory into &.

Decode9 decode theinstruction.

2*ecute9 e*ecuteinstruction.

InstructionFetch

Instruction

Decode

OperandFetch

Execute

ResultStore

ext

Instruction



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(un-amenta! Con#epts 0@1

6etch9 6etch ne*t instruction into &"&nstruction egister#. Assume each word is F bytes and each

instruction is stored in a word, and that the

memory is byte addressable. 1C "1rogram Counter# contains address ofne*t instruction.

& WW1CXX

1C W1CX ' F



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'ing!e 5us Organization

Data line

Address line

PC

MAR

MDR

Y

Internal

processor bus

M!"

A

A#!

B

Constant $

%elect

Add%ub

"&R

'

A#!controllines Carr()in

IR

R&

R*n+,

''

-EMP

Instruction

decoder and

control lo.ic

/ / /

Control si.nals



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Instru#tion C*#!es

1rocedure the C1> goes through toprocess an instruction.

3. 6etch $ get instruction

@. Decode $ interperate the instruction . 2*ecute $ run the instruction.



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Timing Diagram,Memor* Rea-

Address is placed at beginning of cloc after one cloc cycle the C1> asserts the read. Causes the memory to place its data onto the data bus.

C-I 9 System Cloc used to synchroni/e

C-I

AddressHus

Hus

ead

Data



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Timing Diagram ,Memor* Write

C1> places the Address and data on the rst cloc cycle. At the start of the second cloc the C1> will assert the

write control signal. !his will then start memory to store data.

After some time the write is then deasserted by the C1>after removing the address and data from the subsystem.

C-I

AddressAddress Hus

Data Hus

ead

Data



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I


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Te#hno!og* Tren-s

Pro#essor

logic capacity9 about 5 per year

cloc rate9 about @5 per year Memor*

DA( capacity9 about 75 per year "F* every years#

(emory speed9 about 35 per year

Cost per bit9 improves about @; per year Dis

capacity9 about 75 per year !otal use of data9 355 per 4 months=

Net&or 5an-&i-th

Handwidth increasing more than 355 per year=



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0 In B3 the sing!e$#hip pro#essor 0@?$Fit1 an- the sing!e$Foar- #omputer emerge-

0 In the ?..?4 time"rame> these ma* &e!! !oo !iemain"rames #ompare- sing!e$#hip #omputer 0ma*Fe ?

#hips1

DRAMear 'ize3. JF3@ ? JF

3 3 MF3 MF3? 3 MF3 MF3 ? MF?..? 3 GF

(icroprocessor -ogic Density

DRAM #hip #apa#it*

Te#hno!og* Tren-s



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Te#hno!og* Tren-s

'ma!!er "eature sizes K higher spee-> -ensit*



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Te#hno!og* Tren-s

NumFer o" transistors -ouF!es e=er* 3months

0amen-e- to ? months1



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Re"eren#es

Computer )rgani/ation and Architecture,Designing for performance by WilliamStallin!s" 1rentice Gall of &ndia.

(odern Computer Architecture, by #orris

#ano" 1rentice Gall of &ndia. Computer Architecture and )rgani/ation

by$ohn %. &a'es" (cKraw Gill 1ublishingCompany.

Computer )rgani/ation by (. )arl&amacher" *+onko ,. (ranesic" Sa-wat ,.*ak'" (cKraw Gill 1ublishing Company.



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Than ou

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computer architecture and organization 110215201832 Phpapp01 120221041908 Phpapp02