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Efficient design implementation of any ASIC requires an appropriate style which meet the design goals Area Power Speed Multi-dimensional Trade off
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ASEMINAR ON
LOW POWER AND AREA EFFICIENT CARRY SELECT ADDER
BY
Jayaprakash Nagaruru
Tuesday, March 19, 2013 2Low Power & Area Efficient CSLA
ObjectiveTo design a Carry Select Adder(CSLA) with a optimum utilization of area and power
Low Power & Area Efficient CSLA 3
Agenda• Introduction • Carry Select Adder• Delay and Area Evaluation • Principle Behind Modification• Modified CSLA• Delay and Area Evaluation• Implementation Results• Conclusion
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Introduction
• Efficient design implementation of any ASIC requires an appropriate style which meet the design goals
Area Power Speed
• Multi-dimensional Trade off
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Carry Select Adder
• Ripple carry adder & MUX
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Regular CSLA
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Delay and Power Evaluation
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Contd…
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Regular CSLA
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Principle Behind Modification• Binary to Excess-1 Convertor
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CSLA with BEC
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Modified CSLA
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Delay and Power Evaluation of modified CSLA
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Comparison
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Implementation Results
• Typical ASIC flow Using 0.18u Technology for regular and modified CSLA
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Graphical Analysis
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Conclusion
• Despite with a little delay overhead a optimized carry select adder has been designed
No. of
Bits
Area Reduction
(%)8 9.7
16 1532 16.764 17.4
Power Reduction
(%)7.6
10.5613.6315.46
Delay Overhead
(%)149.86.7
3.76
Power Delay
Product(%)5.2
1.768.18
12.28
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Area Delay Product(%)
2.96.711
14.4
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References
Bibliography • IEEE 2012 paper on Low Power
& Area Efficient CSLA by B Ram Kumar & H M Kittur
• J M Rabaey Digital Integrated Circuits
• IJCE 2012 paper on VLSI Realization Of Fast Carry Adder in Binary Excess by Santhosh Kannan and Bhanumathi
Webography • http://en.wikipedia.org/wiki/C
arry-select_adder
• http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5407919&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D5407919
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Presented by
Jayaprakas
hTuesday, March 19, 2013
