Computer Architechture & Organization Ch-1

7/31/2019 Computer Architechture & Organization Ch-1

1/72


2/72

Architecture the building blocks

Structure -static arrangement of the parts (plan)

Organization - dynamic interaction of these parts and

their management (design) Implementation - the design of specific building blocks

(construction)

Performance evaluation - the behavior study of the

system (decorative treatment)


3/72

Wolf Radius Bone

Wolf radius bone ca. 25,00030,000 B.C. showing 55 cuts in groups offive, suggesting a rudimentary form of multiplication or division.

(Source: Illustrated London News, October 2, 1937.)


4/72

Tally Sticks

Original wooden tally

sticks from Westminster,

England, ca. 12501275

A.D.

( SSPL/The ImageWorks.)


5/72


6/72

Cylinder Music Box

Victorian Swiss cylinder music box, dated 1862.

(Source: http://www.liveauctioneers.com/auctions/ebay/497199.html.)


7/72

Pascals Calculating Machine Performs basic arithmetic operations (early to mid 1600s). Does not

have what may be considered the basic parts of a computer.

(Source: IBM

Archives

photograph.)


8/72


9/72

The Jacquard Pattern Weaving Loom

The Jacquard patternweaving loom (ca.

1804).

(Source: The Deutsche Museum.)


10/72

Enigma

Siemens Halkse T-52 Sturgeon (Enigma) cipher machine.

(Photo and copy courtesy John Alexander, G7GCK Leicester, England.)


11/72

Colossus

The Colossus (ca. 1944).

(Source: http://www.turing.org.uk/turing/scrapbook/electronic.html.)


12/72

The ENIAC

(Time & Life Pictures/Getty Images.)


13/72

Moores Law

Computing power doubles every 18 months, for the same price.


14/72


15/72

The von Neumann Model

The von Neumann model consists of five major components:(1) input unit; (2) output unit; (3) arithmetic logic unit; (4) memory unit;(5) control unit.


16/72

The System Bus Model

A refinement of the von Neumann model, the system bus model has a CP(ALU and control), memory, and an input/output unit.

Communication among components is handled by a shared pathway callthe system bus, which is made up of the data bus, the address bus, and thcontrol bus. There is also a power bus, and some architectures may also ha separate I/O bus.


17/72

A Typical

ComputerSystem

(Computer case source http://www.baber.com/cases/mpe_md14_silver.htm.Motherboard source ftp://ftp.tyan.com/img_mobo/i_s2895.tif)


18/72

The Motherboard

Source: Courtesy Tyan Computer Corp. (USA).

An AMD Opteron 200 based motherboard.


19/72

Memory & Storage
http://en.wikipedia.org/wiki/Image:Computer_storage_types.svg


20/72

AMD Phenom 2 Die


21/72

Intel Nehalem (Core i7) ProcessorDie


22/72

Intel Nehalem (Core i7) ProcessorWafer


23/72

inputs outputssystem

Combinational vs. sequentialdigital circuits

A simple model of a digital system is a unit with inputsand outputs:

Combinational means "memory-less a digital circuit is combinational ifits output values only depend on its

input values

Sequential systems have memory The output values depend on the input values and previous input

values


24/72

Combinational logic topics

Logic functions, truth tables, and switches NOT, AND, OR, NAND, NOR, XOR, . . .

minimal set

Axioms and theorems of Boolean algebra

proofs by re-writing

proofs by perfect induction Gate logic

networks of Boolean functions

time behavior

Canonical forms

two-level

incompletely specified functions

Simplification

Boolean cubes and Karnaugh maps

two-level simplification


25/72

The Combinational Logic Unit Translates a set of inputs into a set of outputs according to one or more

mapping functions. Inputs and outputs for a CLU normally have two distinct (binary)

values: high and low, 1 and 0, 0 and 1, or 5 V. and 0 V. for example.

The outputs of a CLU are strictly functions of the inputs, and theoutputs are updated immediately after the inputs change. A set ofinputs i

0i

nare presented to the CLU, which produces a set of outputs

according to mapping functionsf0fm.


26/72


27/72

Alternate Assignments of Outputs

to Switch Settings Logically identical truth table to the original (see previous

slide), if the switches are configured up-side down.


28/72

Truth Tables Showing All PossibleFunctions of Two Binary Variables

The more frequently used functions have names: AND, XOR,OR, NOR, XOR, and NAND. (Always use upper case spelling.)


29/72


30/72


31/72

Minimal set of functions

All logic functions can be implemented from NOT,AND, and OR Can we do it with only 2 of the 3?

Can we implement all logic functions from NOT,NOR, and NAND? For example, implementing X and Y

is the same as implementing not (X nand Y)

In fact, we can do it with only NOR or only NAND NOT is just a NAND or a NOR with both inputs tied

together

X = Xnand X X = X nor X NAND and NOR are "duals",

that is, its easy to implement one using the other

X nand Y not ( (not X) nor (not Y) )

X nor Y not ( (not X) nand (not Y) )


32/72


33/72


34/72

The Mathematics: Booleanalgebra A Boolean algebra is an algebraic structurethat consists of

a set of elements B; B = {0, 1} binary operations { + , }; + is logical OR, is

logical AND and a unary operation { ' }; ' is logical NOT such that the following axioms (laws) hold:

1. the set B contains at least two elements, a, b, such that a b2. closure: a + b is in B a b is in B3. commutativity: a + b = b + a a b = b a4. associativity: a + (b + c) = (a + b) + c a (b c) = (a b) c5. identity: a + 0 = a a 1 = a6. distributivity: a + (b c) = (a + b) (a + c) a (b + c) = (a b) + (a c)7. complementarity: a + a' = 1 a a' = 0


35/72

X, Y are Boolean algebra variables

X Y X Y0 0 00 1 0

1 0 01 1 1

X Y X' Y' X Y X' Y' ( X Y ) + ( X' Y' )0 0 1 1 0 1 10 1 1 0 0 0 01 0 0 1 0 0 01 1 0 0 1 0 1

( X Y ) + ( X' Y' ) X = Y

X Y X' X' Y0 0 1 00 1 1 1

1 0 0 01 1 0 0

Boolean expression that istrue when the variables Xand Y have the same valueand false, otherwise

Logic functions and Booleanalgebra Any logic function that can be expressed as a truth table can be written

asan expression in Boolean algebra using the operators: ', +, and


36/72

CSE 370 Winter 2002 - CombinationalLogic - 36

Useful laws (Axioms) andtheorems Identity a + 0 = a a 1 = a Null a + 1 = 1 a 0 = 0

Idempotent a + a = a a a = a

Involution (a) = a

Complementarity a + a' = 1 a a' = 0

Commutativity a + b = b + a a b = b a

Associativity a + (b + c) = (a + b) + c a (b c) = (a b) c

Distributivity a + (b c) = (a + b) (a + c) a (b + c) = (a b) + (a c)

Uniting a b + a b = a (a+b) (a + b) = a

Absorbtion a + a b = a a (a + b) = a

Absorbtion # 2 (a + b) b = a b (a b)+ b = a+ b

deMorgans law and some more useful


37/72


deMorgan s law and some more usefulones

de Morgan's(a + b + ...)' = a' b' ... (a b ...)' = a' + b' + ...

generalized de Morgan's:f'(X1,X2,...,Xn,0,1,+,) = f(X1',X2',...,Xn',1,0,,+)

establishes relationship between and +

Duality (a+b+c+ )D

= (a b c ) (a b c )D

= (a+b+c+..) Generalized duality

{f(X1,X2,...,Xn,0,1,+,) } D = f(X1,X2,...,Xn,1,0,,+)

Factoring (a+b) (a+c) = a c + ab (a b)+(a c) = (a+c) (a+b)

Consensus a b + b c + a c = a b + a c

(a+b) (b+c) (a+c) = (a+b) (a+c)


38/72


39/72


S-o-P, P-o-S, and de Morganstheorem

Sum-of-products F' = A'B'C' + A'BC' + AB'C'

Applyde Morgan's (F')' = (A'B'C' + A'BC' + AB'C')' F = (A + B + C) (A + B' + C) (A' + B + C)

Product-of-sums F' = (A + B + C') (A + B' + C') (A' + B + C') (A' + B' + C) (A' + B' +

C')

Apply de Morgan's (F')' = ( (A + B + C')(A + B' + C')(A' + B + C')(A' + B' + C)(A' + B'

+ C') )' F = A'B'C + A'BC + AB'C + ABC' + ABC


40/72

6/23/2012CSE 370 Winter 2002 - CombinationalImplementation - 40

Implementations of two-levellogic

Sum-of-products AND gates to form product terms (minterms)

OR gate to form sum

Product-of-sums

OR gates to form sum terms (maxterms)

AND gates to form product

F = ABC + AB + BC

G = (A+B)(B+C)(A+B+C)


41/72


Two-level logic using NAND gates Step 1: Replace minterm AND gates with NAND gates

and place compensating inversion at inputs of OR gate


42/72


Two-level logic using NAND gates(contd)

Step 2: OR gate with inverted inputs is a NAND gate de Morgan's: A' + B' = (A B)'

Two-level NAND-NAND network

inverted inputs are not counted

in a typical circuit, inversion is done once and signal distributed


43/72

6/23/2012 CSE 370 Winter 2002 - CombinationalImplementation - 43

Two-level logic using NOR gates Step 1: Replace maxterm OR gates with NOR gates

and place compensating inversion at inputs of AND gate

l l l


44/72


Two-level logic using NOR gates(contd)

Step 2: AND gate with inverted inputs is a NOR gate de Morgan's: A' B' = (A + B)'

Two-level NOR-NOR network

inverted inputs are not counted

in a typical circuit, inversion is done once and signal distributed


45/72


A

BC

DE

FG

X

Multi-level logic

x = A D F + A E F + B D F + B E F + C D F + C E F + G reduced sum-of-products form already simplified

6 x 3-input AND gates + 1 x 7-input OR gate (that may not evenexist!)

25 wires (19 literals plus 6 internal wires)

x = (A + B + C) (D + E) F + G factored form not written as two-level S-o-P

1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input AND gate

10 wires (7 literals plus 3 internal wires)


46/72


Choosing the best realization

Two-level logic: usually has minimal delay Usually means faster circuits But with more gates (more transistors) and more

wires (larger circuit area); hence requires more power.

Easy to eliminate static hazards (see later) Sometimes requires large fan-ins

Multilevel logic usually requires less gates Usually means smaller circuits Less gates, less wires, shorter wires

Harder to eliminate hazards


47/72


Issues with multilevel design

No global definition of an optimalmultilevel circuit Depends on user-defined goals (number of

gates, delay etc.)

Use of synthesis (starting with a formaldescription and proceeding to a logic diagram)to meet the design goals

Synthesis requires CAD-tool help No simple hand methods like Karnaugh maps CAD tools manipulate Boolean expressionswith some heurisitics to achieve goals


48/72

The Multiplexer


49/72

6/23/2012 CSE 370 Winter 2002 - Hazards - 49

two alternative formsfor a 2:1 Mux truth table

functional formlogical form

A Z

0 I0

1 I1

I1 I0 A Z0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 0

1 0 0 0

1 0 1 11 1 0 1

1 1 1 1

Z = A' I0 + A I1

A is control

I0 , I1 are input

Z is output

Multiplexers (aka selectors)

Multiplexers/selectors: general concept 2n data inputs, n control inputs (called "selects"), 1 output

used to connect 2n points to a single point

control signal pattern forms binary index of input connected tooutput


50/72


2 -1

I0I1I2I3I4

I5I6I7

A B C

8:1mux

Z

I0I1I2I3

A B

4:1mux

ZI0I1

A

2:1mux

Z

k=0n

Multiplexers/selectors (cont'd) 2:1 mux: Z = A' I0 + A I1

4:1 mux: Z = A' B' I0 + A' B I1 + A B' I2 + A B I3

8:1 mux: Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 +A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7

In general, Z = (mkIk)

in minterm shorthand form for a 2n:1 Mux

G l l i l i f


51/72


Gate level implementation ofmuxes

2:1 mux

4:1 mux


52/72

Gate-Level Layout of Multiplexer

M lti l l


53/72

6/23/2012 CSE 370 Winter 2002 - Hazards - 53CA B

0

1

2

34

567

1

0

1

00

011

S2

8:1 MUX

S1 S0

F

Multiplexers as general-purposelogic

A 2n:1 multiplexer can implement any function of n variables

with the variables used as control inputs and

the data inputs tied to 0 or 1

in essence, a lookup table

Example: F(A,B,C) = m0 + m2 + m6 + m7

= A'B'C' + A'BC' + ABC' + ABC

M lti l l


54/72


A B C F

0 0 0 1

0 0 1 0

0 1 0 10 1 1 01 0 0 01 0 1 0

1 1 0 1

1 1 1 1

C'

C'

0

1 A B

S1 S0

F0

1

23

4:1 MUX

C'

C'

01

F

CA B

0

1

23

456

7

1

0

10

001

1S2

8:1 MUX

S1 S0

Multiplexers as general-purposelogic (contd)

A 2n-1:1 multiplexer can implement any function of n variables

with n-1 variables used as control inputs and

the data inputs tied to the last variable or its complement

Example:

F(A,B,C) = m0 + m2 + m6 + m7= A'B'C' + A'BC' + ABC' + ABC= A'B'(C') + A'B(C') + AB'(0) + AB(1)


55/72

Implementing the Majority Functionwith an 8-1 Mux

Principle: Use the mux select to pick out the selected minterms of thefunction.


56/72

Efficiency: Using a 4-1 Mux toImplement the Majority Function

Principle: Use the A and B inputs to select a pair of minterms. The

value applied to the MUX input is selected from {0, 1, C, C} to pick

the desired behavior of the minterm pair.


57/72

The Demultiplexer (DEMUX)


58/72


1:2 Decoder:O0 = G SO1 = G S

2:4 Decoder:O0 = G S1 S0O1 = G S1 S0O2 = G S1 S0O3 = G S1 S0

3:8 Decoder:O0 = G S2 S1S0O1 = G S2 S1 S0O2 = G S2 S1 S0

O3 = G S2 S1 S0O4 = G S2 S1S0O5 = G S2 S1 S0O6 = G S2 S1 S0O7 = G S2 S1 S0

Demultiplexers (aka decoders)

Decoders/demultiplexers: general concept single data input, n control inputs, 2n outputs

control inputs (called selects (S)) represent binary index of outputto which the input is connected

data input usually called enable (G)

Demultiplexers as general-purpose


59/72


F1

F2

F3

Demultiplexers as general purposelogic (contd)

F1 = A' B C' D + A' B' C D + A B C D

F2= A B C' D + A B C

F3 = (A' + B' + C' + D')

A B

0 A'B'C'D'1 A'B'C'D2 A'B'CD'3 A'B'CD4 A'BC'D'5 A'BC'D6 A'BCD'7 A'BCD8 AB'C'D'9 AB'C'D10 AB'CD'11 AB'CD

12 ABC'D'13 ABC'D14 ABCD'15 ABCD

4:16DECEnable

C D


60/72


61/72

A 2-to-4 Decoder


62/72

Using a 3-to-8 Decoder to Implementthe Majority Function


63/72

Sequential Logic

The combinational logic circuits we have been studying so farhave no memory. The outputs always follow the inputs.

There is a need for circuits with memory, which behavedifferently depending upon their previous state.

An example is a vending machine, which must remember howmany coins and what kinds of coins have been inserted. Themachine should behave according to not only the current coininserted, but also upon how many coins and what kinds of coinshave been inserted previously.

These are referred to asfinite state machines, because they canhave at most a finite number of states.


64/72

S-R Flip-Flop

The S-R flip-flop is an active high (positive logic) device.


65/72

NAND Implementation of S-R Flip-Flop

A NOR implementation of an S-R flip-flop is converted into a NAND

implementation.


66/72


67/72

Clocked S-R Flip-Flop

The clock signal, CLK, enables the S and R inputs to the flip-flop.


68/72

Clocked D Flip-Flop

The clocked D flip-flop, sometimes called a latch, has a potential

problem: If D changes while the clock is high, the output will also change.

The Master-Slave flip-flop (next slide) addresses this problem.


69/72

Clocked T Flip-Flop

The presence of a constant 1 at J and K means that the flip-flop will change

its state from 0 to 1 or 1 to 0 each time it is clocked by the T (Toggle) input.

Cl k d J K Fli Fl


70/72

Clocked J-K Flip-Flop The J-K f lip-flop eliminates the disallowed S=R=1 problem of the S-R flip-

flop, because Q enables J while Q disables K, and vice-versa. However, there is still a problem. If J goes momentarily to 1 and then back

to 0 while the flip-flop is active and in the reset state, the flip-flop will

catch the 1. This is referred to as 1s catching.

The J-K Master-Slave flip-flop (next slide) addresses this problem.


71/72

Master-Slave Flip-Flop

The rising edge of the clock loads new data into the master, while the

slave continues to hold previous data. The falling edge of the clock loads

the new master data into the slave.


72/72

Master-Slave J-K Flip-Flop

Documents

Computer Architechture & Organization Ch-1