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ASIA PACIFIC INSTITUTE OF INFORMATION TECHNOLOGY APIIT Diploma Part II INCOURSE ASSIGNMENT CSA Case Study 3 Memory Architecture Prepared By A.S.Tiffaniya Fernando (CB004165) A.N.Ahamed Nishadh (CB004081) S.D.Ilangakoon (CB004041) Module Code & Title AICT001-3-2 Computer Systems Architecture Cohort DF10A1ICT Date of Submission 12 th May 2011 Instructor Dr.Gayan Jayakody Submitted in partial fulfillment for the degree of Bachelor of Science (Hons) in Computing Word Count [2900 words]

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Page 1: Computer Systems Architechture

ASIA PACIFIC INSTITUTE OF INFORMATION

TECHNOLOGY

APIIT Diploma Part II

INCOURSE ASSIGNMENT

CSA – Case Study 3 – Memory Architecture

Prepared By

A.S.Tiffaniya Fernando (CB004165)

A.N.Ahamed Nishadh (CB004081)

S.D.Ilangakoon (CB004041)

Module Code & Title

AICT001-3-2 – Computer Systems Architecture

Cohort

DF10A1ICT

Date of Submission

12th May 2011

Instructor

Dr.Gayan Jayakody

Submitted in partial fulfillment for the degree of

Bachelor of Science (Hons) in Computing

Word Count

[2900 words]

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GROUP COMPONENT INDIVIDUAL

COMPONENT

Ass

um

pti

on

s (5

)

Rep

ort

co

nte

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(10

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Dia

gram

s an

d/o

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gure

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An

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ical

an

d C

riti

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Thin

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0)

Do

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n (

5)

Ref

eren

cin

g (1

0)

Gro

up

To

tal (

70

)

Pre

sen

tati

on

(2

0)

Pro

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s R

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5)

Wo

rklo

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)

Ind

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ua

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30

)

Gra

nd

To

tal (

10

0)

Tiffaniya

Fernando

Ahamed

Nishadh

Deshan

Ilangakoon

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WORKLOAD MATRIX

Name / CB

No.

Work Assigned

Work

Completed

Comments & Signature

Tiffaniya Ahamed Deshan

Tiffaniya

Fernando

CB004165

Memory Hierarchy

Introduction of the

document

Proofing the

document

ALL

COMPLETED

Ahamed

Nishadh

CB004081

RISC Architecture

Compiling the

Document

Frequently Asked

Questions

ALL

COMPLETED

Deshan

Ilangakoon

CB004041

Cache memory

GANTT Chart

Meeting Minutes

ALL

COMPLETED

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PROJECT GNATT CHART

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ACKNOWLEDGEMENTS

Firstly we would like to thank our lecturer Dr.Gayan Jayakody for all the help and

guidance given to us while doing this assignment. Especially for teaching us this

module in such a way that we were able to learn this highly technical module very

easily.

Also there are many individuals who have helped us in numerous ways directly and

indirectly so that we were able to complete this assignment.

APIIT Lanka for providing us with resources and the Tech Team at APIIT Lanka for

their assistance at required times.

And last but not least our friends, parents and the well-wishers without whose moral

support and encouragement, we would not have been able to do a good job.

Finally, if there are any shortcomings in this project, then we request to excuse us for

all those and accept this documentation.

Tiffaniya Fernando

Ahamed Nishadh

Deshan Ilangakoon

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TABLE OF CONTENTS

WORKLOAD MATRIX .............................................................................................. ii

PROJECT GNATT CHART ....................................................................................... iii

ACKNOWLEDGEMENTS ........................................................................................ iv

TABLE OF CONTENTS .............................................................................................. v

1.0 – INTRODUCTION ................................................................................................ 1

2.0 – MEMORY HIERARCHY ................................................................................... 2

2.1 – PRINCIPLE AND BENEFITS ........................................................................ 2

2.2 – HOW CAN THE MEMORY HIERARCHY PROVIDES BOTH FAST AND

THE LARGE CAPACITY ....................................................................................... 3

2.3 – WHAT TYPICAL PROGRAM BEHAVIOR COINCIDES WITH THE

BENEFITS OF A MEMORY HIERARCHY? ........................................................ 4

3.0 – CACHE ................................................................................................................ 6

3.1 – CACHE MEMORY WRITE STRATEGIES .................................................. 7

4.0 – REDUCED INSTRUCTION SET COMPUTERS .............................................. 9

4.1 – ADVANTAGES OF USING REGISTERS OVER MEMORY ................... 10

5.0 – FREQUENTLY ASKED QUESTIONS ............................................................ 12

6.0 – CRITICAL EVALUATION .............................................................................. 16

6.1 – TIFFANIYA FERNANDO ........................................................................... 16

6.2 – AHAMED NISHADH ................................................................................... 18

6.3 – DESHAN ILANGAKOON ........................................................................... 20

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BIBLIOGRAPHY ....................................................................................................... 22

TABLE OF FIGURES ................................................................................................ 24

APPENDIX ................................................................................................................. 25

1.0 – MEETING MINUTES .................................................................................. 25

1.1 – 1st MEETING ............................................................................................. 25

1.2 – 2nd

MEETING ............................................................................................ 27

1.2 – 3rd

MEETING ............................................................................................ 28

1.2 – 4th

MEETING ............................................................................................ 29

1.2 – 5th

MEETING ............................................................................................ 30

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1.0 – INTRODUCTION

The Computer System Architecture assignment that was handed out on the 10th

March 2011 is a Research based assignment. It was separated into 3 Case Studies of

which one has to be selected to research upon.

The Case Study that our group decided upon to carry out the research on is the 3rd

Case Study Memory Architecture. This Case Study contained 3 parts. The first

relating to Memory Hierarchy, the second Cache Memory and the third is RISC

Architecture.

This assignment was carried out by our group and the complied document containing

the result of our research is given in this documentation

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2.0 – MEMORY HIERARCHY

2.1 – PRINCIPLE AND BENEFITS

Memory hierarchy is designed is based on three important principles:

Make the common case fast.

Principle of locality

Smaller s faster

A memory system is a hierarchy of storage devices with different capacities, costs,

and access times. A memory hierarchy is successful if the data and instructions are

available, when needed. On the top of the hierarchy. CPU registers hold the most

frequently used data. Small, fast cache memories nearby the CPU act as staging areas

for a subset of the data and instructions stored in the relatively slow main memory.

The main memory stages data stored on large, slow disks, which in turn often serve

as staging areas for data stored on the disks or tapes of other machines connected by

networks. A memory hierarchy is successful if data and instructions are available,

when needed, on the top levels of the hierarchy. (Computer Systems: A

Programmer's Perspective, 2011)

The levels of memory in a computer. From fastest to slowest speed, they are shown

in the figure shown below:

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Figure 1 - Memory Hierarchy

A memory hierarchy is computer storage established at each level in the hierarchy by

response time. Since response time, complexity and capacity are related. The levels

may be established by controlling technology.

There are four major storage levels:

Internal – Processor registers and cache.

Main – the system RAM and controller cards.

On- line mass storage – Secondary storage.

Off-line bulk storage – Tertiary and Off-line storage.

This is a most general memory hierarchy structuring. Many other structures are

useful. For example, a paging algorithm may be considered as a level for virtual

memory when designing computer architecture. (www.answers.com, n.d.)

2.2 – HOW CAN THE MEMORY HIERARCHY PROVIDES

BOTH FAST AND THE LARGE CAPACITY

These are the levels in typical memory hierarchy. Moving farther way form CPU the

memory in level become larger and slower.

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Figure 2 - Memory Path

The above principles suggest that we should try to keep recently accessed items in

the fastest memory. Because the smaller memories are more expensive and faster, we

want to use smaller memories to try to hold the most recently accessed items close to

the CPU and successively larger (and slower, and less expensive) memories as we

move away from the CPU. This type of organization is called a memory hierarchy.

Two important levels of the memory hierarchy are the cache and virtual memory.

According to the principles of the memory hierarchy, smaller piece of hardware will

generally be faster than larger pieces. There are methods to improve the memory

accesses:

Wide path Memory Access – Retrieve multiple bytes instead of 1 byte at

time.

Memory Interleaving – Partition memory into subsections, each with its own

address register and data register

Cache Memory

2.3 – WHAT TYPICAL PROGRAM BEHAVIOR COINCIDES

WITH THE BENEFITS OF A MEMORY HIERARCHY?

As discussed in this work, objects typically are small, short-lived and frequently

accessed during their short life span. Thus object references exhibit certain

characteristic properties that make the object fields referred by them suitable

candidates to be cached separately in a cache structure known as an Object-cache.

An Object-cache is a cache structure, separately designed for caching only objects. It

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creates a parallel data access path for objects. The object references are directed

through the Object-cache while the other references are directed through a regular

data cache.

The performance and energy behavior of the benchmark programs was found to be

extremely sensitive to the configuration of the Object-cache, when the optimal

configuration was determined on a per-application basis. The relationship between

the configuration and performance and energy characteristics of a program (of the

entire application) can be explained as follows. A direct mapped Object-cache is

more energy efficient per access, consuming only about 30% of the energy of a

similar sized four-way set associative cache.

This reduction occurs because a direct mapped cache accesses only one tag and data

array per access, while a four-way cache accesses four tag and data arrays per access.

A direct mapped cache can also have a shorter access time in part because multiple

data arrays need not be multiplexed. While a direct-mapped caches hit rate may be

acceptable for many applications, for some applications a direct-mapped cache

exhibits a very poor hit rate and hence suffers from poor performance and energy

consumption.

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3.0 – CACHE

Cache memory is a type of memory subsystem that is used to reduce the CPU’s

accessing time of memory. The CPU has an average execution time of approximately

two nanoseconds and the accessing time of the RAM is near 60 nanoseconds. This

means that the CPU will spend more time looking for the next instruction than

actually executing it.

This is where Cache Memory comes into use. While cache memory is a lot smaller

in size when compared with RAM and other hard drives it is almost double in speed

when compared with RAM but it is also very expensive and therefore is used only in

small amounts. (Gache, 2008)

Cache Memory uses the logic that memory that is accessed is not at random.

Memory does not get placed all over but memory of one program is generally near

another or in a localized area. There are two types of locality:

1. Temporal Locality: These are data or instructions that the CPU will have to

access many times during the execution of a program.

2. Spatial Locality: This is data or instructions that come one after the other in

terms of memory addresses. For example arrays.

(Jayakody, 2011)

Cache can divided into 2 levels. Level 1 (L1) is small in size with about 4-16KB

capacity and has an access time of approximately 10 nanoseconds. This cache level

is built right into the microprocessor. The next is Level 2 (L2). This cache level has a

higher capacity of up to 512 KB with a slightly slower accessing time of 20 to 30

nanoseconds. However CPU’s cannot have only L1 cache memory as this would be

expensive and also the CPU does not require such large amount of cache due to the

above mentioned locality of reference or addresses. Cache only has to load the data

or instructions that will be needed immediately and the CPU can then access this

data or instructions much faster.

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As mentioned above cache is used to reduce the accessing time of the CPU. How this

works is the CPU will initially look for the required data or instructions in the cache

memory. If it is available then the required data or instructions are immediately

loaded into the processor. This is called as a Cache Hit where the required data or

instructions are found in the cache memory. However on certain occasions the

required instruction or data may not be available in the cache memory and the CPU

is then forced to look for it in the RAM. When a situation like this occurs it is called

a Cache Miss. When this happens the CPU wastes valuable processor time looking

for this data in the RAM. (Gache, 2008)

The usefulness of Cache memory is determined by calculating the Hit Rate. This is

calculated by dividing the Cache Hits by the sum of the Cache Hits and Cache

Misses and the result is given as a percentage.

For a cache memory to be effective the Hit Rate should be greater than 90%. If lower

than this the Cache memory is not useful.

3.1 – CACHE MEMORY WRITE STRATEGIES

There are three main write strategies that are used to write to cache memory:

1. Write-back

2. Write-through

3. Buffered Write

Write-back also known as Copy-back is when a write is made to the current cache

memory. However this write is made only to the cache memory and not to the

system memory. This will stay in the cache till a new system address requires that

space in which instance the data is written into the system memory and the space

taken up is made available. The main advantage to Write-back or the copy-back

policy is that it reduces the write load to the memory. However this method slows

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down when it comes to loading new cache lines as it has to first remove the existing

line, write it to memory and then only replace the cache with new memory.

Write-through the write is made to the cache and the related memory at the same

time. The main advantage of Write-back policy is that both cache and memory

copies get updated at the same time. This is especially useful in multiprocessor

systems. However this method has a drawback, which is that it tends to waste bus

and memory bandwidth.

Buffer write on the other hand does not write to memory immediately. However it

buffers the write and writes at a later instance and is useful when using a write

through policies. (www.pcguide.com, 2001) and (Dandamudi, 2003)

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4.0 – REDUCED INSTRUCTION SET COMPUTERS

The RISC architecture is a relatively new type of CPU architecture that is very much

different in how it works compared to the CISC CPU architecture. As the name itself

suggests, this architecture is where certain functionality of the CPU is changed to

improve the efficiency and performance of the CPU. And thus to improve the

performance of the CPU, designers researched on and found out that certain

instructions are used very often than some others and also that most programmers

avoid using complex instruction sets in programs.

And therefore to optimize the performance, these unwanted wastages were cut down

to increase the performance.

Main features of RISC architecture are:

1. Limited set of simple instructions which can be executed in a very short

time using the optimized CPU’s.

2. Register oriented instruction with limited access to memory so that the

instructions are executed faster.

3. It’s a length independent architecture which means that the length of the

instructions is fixed and it doesn’t require calculation of previous

instructions to continue with the next which again makes the execution of

instructions faster.

(Jayakody, 2004)

Some examples of processors using the RISC architecture are the SPARC (Scalable

Processor ARChitecture) by Sun Microsystems, MIPS (Microprocessor without

Interlocked Pipeline Stages) by MIPS Technologies, IBM R6000, DEC Alpha by

Digital Equipment Corporation and POWER-PC (Performance Optimization With

Enhanced RISC – Performance Computing) by Apple, IBM and Motorola together.

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In the current era, it can be seen that the Apple iPods, Apple iPhones, Nintendo

Gameboy devices, Sony Walkman devices and some mobile phones also using

CPU’s with the RISC architecture implemented into them. (Cook, 2008)

4.1 – ADVANTAGES OF USING REGISTERS OVER MEMORY

The main advantage of using registers over memory in instructions is that registers

work faster than normal memory. It can be seen in the memory hierarchy diagram in

section X above that registers are faster than normal memory modules in terms of

data store and load. Thus when using registers, the instruction can be executed faster

as very few instructions access the memory thus the time wasted in retrieving is

reduced.

Also the number of clock cycles per taken for each instruction to be executed is

reduced when registers are used. When the memory is being accessed, the number of

clock cycles taken is more compared to the cycles taken when accessing the register.

Figure 3 - CISC v RISC

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When the numbers of clock cycles are less and the instructions get executed faster,

the performance of the computer is increased. More work can be done in less time

thus making the computer more efficient.

One more advantage in this situation is the cost involved. Although memory is

cheaper than registers, in the CPU designs, the registers cost less than transistors

which are used mainly in the CISC computers. And so the cost of the CPU is also

brought down and the concept of Very Large Scale Integration is brought into work

at this instance as more space is available when transistors are not used hence more

registers can be used or the size of the CPU can be reduced. (Wang & Horvath, n.d.)

Also in the case of RISC architecture, it’s more favored by the programmers. It is a

known fact that very few programmers tend to write complex instruction sets.

Programmers often right simple instruction sets that are faster to execute and so the

RISC architecture helps them in their work. (Swanson, 2003)

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5.0 – FREQUENTLY ASKED QUESTIONS

Q : What is Memory ?

A : Memory can be referred to the components in a computer or electronic device

where data can be stored for running the device. Memory are of different types and

are used according to the need.

Q : What is a Memory Hierarchy ?

A : A memory hierarchy is the hierarchy of memory. It is usually ordered in the

speed of the memory type. For example, Registers are at top as they are very fast

while hard disks are at last as they are comparatively slower.

Q : What are the different types of memory ?

A : Registers, Cache Memory, Main Memory, Magnetic Disk, Magnetic Tapes and

other disks.

Q : What are the 4 storage levels ?

A : Internal, Main, On- line mass storage, Off-line bulk storage

Q : What is Cache Memory?

A : Cache memory is used by the CPU to reduce the speed it takes for reading

memory by keeping back-ups of the most frequently and recently used data and

instructions.

Q : How is Cache Memory used ?

A : When the CPU needs to Read or Write data to the main memory it Reads and

Writes to the Cache since it is a lot faster than Reading or Writing to the main

memory. This helps the CPU to increase its speed since main memory takes a longer

period to execute than the CPU

Q : What is Locality?

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A : Locality is the Logic that is used behind Cache memory. This logic says that the

memory addresses of the memory that the CPU needs to access is not at random.

Instead it is either in a temporal, this refers to repetitive memory, or spatial, which

refers to memory that comes in a sequential manner.

Q : What are write strategies used for?

A : Write strategies determine how the data or instructions that needs to be written

into the main memory and the cache is done. There are three methods or policies.

They are Write-back, Write-through and Buffered Write.

Q : What are Cache Hits and Misses?

A : When the CPU looks for the data or instructions that it needs in the Cache and

finds it, it is known as a Cache Hit. If it does not find the data or instructions in the

Cache it is known as a Cache Miss.

Q : What is a CPU ?

A : The CPU, also known as the processor of a computer is the main element of the

computer system. It is where all the calculations take place to run the computer.

Q : Name two types of CPU Architectures ?

A : There are many CPU architectures that are used when designing CPU’s. Two of

the main architectures are the Complex Instruction Set Computer Architecture and

the Reduced Instruction Set Computer Architecture.

Q : What is a Cycle in terms of CPU Cycle ?

A : A CPU Cycle refers to a single pulse of the computer clock. For example, a 4

MHz CPU will have 4 million CPU cycles per second. (http://www.codepedia.com,

2004)

Q : What is Very Large Scale Integration ?

A : VLSI is an integrated circuit design that contains 5,000 to 50,000 components on

a single chip. (http://www.computerhope.com, n.d.)

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Q : What is a RISC Architecture ?

A : Developed and introduced by IBM in 1980, RISC is short for Reduced

Instruction Set Computer and pronounced as risk. RISC is a processor architecture

that requires fewer instructions to operate, causing the processors to be faster than

earlier CISC processors. (www.computerhope.com, n.d.)

Q : Examples for RISC Architecture ?

A : SPARC (Scalable Processor ARChitecture) by Sun Microsystems, MIPS

(Microprocessor without Interlocked Pipeline Stages) by MIPS Technologies, IBM

R6000, DEC Alpha by Digital Equipment Corporation and POWER-PC

(Performance Optimization With Enhanced RISC – Performance Computing) by

Apple, IBM and Motorola together.

Q : How many levels are there in cache memory?

A : Two levels, Level1 and Level2.

Q : Which level is faster?

A : Level1.

Q : Which level has more memory capacity?

A : Level 2

Q : What is Write -Back?

A : Write-Back writes to cache only not the main memory.

Q : What is Right-Through?

A : Write through to both cache and main memory.

Q : What is Buffered- Right?

A : Buffers write instruction until a later moment.

Q : What is the Hit rate?

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A :

Q : What are the types of locality?

A : Temporal Locality and Spatial Locality.

Q : What is Temporal Locality?

A : Memory that it used repetitively.

Q : What is Spatial Locality?

A : memory that is accessed in sequence order.

Q : In memory what is the speed to capacity relationship?

A : Greater the capacity, Slow the speed.

Q : What’s the average access time of cache?

A : 10 nanoseconds.

Q : What are the main two types of RAM?

A : SDRAM and DRAM.

Q : What are the two main types of ROM?

A : PROM and EPROM

Q : What are the main major storage levels?

A : Internal, main, off-line mass and off-line bulk.

Q : What are the two important levels of memory hierarchy?

A : Cache and Virtual Memory.

Q : What other types of CPU Architectures are available?

A : RISC, CISC, VLIW, etc.

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6.0 – CRITICAL EVALUATION

6.1 – TIFFANIYA FERNANDO

My group members and me decided to work on case 3. This case is about Memory

Architecture. As the leader of my group I assigned the questions to my group

members according to the case. And I decided to take the first question from the case

that is about the Memory Hierarchy. This was a new task for me and I selected this

topic because it’s a topic where I was interested in this module. Though I learned

about memory hierarchy in class, this assignment helped me a lot to improve my

knowledge on this particular subject. I did my research on this project in various

ways, such as browsing online, referred books and my lecturer gave me a fair idea on

memory hierarchy. With the help of all these researches and lectures my knowledge

on memory hierarchy gradually improved.

I had no knowledge on the principle of the memory hierarchy, but however I

managed to get help from my other group members whenever I get stuck and also

some of the websites from Google helped me a lot to get fair knowledge on the

specific topic. I was able to manage the troubles, and I overcome along that.

The opportunity of being a group leader was great experience for me, I learnt to

handle group members, and I was able to overcome the problems and we shared

information among us. I managed to work with my group members in a pleasant

way, and also I have been with the same group members in my previous assignments

as well. So it was an awesome experience to work the same people as a group leader.

As I mentioned before I was assigned to do question one, but this question had three

different parts. Even though I already had an idea on this topic the last part of the

question I didn’t understand, so I got help from one of my group member, after he

explained me I started on my research through Internet and now am familiar with the

whole question.

I had certain knowledge about memory hierarchy; also I knew the memory hierarchy

chart, so I drew it on my document.

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Another task I was assigned to do is finalizing the document, after getting all the

documents from my group members. My group members did meeting minutes and

the Gantt chart, and my part was to finalize the documentation.

As a conclusion, the project was successfully managed for the submission. And It

was so thankful to gain more knowledge about memory hierarchy.

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6.2 – AHAMED NISHADH

In this research based assignment I was faced with the problem of researching every

little bit of details from scratch as it was a completely new topic. We all use various

computerized electronic devices in our day to day lives but we never for a minutes in

our busy days stop to think how each device works, what is exactly happening inside

the device, what are the components inside the device, how are they designed etc.

But after doing this research, I was able to get a very idea on how the main element

of any computerized electronic device work. The Central Processing Unit also

referred to as the brain of the computer or any computerized device is actually a very

interesting component. It is actually amazing to know how such a small component

contains so many elements inside it and does so much work

At the beginning of this research I had very little idea of what CPU architectures,

addressing modes, registers and memory meant as we hadn’t by the time I had

started the research studied those. As time went on while studying about these at

lectures and by reading up on articles on the internet as well as in books I was able to

get a comprehensive idea on what these meant and how they are all connected to

each other.

In my documentation, I have referenced from various sources. It should be noted that

most of my references have been made from lecture notes or handouts given at

various higher education institutes. I choose to use this information as sources for my

documentation as these are information compiled by learned people in those relevant

fields of study and the information is authentic and reliable most of the time. This

helps me make sure that I have real and known information in my documentation

rather than unknown or unreliable information.

In addition to this, I have also reference lectures notes given to us by our lecturer.

Certain definitions have been taken from websites that are specialized in providing

definitions for technical words. I used this source for this information as they are

reliable and are being used and trusted by many users.

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At the end of the research I am now able to understand completely on how CPU’s

work and the different kind of architectures that are used in designing CPU’s, the

way they work, how changes in CPU components change the way they work and

how it affects the performance of the computer as a whole where those that I gained

knowledge on.

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6.3 – DESHAN ILANGAKOON

The group in which I worked for this assignment chose case study 3 and I was

assigned to undertake the second segment of that case study which was pertaining to

Cache Memory. This confronted me with a new challenge. Though I had previously

learnt about Cache Memory this assignment opened my view to help me understand

Cache in a wider perspective. In the compilation of information for this assignment I

researched in depth to find information regarding Cache memory. My understanding

on Cache has vastly improved during the course of this project.

I had no knowledge on certain segments such as Cache Write strategies. This posed a

fairly strong challenge to me. However with help from the rest of my team members

I was able to overcome these problems. I also had to employ self-learning in order to

complete this assignment up to the standards that were expected of me.

The opportunity to work with the members I have in my group was also a very

enjoyable and an extremely pleasant experience. Working with this group was also

very easy since I had worked with them on prior assignments and thus I was familiar

with them.

The work that I was assigned to do as mentioned above was section 2 of the second

case study. In this section the work required me to investigate into Cache Memory,

specifically on how it works with regards to speed of execution and fetching

instructions. I also had to research on what Cache Hits and Cache Misses are and

what relevance they have to Cache Memory

I also had to research into the Write Policies employed when writing Cache into

memory. The main three policies that I researched into were Write-back or Copy-

back, Write-through and Write with buffer. For the assignment I had to research into

how each policy works compare their advantages and disadvantages.

Another task that I was assigned to do was assigned was the maintaining of meeting

minutes. This task was fairly easy since I had previously also been tasked with

handling the meeting minutes.

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The main problem that I faced during the assignment is the lack of information

regarding the Write policy Write with Buffer. However I was able to after searching

the internet find a PDF document with information regarding Write with buffer.

In conclusion this assignment, though a challenge, was highly fruitful and helped me

immensely in gaining a better understanding of Cache memory and I am thankful for

that opportunity.

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BIBLIOGRAPHY

Computer Systems: A Programmer's Perspective, 2011. Chapter 6 - The Memory

Hierarchy. [Online] Available at: http://csapp.cs.cmu.edu/public/ch6-preview.pdf

[Accessed 2011].

Cook, C.D., 2008. [Online] Available at:

http://www.cs.sjsu.edu/~lee/cs147/RISC%20vs.%20CISC.ppt [Accessed 2011].

Dandamudi, S., 2003. Cache Memory. [Online] Available at:

http://www.scs.carleton.ca/sivarama/org_book/org_book_web/slides/chap_1_version

s/ch17_1.pdf [Accessed 2011].

Gache, G., 2008. How Cache Memory Works. [Online] Available at:

http://news.softpedia.com/news/How-Cache-Memory-Works-83803.shtml [Accessed

2011].

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http://www.codepedia.com/1/CPU+cycles [Accessed 2011].

http://www.computerhope.com, n.d. VLSI. [Online] Available at:

http://www.computerhope.com/jargon/v/vlsi.htm [Accessed 2011].

Jayakody, D.G., 2004. RISC and CISC Architecture. Lecture Notes. Asia Pacific

Institute of Information Technology.

Jayakody, D.G., 2011. “Type of memory”. Lecture Notes. Asia Pacific Institute of

Information Technology.

Swanson, W., 2003. The Art of Picking Intel Registers. [Online] Available at:

http://www.swansontec.com/sregisters.html [Accessed 2011].

Wang, R. & Horvath, T., n.d. RISC vs. CISC. [Online] Available at:

www.cs.virginia.edu/~skadron/cs654/cs654_01/slides/tibor.ppt [Accessed 2011].

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http://www.answers.com/topic/memory-hierarchy [Accessed 2011].

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http://www.computerhope.com/jargon/r/risc.htm [Accessed 2011].

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TABLE OF FIGURES

Figure 1 - Memory Hierarchy ...................................................................................... 3

Figure 2 - Memory Path ............................................................................................... 4

Figure 3 - CISC v RISC ............................................................................................. 10

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APPENDIX

1.0 – MEETING MINUTES

1.1 – 1st MEETING

Date : Tuesday 15th

March 2011

Time of Commencement : 04.50 pm

Time of Conclusion : 05.15 pm

Venue : APIIT, Union Place, 6th

Floor Cafeteria

Members Present : Tiffaniya Fernando

Ahamed Nishadh

Deshan Ilangakoon

Agenda:

Deciding on which case study to be undertaken

Maintaining meeting minutes and records

Minutes

The meeting commenced with Tiffaniya taking the lead and asking the rest of the

group which case study would be best to take up and who would want to tackle each

part. Deshan said that both case studies two and three were good and Ahamed

suggested that since Memory Architecture was the easiest that this should be the

topic that would be followed. Since there were no disagreements on this point it was

finalized that the group would take on case study 3.

The next matter was who should take on which part of the assignment. After a brief

discussion it was decided that Part A of the case study would be taken or by

Tiffaniya Part B by Deshan and Part C by Ahamed.

After this the next matter that was brought up was the recording and maintaining of

the minutes of the meeting that is being held and those to come. Deshan volunteered

to take on this task and said he would maintain all the records.

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After this meeting was adjourned until the 30th

of March 2011.

………………………………….

Group Leader

………………………………….

Lecturer

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1.2 – 2nd

MEETING

Date : Wednesday 30th

March 2011

Time of Commencement : 03.30 pm

Time of Conclusion : 04.00 pm

Venue : APIIT, Union Place, 6th

Floor Cafeteria

Members Present : Tiffaniya Fernando

Ahamed Nishadh

Deshan Ilangakoon

Agenda:

Reading of previous meetings minutes

Assessment of group progress

Minutes

The meeting started with a brief re-cap of the previous meetings minutes. After

which Tiffaniya asked each member as to how the progress of their allocated

sections was fairing. Both Ahamed and Deshan stated that though they had not

started to compile the document they had begun research into their sections.

After this problems that were being faced by the members were discussed. since it

was still in the early stages of the research there were no problems as yet to be

discussed.

Meeting was adjourned until the 6th

of April 2011.

………………………………….

Group Leader

………………………………….

Lecturer

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1.2 – 3rd

MEETING

Date : Tuesday 5th

April 2011

Time of Commencement : 04.50 pm

Time of Conclusion : 05.15 pm

Venue : APIIT, Union Place, 6th

Floor Cafeteria

Members Present : Tiffaniya Fernando

Ahamed Nishadh

Deshan Ilangakoon

Agenda:

Reading previous meeting minutes

Assessment of work

Problems faced

Minutes

The main reason for this meeting to be called was to check on the progress of the

work that has so far been done. Here all the work done so far was presented and

Tiffaniya checked on the work to see if the work done was accurate and adequate.

Tiffaniya told all the members present that the work done so far was in her opinion

satisfactory and no further change.

Tiffaniya then asked the members present as to whether there were any difficulties

that they were facing. Deshan stated that he was having a little difficulty finding

information on section B of his allocated part 2. Ahamed stated that he was not

facing any difficulties as yet but would let the group know if he was.

The meeting was after this, adjourned the 26th

of April.

………………………………….

Group Leader

………………………………….

Lecturer

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1.2 – 4th

MEETING

Date : Tuesday 26th

April 2011

Time of Commencement : 04.50 pm

Time of Conclusion : 05.15 pm

Venue : APIIT, Union Place, 6th

Floor Cafeteria

Members Present : Tiffaniya Fernando

Ahamed Nishadh

Deshan Ilangakoon

Agenda:

Reading previous meeting minutes

Assessment of work

Problems faced

Minutes

The meeting commenced by going over the last meeting minutes to see if there were

any problems that were carried on from the last meeting. Deshan said that he was no

longer having difficulty in finding information and was getting along fine with the

work.

Ahamed pointed out that he was having a few problems as he did not have any prior

knowledge of the topic but said he could manage.

After this the meeting was adjourned until the 10th

of May where all the separate

segments would be complied.

………………………………….

Group Leader

………………………………….

Lecturer

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1.2 – 5th

MEETING

Date : Tuesday 10th

May 2011

Time of Commencement : 04.50 pm

Time of Conclusion : 05.15 pm

Venue : APIIT, Union Place, 6th

Floor Cafeteria

Members Present : Tiffaniya Fernando

Ahamed Nishadh

Deshan Ilangakoon

Agenda:

Collect all information from all members and to compile it

Minutes

The main purpose of this meeting was so that all the information and documents of

each separate member could be collected and compiled. All the members handed

over their documents to Ahamed who agreed to compile it and to format it into the

specified way.

After this Tiffaniya thanked all for the hard work and the meeting was adjourned.

………………………………….

Group Leader

………………………………….

Lecturer