Jeff Sopc Framework

.......................................................................................................................i

ABSTRACT .................................................................................................................ii .....................................................................................................................iii .....................................................................................................................iv

.....................................................................................................................vi ....................................................................................................................vii ...............................................................................................................1 1.1 1.2 ............................................................................................1 ........................................................................................................2

........................................................................................................3 2.1 2.2 2.3 2.4 2.5 2.6 (Color Space) ..................................................................................3 (Spatial Filter) .............................................................................4 ....................................................................................................4 (Morphology)......................................................................................5 (Connected-Component Labeling) ...........................................6 ................................................................................................7

.........................................................8 3.1 NIOS ......................................................................................8 3.1.1 ............................................................................................8 3.1.2 Avalon Bus .................................................................................9 3.1.3 ..........................................................................................12 3.1.4 DMA Controller ................................................................................14 3.1.5 ..........................................................................................16 3.2 ......................................................................................................17 3.2.1 CMOS Sensor () ................................................................18 3.2.2 Bayer Color Pattern Data to 30-Bit RGB...........................................20 3.2.3 VGA Controller and Data Request ....................................................22iv

3.2.4 VGA DAC() ......................................................................23 ..................................................................................24 4.1 4.2 4.3 4.4 4.5 4.6 ......................................................................................24 ......................................................................................25 ..........................................................................................26 VGA_IF ...............................................................................29 CCD_IF................................................................................30 ......................................................................................31

...............................................................32 5.1 ..................................................................................32 5.1.1 VGA_IF Finite State Machine...........................................................32 5.1.2 Reset ........................................................................................34 5.1.3 Snapshot Operation ...........................................................................35 5.1.4 .......................................................................36 5.2 ......................................................................................................37 5.2.1 ...............................................................................37 5.2.2 Example 1Bypass ..........................................................................38 5.2.3 Example 2Single Frame Process - RGB2Gray...............................39 5.2.4 Example 3Scale and Diff ...............................................................40 5.2.5 Example 4 ..................................................43 .............................................................................................................46 ....................................................................................................................47

v

2. 1 3. 1 3. 2 3. 3 3. 4 4. 1 4. 2 5. 1 5. 2 RBG-YUVRGB-YCbCr ............................................................3 Avalon Bus ...........................................................................................9 DMA ...............................................................................................14 Status .......................................................................................14 Control ...................................................................................15 VGA_IF ..................................................................................29 CCD_IF ...................................................................................30 VGA_IF Finite State Machine .............................................................33 CCL ( clock) .............................................................44

vi

2. 1 2. 2 2. 3 2. 4 2. 5 2. 6 3. 1 3. 2 3. 3 3. 4 3. 5 3. 6 3. 7 3. 8 3. 9 3. 10 3. 11 3. 12 3. 13 3. 14 3. 15 3. 16 3. 17 3. 18 3. 19 3. 20 Mean Filter ....................................................................................................4 (Erosion) ....................................................................................5 (Dilation)....................................................................................5 4 8 ............................................................................................6 ................................................................................6 ...............................................................................................7 ...................................................................................................8 -............................................................................................10 -............................................................................................10 -............................................................................................ 11 -............................................................................................ 11 ..............................................................................12 .....................................................................................................13 SOPC Builder ........................................................13 Timer ...................................................................16 DE2 ...........................................................................................17 130 ..........................................17 MT9M011 .........................................................................................18 Timing Example of Pixel Data ...................................................................18 Row Timing and FRAME_VALID/LINE_VALID Signals .........................18 Bayer Color Pattern ...................................................................................19 Bayer Color Pattern ...........................................................19 Line Buffer ...............................................................................20 Stack .........................................................................................21 VGA Controller ................................................................22 VGA D/A Converter ......................................................................23

vii

4. 1 4. 2 4. 3 4. 4 4. 5 4. 6 4. 7 4. 8 4. 9

FIFO ...........................................................................24 .................................................................................................25 VGA ....................................................................................26 Signal Tap II Trigger ...................................................................27 Arbitration (1,1,1)..................................27 Arbitration (2,2,6)..................................27 Arbitration (20,20,60) ..........................28 VGA_IF ..................................................................................29 CCD_IF ...................................................................................30

4. 10 ...............................................................................31 5. 1 5. 2 5. 3 5. 4 5. 5 5. 6 5. 7 5. 8 5. 9 5. 10 5. 11 5. 12 5. 13 5. 14 5. 15 VGA_IF State Machine ...............................................................................32 VGA_IF Raise DMA State Machine ..................................................33 .....................................................................................................34 Snapshot Operation ........................................................................35 ..............................................................................36 .....................................................................................................36 Example 1 Buffer ...............................................................................38 Example 2 Buffer ...............................................................................39 Example 3 VGA ..................................................................40 Example 3 Buffer ..................................................40 Example 3 ................................................................................42 Example 4 VGA LCM .................................................44 Example 4 .....................................................................44 Example 4 ................................................................................45 LCM ..................................................................................45

viii

1.1

Server Server ObjectVideo, Inc. ObjectVideo OnBoard TI DaVinci SOPC FPGA SOPC(System On Programmable Chip ) NIOS Altera SOPC FPGA NIOS (1)(2) CMOS Sensor Avalon Bus SDRAM VGA Avalon Bus SDRAM Avalon Master Interface Avalon Slave Interface FIFO

1

DMA Master Device FIFO SDRAM CMOS Sensor Frame SDRAM CMOS Sensor VGA CPU CMOS Sensor

1.2 Altera NIOS

2

(Computer Vision)

2.1 (Color Space)[1] (RGB )(YUV )(U*V*W ) RGB YUV YCbCr YCbCr YUV 2. 1 YUV to RGB UV 0 R=G=B=Y

RGB to YUV

YUV to RGB

RGB to YCbCr

YCbCr to RGB

2. 1 RBG-YUVRGB-YCbCr Y = 0.299R + 0.587G + 0.114B U =-0.196R - 0.331G + 0.500B V = 0.500R - 0.419G - 0.081B R = 1.000Y + 1.402V G = 1.000Y - 0.344U - 0.714V B = 1.000Y + 1.722U Y = 0.257R + 0.504G + 0.098B + 16 Cb=-0.148R - 0.291G + 0.439B + 128 Cr= 0.439R - 0.368G - 0.071B + 128 R = 1.164(Y-16) + 1.596(Cr-128) G = 1.164(Y-16) - 0.391(Cb-128) - 0.813(Cr-128) B = 1.164(Y-16) + 2.018(Cb-128)

3

2.2 (Spatial Filter)(Image Enhancement)[1] (Low-Pass Filter) (Band-Pass Filter)(High-Pass Filter) Mean Filter ( 2. 1) Median Filter

1/9 1/9 1/9 1/9 1/9 1/9 1/9 1/9 1/9 3x3 mask

0 0 0 0

0 0 0 0

0 90 9 0

0 0 0 0Mean filter

0 0 0 0

10 11 11 1

10 11 11 1

10 11 11 1

2. 1 Mean Filter

2.3 [2] 0 1 0 1 (Threshold) () 0 1 1

4

2.4 (Morphology)[1] 4 (Erosion)( 2. 2)(Dilation) ( 2. 3)(Opening)(Closing) AB B A 2. 2 2. 3 Opening Erosion Dilation Closing Dilation Erosion Dilation A B Erosion AB Opening A o B = ( AB) B Closing A B = ( A B)B

B

BA

A

2. 2

(Erosion)

B

BA

A

2. 3

(Dilation)

5

2.5 (Connected-Component Labeling) (CCL)[3] (Segmentation) (Pattern Recognition ) (Connected-Component)4 (4-adjacent) 8 (8-adjacent) 2. 4 (Labeling) (1)Label-Assigning (2)Label-Merging Union-Find 2. 5

0 1 0

1 P 1

0 1 0

1 1 1

1 P 1

1 1 1

4-adjacent

8-adjacent

2. 4

4 8

v Component labeling process example Setp1: Label-Assigning

1 0 0 0 1 1 0 0 1 1 0 1 0 1 1 0 0 1 0 0

1 1 0 0

0 0 1 0

0 0 0 1

0 2 2 0

2 2 2 0Equivalent relation:Pair(1,2)

Step2: Label-Merging

1 1 0 0

0 0 1 0

0 0 0 1

0 1 1 0

1 1 1 0

1 1 0 0

0 0 1 0

0 0 0 1

0 2 2 0

2 2 2 0

1 1 0 0

0 0 1 0

0 0 0 1

0 1 1 0

1 1 1 0

2. 5

6

2.6 (Temporal Differencing)(Background Subtraction)[2](Optical Flow) ( 2. 6)

RGBY F ? T

Mean Filter

2. 6

2. 6 Mean Filter

7

3.1 NIOS NIOS NIOS DMA Controller NIOS

3.1.1 NIOS SOPC Builder Symbol Quartus Symbol Export NIOS IDE SOPC Builder .ptf system.h Pin Assign .v Top-Level Entity 3. 1

symbol1

3 2 4

.ptf system.h

3. 1

8

3.1.2 Avalon Bus Avalon Bus[4][5] Avalon Bus Avalon Bus Avalon 3. 1

Specification

3. 1 Avalon Bus Description

4GB 32 (Memory-Mapped) Avalon Chip Select Avalon Avalon SOPC Builder (/ )Avalon Avalon

9

Avalon l Read 3. 2 A D clk clk

3. 2

-

3. 3 E clk E

3. 3

-

10

l

Write 3. 4 A C clk

clk

3. 4

-

3. 5 D clk D

3. 5

-

11

3.1.3 Avalon Bus Avalon Bus .v SOPC Builder Component Editor Component Editor Top Level Module Signals 3. 6 Interfaces Avalon Bus Export Export Symbol Address Signal Type Width 32bit 4G 3bit 8 Chip Select SOPC Builder ( 3. 7) ( 3. 8)

3. 6

12

3. 7

3. 8

SOPC Builder

13

3.1.4 DMA Controller DMA Controller[4] NIOS DMA Controller SDRAM Controller SDRAM DMA Controller ( )() DMA 3. 2

3. 2 DMA Register Map

DMA

l l l l

status DMA readaddress DMA writeaddress DMA lengthlength ( byte )length

l

control DMA 3. 3 Status done busy reop weop len DMA DMA DMA

0 1 2 3 4

14

0 1 2 3 4 5 6 7 8 9

byte hw word go i_en reen ween leen rcon wcon

3. 4 Control (8-) (16-) (32-) DMA 0 DMA

DMA Controller //word IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_BASE, 0x0294); // IOWR_ALTERA_AVALON_DMA_STATUS(DMA_BASE, 0); // IOWR_ALTERA_AVALON_DMA_RADDRESS(DMA_BASE, S_ADDR); // IOWR_ALTERA_AVALON_DMA_WADDRESS(DMA_BASE, D_ADDR); // IOWR_ALTERA_AVALON_DMA_LENGTH(DMA_BASE, LEN); //DMA IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_BASE, 0x029c);

15

3.1.5 NIOS IDE alt_timestamp()[6] System Timestamp Timer 3. 9 #include #include "sys/alt_timestamp.h" int main() { alt_u32 time1; alt_u32 time2; if (alt_timestamp_start() < 0) { printf ("No timestamp device available\n"); } else { time1 = alt_timestamp(); //do something time2 = alt_timestamp(); printf("time(2-1)=%u\n",(unsigned int)(time2-time1)); } }

3. 9

Timer

16

3.2 DE2( 3. 10)[7]( 3. 11) Multi-Port SDRAM Controller CPU CMOS Sensor VGA Controller VGA

3. 10

DE2

3. 11

130

17

3.2.1 CMOS Sensor () MT9M011(1/3-Inch Megapixel Image Sensor)[8] 3. 12 3. 13 3. 14 PIXCLKLINE_VAILD FRAME_VAILD Dout Bayer Color Pattern ( 3. 15)

3. 12

MT9M011

3. 13

Timing Example of Pixel Data

3. 14

Row Timing and FRAME_VALID/LINE_VALID Signals

18

3. 15

Bayer Color Pattern

Bayer Color Pattern 3. 16

3. 16

Bayer Color Pattern

19

3.2.2 Bayer Color Pattern Data to 30-Bit RGB CMOS Sensor CMOS Sensor X-Y X-Y 1280 1024 Shift-Register (Ram-Base) Line Buffer RAM-2port Stack VGA 640 480 1/4 640 512 3.17 3.18 Line Buffer Stack 3. 17 Line Buffer 3. 18

tap distance

Total distance=3*5=15

3. 17

Line Buffer

20

3. 18

Stack

21

3.2.3 VGA Controller and Data RequestVGA 640 480@60Hz 60 640 480[9] 25MHz H-Sync( ) V-Sync() VGA VGA 3. 19 640 480@60Hz H_SYNC_TOTAL =H_SYNC_FRONT+H_SYNC_CYC+H_SYNC_BACK+H_SYNC_ACT =16+96+48+640=800 V_SYNC_TOTAL =V_SYNC_FRONT+V_SYNC_CYC+V_SYNC_BACK+V_SYNC_ACT =10+2+33+480=525 Total pixel 800x525x60=25200000DotClock=25MHz ACT(Active) 640 480 H-Cont() V-Cont()

front sync

back

active

640*480@60hz H front=16 H sync=96 H back=48

3. 19

VGA Controller

22

3.2.4 VGA DAC() ADV7123[10] 30bits 10bits R 10bits G 10bits B 3. 20 VGA

3. 20

VGA D/A Converter

23

4.1 [7] 4-Port SDRAM 4-Port 4-Port 2-Port 16bits 32bits 2-Port 16bit 32bits FIFO(Dual-Clock FIFO)[11] SDRAM Controller 16bits SDRAM 4 Port 4. 1 FIFO SDRAM Controller SDRAM SDRAM Controller FIFO 4-Port FIFO SDRAM Controller VGA Block + CCD Block

@100MHz x 16bits

CCD Block

FIFO FIFO

SDRAM Controller

FIFO FIFO

VGA Block

@25/4MHz x 32bits SDRAM

VGA : @25MHz x 32bits LCM : @18MHz x 10bits

FIFO size total 512 SDRAM Controller 256SDRAM256SDRAM

4. 1 FIFO 24

4.2 CCD Block VGA Block NIOS Avalon Bus 4. 2 CCD VGA FIFO CCD_IF( CCD Interface ) FIFO DMA SDRAM FIFO VGA_IF( VGA Interface ) FIFO DMA SDRAM FIFO FIFO CPU SDRAM NIOS IDE () CCD_IF VGA_IF CCD_IF VGA_IF NIOS DMA Avalon Bus FIFO DMA

CPU

Avalon Bus 100Mhz

Arbitration

CCD_IF

VGA_IF

SDRAM Controller

CCD Block

VGA Block SDRAM

4. 2

25

4.3 4. 2 SDRAM SDRAM Arbitration (instruction master, data_master, dma_read_master) SDRAM Arbitration (1,1,1) (1Hz) VGA Controller(25MHz) buffer 640 480 0 640 480-1 4. 3 Signal tap II Trigger 4. 4 VGA H_COUNT=144V_COUNT=34 VGA buffer 0 H_COUNT=144 V_COUNT=35 buffer 640 H_COUNT=144V_COUNT=513 306560 CPU instruction_master data_master

144 34 35

0 640

306560 513

4. 3

VGA

26

4. 4

Signal Tap II Trigger

4. 5

Arbitration (1,1,1)

4. 6

Arbitration (2,2,6)

27

4. 7

Arbitration (20,20,60)

clk DMA Arbitration (2,2,6) 4. 6 Arbitration (20,20,60) 4. 7 clk Arbitration (1,1,1) 4. 5 VGA

28

4.4 VGA_IFVGA_IF VGA_IF Avalon Slave Avalon Master 4. 8 CPU Slave_1 Control Master_0 FIFO (wrusedw) Master_0 DMA DMA SDRAM () Slave_0()( FIFO Avalon Bus Slave)FIFO Export VGA Controller 4. 1 VGA_IF Description FIFO DMA buffer (read address) FIFO (write address) DMA DMA ()

Interface Slave_0 Slave_1

Offset 0 0 1 2 3 4 7

DMA control write read Avalon Bus 100MhzSlave_1 Master_0 Slave_0

CPU

Arbitration

MasterDevVGA_IF

wrusedw

write async FIFO read

SDRAM Controller

VGA Controller 25Mhz

SDRAM

4. 8

VGA_IF

29

4.5 CCD_IFCCD_IF CCD_IF Avalon Slave Avalon Master 4. 9CPU Slave_1 Control Master_0 FIFO (rdusedw) Master_0 DMA DMA Slave_0 ( FIFO Avalon Bus Slave) () SDRAM() SDRAM 4. 2 CCD_IF Description FIFO DMA() buffer (read address) FIFO (write address) DMA DMA ccdBusy ()

Interface Slave_0 Slave_1

Offset 0 0 1 2 3 4 5 7

DMA control read write Avalon Bus 100MhzSalve_1 Master_0 Salve_0

CPU

Arbitration

MasterDevCCD_IF

rdusedw

read async FIFO write CCD Capture 25Mhz

SDRAM Controller

SDRAM

4. 9

CCD_IF

30

4.6 VGA_IF CCD_IF 4. 10 Output_IF VGA_IFInput_IF CCD_IF CPU CPU DSP Block

CPU

Avalon BusArbitration

Input_IF

Output_IF

SDRAM Controller

DSP Block SDRAM

4. 10

31

4.4 4.5 5.1 5.2

5.1 VGA_IF FIFO DMA Controller SDRAM

5.1.1 VGA_IF Finite State MachineVGA_IF Master Port Finite State Machine FIFO (1)Check FIFO Size (2)Raise DMAState Machine Check FIFO Size DMA DMA DMA Raise DMA DMA CCD_IF VGA_IF VGA_IF 5. 1 5. 1 5. 2

Check FIFO Size

Raise DMA

5. 1

VGA_IF State Machine

32

State Check FIFO Size

5. 1 VGA_IF Finite State Machine Description FIFO Raise DMA clk

Raise DMA

VGA_IF Master DMA (a) (b) (c)() (d)() (e) (f) DMA (g) DMA Busy 0 (h) Check FIFO Size

Enter State

Setup Control register

Clear Interrupt

Count readIndex Setup readaddress

Setup writeaddress

Setup length

DMA go

Read status

Check busy

T F

Exit State

5. 2

VGA_IF Raise DMA State Machine33

5.1.2 Reset VGA CCD (1) FIFO(2) DMA() (3) CCD VGA Delay 5. 3

FIFO

Master Dev

VGA / CCD

5. 3

34

5.1.3 Snapshot Operation Frame CCD_IF FIFO (writeIndex ) CCD Block CCD Block 25MHz CCD_IF 0 1 Frame 5. 4

CPU CPU CCD_IF CCD_IF @100MHz @100MHz CPU busy CCD_IF Control Register CCD_IF CCD_IF frame busy

CCD frame data CCD Block frame CCD Block frame

CCD CCD Block Block @25MHz @25MHz

5. 4

Snapshot Operation

35

5.1.4 5. 5 5. 6

5. 5

5. 6

36

5.2 5.2.1 VGA//setup VGA //dma addr IOWR(VGA_IF_0_BASE,4,0x00800820); //maxAddr maxaddr=(640*480-128)*4; IOWR(VGA_IF_0_BASE,7,maxaddr); //readAddress IOWR(VGA_IF_0_BASE,1,&buffer2); //writeAddress IOWR(VGA_IF_0_BASE,2,0x00800818); //length length=128*4; IOWR(VGA_IF_0_BASE,3,length); //master start IOWR(VGA_IF_0_BASE,0,0x0001);

CCD//setup CCD //dma addr IOWR(CCD_IF_0_BASE,4,0x00800860); //maxAddr maxaddr=(640*512-128)*4; IOWR(CCD_IF_0_BASE,7,maxaddr); //readAddress IOWR(CCD_IF_0_BASE,1,0x00800880); //writeAddress IOWR(CCD_IF_0_BASE,2,&buffer1); //length length=128*4; IOWR(CCD_IF_0_BASE,3,length); //Snap Operation IOWR(CCD_IF_0_BASE,0,0x0001);

37

5.2.2 Example 1BypassCCD VGA Buffer CCD VGA Buffer 5. 7

SDRAM640

VGA

480 512

CCD

CCD Capture

VGA Controller

5. 7

Example 1 Buffer

while(1){ //capture image IOWR(CCD_IF_0_BASE,0,0x0001); //wait ccd ccdBusy=1; while(ccdBusy){ ccdBusy=IORD(CCD_IF_0_BASE,5); } }

38

5.2.3 Example 2Single Frame Process - RGB2Gray VGA CCD Buffer1 Buffer2 CCD VGA Buffer1 Buffer2 5. 8

CCD

VGA

0,0

0,0

511,639

479,639

buffer1

buffer2

5. 8

Example 2 Buffer

while(1){ IOWR(CCD_IF_0_BASE,0,0x0001); ccdBusy=1; while(ccdBusy){ ccdBusy=IORD(CCD_IF_0_BASE,5); } index=0; for(i=0;i 10; b =( buffer1[index]& 0x3FF00000 ) >> 20; r=(299*r); g=(587*g); b=(114*b); y=(b+g+r)>>10; y=y>=1024?1024:y; buffer2[index]=(y1))*640+(0+(j>>1))]&0x000003FF); //abs tmp=tmp>0?tmp:-tmp; buffer2[(py+(i>>1))*640+(px+(j>>1))]= (tmp&0x000003FF)>64?0xFFFFFFFF:0; }else{ buffer2[(py+(i>>1))*640+(px+(j>>1))]= rgb2gray(buffer1[index]); } } index++; } } }

41

Diff

5. 11

Example 3

42

5.2.5 Example 4[3]

(1) An Iterative Algorithm (2) The Classical Algorithm (3) A Space-Efficient Two-Pass Algorithm That Uses a Local Equivalence Table 18 18 (16 16)0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

(1)(2) Union-Find (1) (2) Two-Pass (3) (1)(2) (3)

43

5. 2 CCL ( clock) 1 2 73383 177377 177377 21853 53048 53006 144872 347662 347639

(1) (2) (3)

The Classical Algorithm 160 120 VGA_IF LCM 5. 13 5. 14 VGA 5. 12

VGA

LCM

Diff

CCL

5. 12

Example 4 VGA LCM

CPU

Avalon Bus 100Mhz

Arbitration

CCD_IF

VGA_IF

VGA_IF

SDRAM Controller

CCD Block

LCM Block

VGA Block SDRAM

5. 13

Example 4 44

5. 14

Example 4

Diff Mean Filter Threshold CCL

5. 15

LCM

45

Example 1 NIOS [7]Example 2 - CPU SDRAM CPU Example 3 Example 4 VGA_IF LCM( LCD Module ) NIOS

Altera FIFO DMA Controller SOPC VGA_IF CCD_IF NIOS CPU

46

[1] [2] 2005 / [3] Haralick, Robert M., and Linda G. Shapiro, Computer and Robot Vision, Volume I, Addison-Wesley, 1992, pp. 28-48 [4] [5] [6] [7] NIOS SOPC 2005 Avalon Bus Specification Reference Manual, Version 1.2, Altera, 2002 Nios II Software Developers Handbook, Version 7.1 , Altera , 2007 , p1145 FPGA CMOS Image Sensor http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=Taiwan&Category No=50&No=90 [8] MT9M011 1/3-Inch Megapixel CMOS Active-Pixel Digital Image Sensor Data Sheet , [9] Micron Technology Inc. 2004 Monitor Timing Specifications, Version 1.0, Video Electronics Standards Association, 1998, p7 [10] ADV7123, CMOS, 240 MHz Triple 10-Bit High Speed Video DAC, Analog Devices, Inc., 1998 [11] Single- and Dual-Clock FIFO Megafunction User Guide, Version 4.0, Altera , 2007

47

AVGA_IF/CCD_IF

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

module VGA_IF ( //avalon_slave_0 //======data iDATA0, //writedata //======address iADDR0, //address //======control iCS0, //chipselect iWR0, //write iCLK0, //clk iRST_N0,//reset_n //======export erdreq, oDATA_OUT, eVgaCLK, fifo_clr, //avalon_slave_1 //======data iDATA1, //writedata //======address iADDR1, //address //======control iCS1, //chipselect iWR1, //write iCLK1, //clk iRST_N1,//reset_n //avalon_master_0 //data iDATAm, //readdata oDATAm, //writedata //address oADDRm, //address //control oRDm, //read oWRm, //write iWaitm,//waitrequest iCLKm, //clk iReaddatavalid,//readdatavalid //export vgareset ); //slave_0 //======data input [31:0] iDATA0; //======address input iADDR0; //======control input iCS0; input iWR0; input iCLK0; input iRST_N0; //======export input erdreq; output [31:0] oDATA_OUT; input eVgaCLK; input fifo_clr;

-1 -

62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122

//slave_1 //======data input [31:0] iDATA1; //======address input [2:0] iADDR1; //======control input iCS1; input iWR1; input iCLK1; input iRST_N1; //master interface //data input [31:0] iDATAm; output [31:0] oDATAm; //address output [31:0] oADDRm; //control output oRDm; output oWRm; input iWaitm; input iCLKm; input iReaddatavalid; //export input vgareset; reg oRDm; reg oWRm; reg [31:0] oADDRm; reg [31:0] tmpDATAm; reg [3:0] state; assign oDATAm=tmpDATAm; //internal reg //3'b000 reg [31:0] control; //3'b001 reg [31:0] readAddress; //3'b010 reg [31:0] writeAddress; //3'b011 reg [31:0] length; //3'b100 dma address reg [31:0] dmaAddr; //3'b111 reg max addr reg [31:0] maxAddr; reg [31:0] readIndex; wire [8:0] wrusedw; //Avalon Slave0 FIFO in from DMA assign wrreq = ((iADDR0==1'b0)&& iCS0) ? iWR0 : 0; FIFO u1( .aclr(fifo_clr), .data(iDATA0), .q(oDATA_OUT), .rdclk(eVgaCLK), .rdreq(erdreq), .wrclk(iCLK0),-2 -

123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183

.wrreq(wrreq), .wrusedw(wrusedw) ); //Avalon Slave1 Config Coordinator always @(posedge iCLK1) begin if((iADDR1==3'b000 )&& iCS1 control

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