CMOS Transistor Theory (and its effects on scaling)mniemier/teaching/2009_A_Spring/lectures/02... · •So far, we have treated transistors as ideal switches ... 5 Lecture 02 - CMOS

1 Lecture 02 - CMOS Transistor Theory & the Effects of Scaling - CSE 40547/60547

CMOS Transistor Theory(and its effects on scaling)

Michael Niemier

(Some slides based on lecture notes by David Harris)


Nanowire-based Gates

If each wire was just 5 nm in diameter, would you be excited about this technology?

Can make very small pn junctions and diode based lgoic


MOSFET cross section…

n

P

With applied Vgs,depletion region

forms

n


To recap…• So far, we have treated transistors as ideal switches• An ON transistor passes a finite amount of current

– Depends on terminal voltages– Derive current-voltage (I-V) relationships

• Transistor gate, source, drain all have capacitance– I = C (ΔV/Δt) -> Δt = (C/I) ΔV– Capacitance and current determine speed


MOS Capacitor• Gate and body form MOS capacitor• Operating modes

polysilicon gate

(a)

silicon dioxide insulator

p-type body+-

Vg < 0

(b)

+-

0 < Vg < V

t

depletion region

(c)

+-

Vg > V

t

depletion region

inversion region

polysilicon gate

(a)


p-type body+-

Vg < 0

(b)

+-

0 < Vg < V

t

depletion region

(c)

+-

Vg > V

t

depletion region

inversion region

polysilicon gate

(a)


p-type body+-

Vg < 0

(b)

+-

0 < Vg < V

t

depletion region

(c)

+-

Vg > V

t

depletion region

inversion region


Terminal Voltages• Mode of operation depends on Vg, Vd, Vs

– Vgs = Vg – Vs

– Vgd = Vg – Vd

– Vds = Vd – Vs = Vgs - Vgd

• Source and drain are symmetric diffusion terminals– By convention, source is terminal at lower voltage– Hence Vds ≥ 0

• nMOS body is grounded. First assume source is 0 too.• Three regions of operation

– Cutoff– Linear– Saturation

Vg

Vs

Vd

Vgd

Vgs

Vds

+-

+

-

+

-


nMOS Cutoff• No channel formed, so no current flows• Ids = 0

+-

Vgs

= 0

n+ n+

+-

Vgd

p-type body

b

g

s d


nMOS Linear• Channel forms• Current flows from d to s

– e- from s to d• Ids increases with Vds

• Similar to linear resistor

+-

Vgs

> Vt

n+ n+

+-

Vgd

= Vgs

+-

Vgs

> Vt

n+ n+

+-

Vgs

> Vgd

> Vt

Vds

= 0

0 < Vds

< Vgs

-Vt

p-type body

p-type body

b

g

s d

b

g

s dIds

Vgs > VtVds = 0, no current

+-

Vgs

> Vt

n+ n+

+-

Vgd

= Vgs

+-

Vgs

> Vt

n+ n+

+-

Vgs

> Vgd

> Vt

Vds

= 0

0 < Vds

< Vgs

-Vt

p-type body

p-type body

b

g

s d

b

g

s dIds

Vgs > VtVds > 0, but < (Vgs - Vt)

(current flows)


nMOS Saturation• Channel pinches off• Ids independent of Vds

• We say current saturates• Similar to current source

+-

Vgs

> Vt

n+ n+

+-

Vgd

< Vt

Vds

> Vgs

-Vt

p-type body

b

g

s d Ids

Vds > Vgs - VtEssentially, voltage difference over induced channel fixed at Vgs - Vt

(current flows, but saturates)(or ids no longer a function of Vds)


Outline (part 2)• Today…

– nMOS & pMOS I-V characteristics• Why (part 1):

– Quantify - or at least estimate - how we represent & moveinformation

• Why (part 2):– This way we can estimate what happens when we make device

smaller -- and in theory, better.• Possibly today…

– A very brief discussion of RC delay models• Why?

– Important because delay = one of the 2 performance metrics wecare most about.

• Another, “why”– Can leverage in 1st HW :-)

• David Frank talk - starts with 1st principles, extrapolatesto practical, chip-level performance


A little bit of foreshadowing

Board digression #0S2S2/U21P/AreaPower Density11/U21/S2IsatVP

1/S1/S1/SRonCgateIntrinsic Delay

111V/IsatRon

S2S2/USIsat/AreaCurrent Density11/U1/SCoxWVIsat

SSSCoxW/Lkn, kp

1/S1/S1/SCoxWLCgate

SSS1/toxCox

1/S21/S21/S2WLArea/deviceS2S2/USV/Wdepl

2NSUB

11/U1/SVdd, Vt

1/S1/S1/SW, L, tox

Fixed-VoltageScaling

General ScalingFull ScalingRelationParameter



Board digression #0



Board digression #0


tox

350 nm

250 nm

180 nm

150 nm

120 nm90 nm65 nm

350/250=1.4

250/180~1.39

180/150~1.2

150/120~1.25120/90~1.33

90/65~1.38

8/6~1.333

6/3.8~1.58

3.8/2.6~1.46

2.6/1.5~1.71.5/1.2~1.251.25/1~1.25


Ok, let’s derive some I-Vrelationships


I-V Characteristics• In Linear region, Ids depends on

– How much charge is in the channel?– How fast is the charge moving?


Channel Charge• MOS structure looks like parallel plate capacitor while

operating in inversion– Gate – oxide – channel

• Qchannel =

n+ n+

p-type body

+

Vgd

gate

+ +

source

-

Vgs

-drain

Vds

channel-

Vg

Vs

Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2 gate oxide

(good insulator, !ox

= 3.9)

polysilicon

gate

Board digression #1




• Qchannel = CV• C =

n+ n+

p-type body

+

Vgd

gate

+ +

source

-

Vgs

-drain

Vds

channel-

Vg

Vs

Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2 gate oxide


= 3.9)

polysilicon

gate




• Qchannel = CV• C = Cg = εoxWL/tox = CoxWL• V =

n+ n+

p-type body

+

Vgd

gate

+ +

source

-

Vgs

-drain

Vds

channel-

Vg

Vs

Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2 gate oxide


= 3.9)

polysilicon

gate

Cox = εox / tox




• Qchannel = CV• C = Cg = εoxWL/tox = CoxWL• V = Vgc – Vt = (Vgs – Vds/2) – Vt

n+ n+

p-type body

+

Vgd

gate

+ +

source

-

Vgs

-drain

Vds

channel-

Vg

Vs

Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2 gate oxide


= 3.9)

polysilicon

gate

Cox = εox / tox

Board digression #2


Carrier velocity• Charge is carried by e-• Carrier velocity v proportional to lateral E-field

between source and drain• v =



between source and drain• v = µE µ called mobility• E =

Board digression #3

How I try notto teach…



between source and drain• v = µE µ called mobility• E = Vds/L• Time for carrier to cross channel:

– t =



between source and drain• v = µE µ called mobility• E = Vds/L• Time for carrier to cross channel:

– t = L / v

Board digression #4


nMOS Linear I-V• Now we know

– How much charge Qchannel is in the channel– How much time t each carrier takes to cross

dsI =




channel

ds

QI

t=

=




channel

ox 2

2

ds

dsgs t ds

dsgs t ds

QI

t

W VC V V V

L

VV V V

µ

!

=

" #= $ $% &' (

" #= $ $% &' (

ox =

WC

L! µ

Board digression #5


Let’s go back to…



111V/IsatRon


SSSCoxW/Lkn, kp

1/S1/S1/SCoxWLCgate

SSS1/toxCox


2NSUB

11/U1/SVdd, Vt

1/S1/S1/SW, L, tox




nMOS Saturation I-V• If Vgd < Vt, channel pinches off near drain

– When Vds > Vdsat = Vgs – Vt

• Now drain voltage no longer increases current

dsI =





2dsat

ds gs t dsat

VI V V V! " #= $ $% &

' (





( )2

2

2

dsatds gs t dsat

gs t

VI V V V

V V

!

!

" #= $ $% &' (

= $

Board digression #7


nMOS I-V Summary

( )2

cutoff

linear

saturatio

0

2

2n

gs t

dsds gs t ds ds dsat

gs t ds dsat

V V

VI V V V V V

V V V V

!

!

"# <## $ %= & & <' ()

* +##

& >#,

• Shockley 1st order transistor models


Again, let’s go back to…



111V/IsatRon


SSSCoxW/Lkn, kp

1/S1/S1/SCoxWLCgate

SSS1/toxCox


2NSUB

11/U1/SVdd, Vt

1/S1/S1/SW, L, tox




Look at IDS in context of scaling

Board digression #8


Board digression #8

Documents

CMOS Transistor Theory (and its effects on scaling)mniemier/teaching/2009_A_Spring/lectures/02... · •So far, we have treated transistors as ideal switches ... 5 Lecture 02 - CMOS