CMOS Process Technology - Laboratoire …hassan/lec2_process_layout.pdf2 CMOS Process Technology •General Layout Considerations •Wafer Processing •Photolithography •Oxidation

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CMOS Process Technology

•General Layout Considerations•Wafer Processing•Photolithography•Oxidation•Ion Implantation•Deposition and Etching•Device Fabrication.

Hassan AboushadyUniversity of Paris VI

• B. Razavi, “Design of Analog CMOS Integrated Circuits”,McGraw-Hill, 2001.

References

H. Aboushady University of Paris VI

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General Considerations


• How are various regionsdefined so accurately ?

• How are nwells andSource/Drain regions built ?

• How are the gate oxide andpolysilicon aligned withSource/Drain regions ?

• How are the contact window created?

• How are the metal interconnect layers deposited?

Modern CMOS technologies involve more than 200 processing steps !

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General Considerations


(1) Wafer processing toproduce the proper type ofsubstrate.

(2) Photolithography toprecisely define each region.

(3) Oxidation, deposition and ion implantation to add materialsto the wafer.

(4) Etching to remove materials from the wafer.




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Wafer Processing


• The starting wafer in a CMOS technology must be created witha very high quality.

• The wafer must be grown as a single crystal silicon body havinga very small number of “defects”, dislocations or impurities.

• The wafer must contain the proper type and level of doping soas to achieve the required resistivity.

• In most CMOS technologies, the wafer has a resistivity of 0.05to 0.1 Ω.cm and a thickness of 500 to 1000 µm, which reduces toa few hundred microns after all of the processing steps.




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Photolithography


The first step in transferring circuit layout information to Wafer.

Photolithography example: the n-well pattern


(a) The pattern iswritten to a transparentglass mask by aprecisely controlledelectron beam.

(b) The wafer iscovered by a thin layerof photoresist, amaterial whose etchingproperties change uponlight exposure.

(c) The mask is placed on top of the wafer and the pattern isprojected onto the wafer by UV light.

(d) The wafer is placed in an etchant that dissolves the “soft”photoresist area.

Lithography Sequence

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Photolithography Cost


2 types of photoresists:• positive: hardens in areas NOT exposed to light.• negative: hardens in area exposed to light.

Cost of fabrication α number of masks in a process

Lithography is a slow and expensive task.Each mask costs several thousand $

• Historically CMOS, low cost process: only 7 masks.

•New CMOS process: 25 masks, but still low cost because bothnumber of transistors per unit area and the size of the wafer hassignificantly increased.




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Oxidation


Purpose:(1) A thin layer of Si02 for Gate-oxide layers:tox = few nanometers.

(2) A thick layer Si02 ,called “Field Oxide” (FOX), in areas betweendevices. Provides foundation for interconnect lines.

Fabrication:Silicon Dioxide is grown by placing the exposed silicon in anoxidizing atmosphere such as oxygen at a temperature around1000°C.




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Ion Implantation


Doping atoms are accelerated as a high energy focused beam,hitting the surface of the wafer and penetrating the exposedareas.• Doping level: is determined by the intensity and duration of theimplantation.• Depth of doped region: is set by the energy of the beam.

“Channel Stop” Regions


MOS transistor with thick gateoxide :leakage path between M1 & M2.

Channel Stop implant before FOXis grown to to raise VTH to a verylarge value.

Annealing: ion implantation damages the silicon latticeextensively. The wafer is heated to 1000°C for 15~30 mn to allowthe lattice bonds to form again.(This operation results in side-diffusion of Source/Drain regions,creating overlap with the gate area.)

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Channeling


If beam implant is aligned withcrystal axis, the ions penetratethe wafer to a great depth.

The implant is tilted by 7-9°.

Impacts matching of transistorsnecessitating precautions in the layout




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•General Layout Considerations•Wafer Processing•Photolithography•Oxidation•Ion Implantation•Deposition and Etching•Device Fabrication



Basic Transistor Fabrication

(a) A thin layer of Si02 isgrown as a protectivecoating.

(b) Lithography sequence.(c) clean up.

(d) Channel-Stop implantand FOX grown.(e) clean up

(f) Growth of gate-oxide andVTH adjustment.

(g) polysilicon layer isdeposited.

(h) N+ implant.(i) P+ implant.

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“Silicidation”


Sheet resistance of doped polysilicon and Source/Draonregions is typically several tens of ohms per square.

Silicidation: covering polysilicon and active areas with highlyconductive material (titanium silicide).

Oxide Spacer: to avoid the silicide layer on the gate to beshorted to that on the Drain/Source.

Contact and Metal Fabrication


(a) - Cover the wafer with athick layer of oxide.- Lithography sequence usingthe contact mask.- Contact holes are created byplasma etching.

(b) - Metal 1 is deposited overthe entire wafer.- Lithography sequence usingthe Metal 1 mask.- Etching

(c) Same as (b) with metal 2.

Each metal layer requires 2 masks: - 1 mask for the contacts- 1 mask for the metal

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“Spiking”


(a) Spiking due to largecontact areas.

(b) Use of small contacts toavoid spiking.

Layout and Mismatch

•General Layout Considerations•Analog Layout Techniques•Substrate Coupling


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Layout and Mismatch



Device Scaling has increased speed of transistors.

• Unwanted interaction between different sections ofintegrated circuits.

• Non-idealities in layout and packaging limit both thespeed and precision of such systems.

Recent CMOS processes


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Design Rules: Minimum Width, Spacing


Minimum Widthimposed by lithography &processing capabilities

Minimum Width α Layer Thickness

Minimum Spacingif too close they may

be shorted

Minimum Spacingbetween active and poly

Design Rules: Minimum Enclosure, Extension


Minimum Enclosure• nwell and p+ implant must surroundthe PMOS transistor with sufficientmargin.

• To ensure that the contact remainsinside the poly and metal 1 squares,both geometries must enclose thecontact with enough margin.

Minimum Extension• Some geometries must extendbeyond the edge of others by aminimum value.

FOX : A Thick layer of SiO2

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Ex: Differential Pair with PMOS current-source load


Antenna Effect


Layout susceptible toantenna effect

Discontinuity in metal 1 layerto avoid antenna effect.

During etching, metal area acts as an “antenna” collectingions, and rising in potential.

Possible increase of MOS gate voltage to the point thatgate-oxide breaks down during fabrication.

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Layout and Mismatch



Analog Layout Techniques


• CMOS processes aim to maximize the yield of digital ICs.

• Analog systems demand many more layout precautionsso as to minimize effects such as:

• Crosstalk• Mismatch• Noise• ...

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C1 : Oxide capacitance between gate & channel

C2 : Depletion capacitance between channel & substrate

C3 , C4 : Overlap of the gate poly with source and drain areas

C5 , C6 : Junction capacitance between source/drain areasand substrate

MOS Transistor Parasitic Capacitances


jswj

SBDB

CEWCEWCC

)(2 ++==

DBSB

jswjDB

CC

CEWCEWC

2

)2

(22

=

++=

Folding Reduces S/D Junction Area and Gate Resistance


• 1 finger :

• 2 fingers :

GRR =• 1 finger :

• 2 fingers :4

GRR =

Source/Drain Junction Capacitances:

Gate Resistance:

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Multi-Finger Transistors


2 fingers 4 fingers

3 fingers 5 fingers

S/D perimeter capacitance foran odd number of fingers N:

jsw

jswP

CWN

NEN

CNWENC

⎥⎦

⎤⎢⎣

⎡ +++=

⎟⎠

⎞⎜⎝

⎛ ++=

1)1(

222

1

To minimize S/D perimetercapacitance contribution:

WEN <<

May conflict with minimizinggate resistance.

• Pelgrom: « for each parameter P in any two separatetransistors, there exists a fixed part and a randomlyvarying part which can be represented by a randomvariable ∆P such that

where AP and SP are process dependent constants, W and L are transistor dimensions, and D is the separation between the two transistors »

• For matched transistors, we must use large devicesplaced close to each other.

( ) 222

2 DSWLAP P

P +=∆σ

M. Pelgrom et. al. , «Matching Properties of MOS transistors », IEEE JSSC, Vol. 24, No. 5, October 1989

Transistors Matching


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• Transistor Q1 is a diode-connected transistor.

• For two perfectly matched transistors:

• Due to random process variations of

– VTH as a result of differences of oxide thickness,doping, …

– β as a result of differences in W, L, oxide thicknessand mobility

on the same chip:

( )( )

( )( )1

22

11

222

1

111

2

222

11

DS

DS

THGS

THGS

oxn

oxn

in

out

VV

VVVV

LWC

LWC

II

λλ

µ

µ

++

−−=

11

22LWLW

II

in

out =

THTH

VV

III ∆∂

∂+∆∂∂=∆ ββ

Current Mirrors

•

• This variations (∆Vth and ∆β) are modeled as random variables

– σ th = σ (∆Vth) ≈ 10 – 25 mV– σ β = σ (∆β/β) ≈ 0.1 – 10 %

• Assuming that they are statistically independent (uncorrelated) !!

• This error can be made small by– biasing the transistors deeply in strong inversion, (high VGS−Vth).– using closely placed transistors in the layout to reduce random

variations.

THm VI

gII ∆−∆=∆

ββ

22

)(2

⎟⎟⎠

⎞⎜⎜⎝

⎛−

+=⎟⎠⎞

⎜⎝⎛ ∆

thTHGS VVI

I σσσ β

Current Mirrors

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(A) (B)

(C) (D)

ωω

Transistor Mismatch: Orientation

Ex: differential pair which layout ?

Different Orientations !


• During source/drain implantation,if the implant beam is aligned withthe crystal axis, the ions penetratethe wafer to a great depth.

• Wafer implant is tilted by about 7°to avoid channeling.

• Asymmetry between the sourceand drain diffusion after annealing.

ωω

Mismatch Effects: Shadowing


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(B)

(C) (D)

Transistor Mismatch: Shadowing

Ex: differential pair which layout ?

Source/Drain Asymmetry !


• Due to silicon crystal anisotropy, the current is notexactly the same in all directions.

• Dummy transistors are inserted to control currentorientation while minimizing layout area.

(B) (C)

(D) (E)

Transistor Mismatch: Current Orientation


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• During polysilicon etching, it continues to cut under thephotoresist (undercut).

• It depends on the boundary, such that the undercut isdeeper for free space around the gate, affecting gatelength.

• Dummy transistors are inserted at the boundary.ωω

Transistor Mismatch: Boundary Effect


(A) (B)

( ) 241 32

1GSToxoxoxnaDaD VL

WCCCII ∆++=+ µ

( ) 232 22

1GSToxoxoxoxnaDaD VL

WCCCCII ∆++∆+=+ µ

• Solution (A):

( ) 231 22

1GSToxoxoxnbDbD VL

WCCCII ∆++=+ µ

( ) 242 32

1GSToxoxoxoxnbDbD VL

WCCCCII ∆++∆+=+ µ

• Solution (B):

Oxide Gradient

BetterMatching

Transistor Mismatch: Gradient EffectInterdigitization


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• the effect of 1st order gradients along both axes iscancelled.

• Complex routing leading to asymmetries and parasiticcapacitances

Transistor Mismatch: Gradient EffectCommon Centroid


Type I Type II

Mis

mat

ch (%

)

M.- F. Lan et. al. , « Current Mirror Layout Strategies for Enhancing Matching Performance », Kluwer AICSP, July 2001.

Mis

mat

ch (%

)

Matching Techniques: Comparison


Interdigitized Common CentroidType I Type II

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Interconnects


Cross-talk

• Each coupling capacitance mayconsiderably corrupt Vin or Vout.

To reduce Cross-talk effect

Use differential signals.Shield sensitive signals.

Single Ended

DifferentialShielding by ground lines

Greater spacing

Layout and Mismatch



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Substrate Coupling


• Low resistivity of the substratecreates unwanted paths betweenvarious devices in the circuitCorruption of sensitive signals.

The problem

Guard rings

• Isolates the sensitive circuit fromthe substrate noise produced byother sections.

Documents

CMOS Process Technology - Laboratoire …hassan/lec2_process_layout.pdf2 CMOS Process Technology •General Layout Considerations •Wafer Processing •Photolithography •Oxidation