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11© IMSE-CNM ΣΔ Design Group
CMOS SigmaCMOS Sigma--Delta Converters Delta Converters ––From Basics to StateFrom Basics to State--ofof--thethe--ArtArt
RocRocíío del Ro del Ríío, Belo, Beléén Pn Péérezrez--VerdVerdúú and Josand Joséé M. de la RosaM. de la Rosa
{rocio,belen,jrosa}@imse.cnm.es
KTH, Stockholm, April 23-27
Circuits and ErrorsCircuits and Errors
22© IMSE-CNM ΣΔ Design Group
1. Circuits and Errors in DT 1. Circuits and Errors in DT ΣΔΣΔ ModulatorsModulators
2. Circuits and Errors in CT 2. Circuits and Errors in CT ΣΔΣΔ ModulatorsModulators
Errors degrading NTFErrors degrading NTF
Additive noise sourcesAdditive noise sources
Harmonic distortionHarmonic distortion
Case studyCase study
OUTLINEOUTLINE
CT CT ΣΔΣΔM M subcircuitssubcircuits
BuildingBuilding--block errors block errors
Architectural timing errorsArchitectural timing errors
Case studyCase study
3. Layout & Prototyping3. Layout & Prototyping
Layout Layout floorplanningfloorplanning
Chip packageChip package
Test PCB and SetTest PCB and Set--upup
2
33© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Overview of NonOverview of NonOverview of Non---idealities idealities idealities
Finite Amplifier Gain Non-linearities Thermal Noise Comparator hysteresis
Capacitor Mismatch Settling Errors Clock Jitter DAC Non-linearity
… among others …
- Ideal In-Band Error Power:
- Actual In-Band Error Power:
2 2
2 1
1 π12 2 1 (2 +1)
L
Q B LPL OSR +
Δ⎛ ⎞= ⎜ ⎟−⎝ ⎠
...T Q Q TH J HDP P P P P P= + Δ + + + +
44© IMSE-CNM ΣΔ Design Group
Capacitors:- Mismatch- Non-linearity
Amplifiers:- Output swing- DC gain- Dynamic limitations (GB, SR)- Thermal and 1/f noise- Gain non-linearity
Multi-bit ADCs & DACs:- Gain error- Offset error- Non-linearity
DTDT--ΣΔΣΔMs: Ms: Overview of NonOverview of NonOverview of Non---idealities idealities idealities Fully-diff SC schematicof a 2nd-order ΣΔM
Switches:- Finite on-resistance- Thermal noise- Charge injection- Clock feedthrough- Non-linearity
Comparators:- Hysteresis- Offset
Clock:- Jitter
References:- Thermal and 1/f noise- Output impedance
Depending on the building-block:
3
55© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Overview of NonOverview of NonOverview of Non---idealities idealities idealities
Output PSD
f/fs (log)0.50.5/OSR
4th order4th order
3rd order3rd order
2nd order2nd order
AMPLIFIER DC GAIN
CAPACITOR MISMATCH
INTEGRATOR SETTLINGAmplifier GBAmplifier SRSwitch Ron
ERRORS DEGRADING NTF
CASCADE ΣΔMsNoise leakagesImperfect cancellation oflow-order quantization errors 1st order1st order
Impact dependson topology
SINGLE-LOOP ΣΔMsLow sensitivity
Depending on their effect:
66© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Overview of NonOverview of NonOverview of Non---idealities idealities idealities
CIRCUIT NOISEThermal noise (switches, opamps, refs)1/f noise (opamps, refs)
DISTORTION
Non-linear amplifier gainNon-linear capacitorsNon-linear settlingNon-linear switches
CLOCK JITTER
MODELED AS ADDITIVE ERRORS
Front-enddominates
Similar impact ondifferent topologies
AMPLIFIER DC GAIN
CAPACITOR MISMATCH
INTEGRATOR SETTLINGAmplifier GBAmplifier SRSwitch Ron
ERRORS DEGRADING NTF
CASCADE ΣΔMsNoise leakagesImperfect cancellation oflow-order quantization errors
Impact dependson topology
SINGLE-LOOP ΣΔMsLow sensitivity
Depending on their effect:
4
77© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Integrator Leakage Integrator Leakage Integrator Leakage
Ideal SC integrator SC integrator considering amplifier finite gain
Amplifier gain1
2
CgC
=
Shift of the pole from DC (z = 1)
Effect of amplifier gain on the integrator transfer function:
88© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Integrator Leakage Integrator Leakage Integrator Leakage
Lth-order ΣΔM:
Effect on single-loop ΣΔMs: - Ideally:
- In practice:
Quite insensitive to leakages (μ2, L-1 shaping)
2nd-order ΣΔM
5
99© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Integrator Leakage Integrator Leakage Integrator Leakage Effect on cascade ΣΔMs:
2-1-1 ΣΔM
- Ideally:- In practice:
low-order leakages
(L1-1, L2-1, …)
Mismatch between analog and digital
filtering
1010© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Integrator Leakage Integrator Leakage Integrator Leakage
Sensitivity to integ leakages of cascades increases with OSR and L1st-stage leakages dominate (L1-1 shaping)
Comparison of integrator leakage effect on 4th-order ΣΔMs
(ideal)
6
1111© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Capacitor Mismatch Capacitor Mismatch Capacitor Mismatch
Circuit primitive: Physical implementations:
“Analog” CMOS“Digital” CMOS “Mixed” CMOS
MOS cap
1212© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Capacitor Mismatch Capacitor Mismatch Capacitor Mismatch Local and global errors in:
1 1g Cu
umg Cnσ σ
= + ⋅
σC ~ 0.05% - 0.1% using good quality caps and adequate layout strategies
1
2
u
u
CCg nC Cm
= =
Centroid techniques
AreaCapacitance per Unit Area
SC integrator
7
1313© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Capacitor Mismatch Capacitor Mismatch Capacitor Mismatch
2nd-order ΣΔM
Effect on single-loop ΣΔMs:
- Ideally:
- In practice:
Slight increase of error, but shaping is preserved
1414© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Capacitor Mismatch Capacitor Mismatch Capacitor Mismatch
2-1-1 ΣΔMEffect on cascade ΣΔMs:
- Ideally:- In practice:
low-order leakages
Mismatch between analog and digital coeffs
(L1, L2, …)
8
1515© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Capacitor Mismatch Capacitor Mismatch Capacitor Mismatch Effect on cascade ΣΔMs:
2-1-1 ΣΔM(OSR = 32)
σC = 0.5%
2-1-1 ΣΔM(OSR = 32)
σC = 0.1%
1616© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Capacitor Mismatch Capacitor Mismatch Capacitor Mismatch Effect on cascade ΣΔMs:
Sensitivity to mismatch rapidly increases with:- Oversampling ratio (OSR)- Cascade order (L)
1st-stage leakages dominate (L1 shaping)
Required σC for 1-bit loss in DR
9
1717© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Integrator Incomplete Settling Integrator Incomplete Settling Integrator Incomplete Settling If only amplifier gain is considered, the relation between voand virtual ground is assumed to be independent on time
ADC GB, SR
In practice, this relation depends is non-linear on time
Integrator temporal evolutionerror due to amplifier finite bandwidthslew-rate limitation
Modulator output spectrumincrease on the noise floorharmonic distortion due to slewing
SNDR degradation
Settling error
1818© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Integrator Incomplete Settling Integrator Incomplete Settling Integrator Incomplete Settling Integrator temporal evolution: [Rio00]
Both integration and sampling dynamics considered
1 pole model + SR limitation in amplifiers
All parasitic caps taken into account
10
1919© IMSE-CNM ΣΔ Design Group
Partial slewLinear response
DTDT--ΣΔΣΔMs: Ms: Integrator Incomplete Settling Integrator Incomplete Settling Integrator Incomplete Settling
Full slew
Integrator temporal evolution: [Rio00]
GBi
SRi
2020© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Integrator Incomplete Settling Integrator Incomplete Settling Integrator Incomplete Settling Integrator temporal evolution: [Rio00]
GBi
SRi
GBs
SRs
11
2121© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Integrator Incomplete Settling Integrator Incomplete Settling Integrator Incomplete Settling Integrator temporal evolution: [Rio00]
2222© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Integrator Incomplete Settling Integrator Incomplete Settling Integrator Incomplete Settling Effect of the amplifier GB:
If only amplifier GB is considered (assuming no SR limitation)
- Can be viewed as a systematic error in the integrator weight
- Effect on ΣΔMs similar to a mismatch between analog and digital coeffs
- It causes low-order noise leakages in cascade ΣΔMs
12
2323© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Integrator Incomplete Settling Integrator Incomplete Settling Integrator Incomplete Settling
Additional effect of the amplifier SR (+ GB):
- “Dominant” linear dynamics are not mandatory in order to fulfill specs- SR can trade for GB- It can be used to optimize the power consumption of amplifiers
Non-linear dynamics cause distortion!SR at the front-end integ must be carefully tackled
2424© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Integrator Incomplete Settling Integrator Incomplete Settling Integrator Incomplete Settling Additional effect of the switches Ron (+ GB + SR):
φ = “1”
Input is sampled with an error
Linear dynamics are slowed down
Slew time shortens
13
2525© IMSE-CNM ΣΔ Design Group
Noise contribution of the switches (input-referred):
DTDT--ΣΔΣΔMs: Ms: Circuit Noise Circuit Noise Circuit Noise
Main noise sources in SC integrators:Switches Thermal noise
Amplifiers Thermal and flicker noise
References Thermal and flicker noise
Integration:Sampling:
Switches for sampling
Aliasedcomponent[Fisc82]
CS = 0.66pFfs = 70MHz
2626© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Circuit Noise Circuit Noise Circuit Noise
Noise contribution of the switches (input-referred):
Main noise sources in SC integrators:Switches Thermal noise
Amplifiers Thermal and flicker noise
References Thermal and flicker noise
Integration:Sampling:
Switches for sampling Switches for integration
14
2727© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Circuit Noise Circuit Noise Circuit Noise Noise contribution of the amplifier (input-referred):
Thermal component
Flicker component
Thermal + Flicker
corner freq.Aliased
component
Low-pass filtered version at the integ input:
Folded tails are “submerged”into the aliased thermal noise
Similar treatment for the references
2828© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Circuit Noise Circuit Noise Circuit Noise
switches amplifier references
Total noise PSD for the front-end integ:
In-band error power due to circuit noise in the ΣΔM
Switches:- kT/C is the ultimate limitation on the converter resolution- It can only be decreased by increasing Cs and/or fs (it does not depend on Ron!)- x2 in fully-diff implementations (3-dB increase, but signal power is 6dB larger!)
Amplifiers & References:- GBs should be as low as settling errors allow (reduces folding!)- 1/f contributions decrease with the corner frequency- Adequate techniques can be applied in low-freq apps: CDS, chopper, … [Enz96]
15
2929© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Circuit Noise Circuit Noise Circuit Noise
3rd-order shaping
Ideal
w/ Integ leakage
w/ Thermal noise2nd-order shaping
no shaping
Effect of noise leakages and thermal noise on a 2-1 cascade
3030© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Circuit Noise Circuit Noise Circuit Noise
Flickercomponent
(1/f)
Thermal components
Effect of 1/f and thermal noise on the spectra of a 4th-order ΣΔM
(silicon results for several fs)
Be careful with Flicker models for transistors!Front-end amplifier needed redesign!
16
3131© IMSE-CNM ΣΔ Design Group
IdealσJ = 0.1ns, fx = 125kHzσJ = 0.1ns, fx = 500kHz
DTDT--ΣΔΣΔMs: Ms: Clock Jitter Clock Jitter Clock Jitter
Sampling time uncertainty [Boser88]:
If jitter is modeled as random:
Error is larger, the larger input freq(wideband apps!)
Non-uniform sampling of the input
3232© IMSE-CNM ΣΔ Design Group
HD3 = -94.0dBHD3 = -89.9dBHD3 = -89.8dB
DTDT--ΣΔΣΔMs: Ms: NonNonNon---linearity of Capacitors linearity of Capacitors linearity of Capacitors
vi
- Even-order distortion cancels w/ fully-diff
- Non-linearity of sampling cap dominates
- Valid for weak non-linearities (MOS caps are very non-linear!)
In an ideal capacitor: dq = Cdv
In practice: dq = C(v)dv, with C being voltage-dependent
Considering the effect of the sampling cap only [Bran97]:
a1 = 500ppm/V, a2 = 500ppm/V2
17
3333© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: NonNonNon---linear Amplifier Gain linear Amplifier Gain linear Amplifier Gain
- Increasing ADC helps a lot!
- ADC at the front-end larger than noise leakages require
ADC = 500, γ1 = 10%/V (single-ended ΣΔM)
Amplifier gain, dB
Output voltage, V
ADC
Actual amplifier gain depends on output voltage:
[Yin94]
3434© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: NonNonNon---linear Settlinglinear Settlinglinear Settling
SR at the front-end larger than settling requires
SR can trade for GB in the integrator settling, but non-linear dynamics cause distortion:
18
3535© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: NonNonNon---linear Switch Resistancelinear Switch Resistancelinear Switch Resistance
|| TpV IvDDV
0 TnDD VV −
pR ,ON nR ,ON
eq,ONR
)(
1,ON
TnIDDn
n
n
VvVL
Wk'R
−−⎟⎠⎞
⎜⎝⎛
=
|)|(
1,ON
TpIp
p
p
VvL
Wk'R
−⎟⎠⎞
⎜⎝⎛
=
ON,eq ON, ON,//n pR R R=
Non-linear sampling [Geer02]:
Switches exhibit a finite RON which is also non-linear:
Alternative switch sizings
- Distortion is dynamic (increases with input freq!)- Front-end switch dominates- RON at the front-end smaller than settling requires- Very important in low-voltage!
Most suited sizing depends on parasitics, Vref/Vsupply, …
Numericallysolved
3636© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Comparators and MultiComparators and Multi--bit Quantizersbit Quantizers
Single-bit ΣΔMs: Comparator:Offset Attenuated by the integrator DC gain
Hysteresis Shaped similarly to quantization error [Boser88]
22
2 1
π4(2 +1)
L
h LP hL OSR +=
1-bit DAC Inherently linear
Multi-bit ΣΔMs:Effect of DAC errors on a 2nd-order 3-bit ΣΔM
22 2
LSB1σ INL2 2 1D B
Δ⎛ ⎞= ⎜ ⎟−⎝ ⎠
Multi-bit ADC Errors attenuated/shaped
Multi-bit DAC Non-linearity directly added to the input!
[Mede99]:DEM techniquesDual quantization
19
3737© IMSE-CNM ΣΔ Design Group
Power-down control.
DTDT--ΣΔΣΔMs: Ms: Case StudyCase StudyA case study: A 2.5-V Cascade ΣΔM in CMOS 0.25um for ADSL/ADSL+
22--11--1 w/ dual quantization1 w/ dual quantization
Two different amplifiers: 2-stage OA in the 1st stage, and 1-stage OA in 2nd and 3rd stages.
Standard CMOS switches (no clock-boosting).
Only 2-branch integrators and 2x16 unit capacitors (MiM).
Comparators: regenerative latch + preamplification stage.
3-bit quantizer in the last stage:
Resistive-ladder DAC (no calibration).
Flash ADC: Static differential input stage + latched comparators.
3838© IMSE-CNM ΣΔ Design Group
Clock jitter
Thermal noise
Quantization noise
-90.1dB
-84.8dB
-88.1dB
-82.2dB
-86.2dB
82.8dB(13.5bit)
-82.3dB
-87.5dB
-88.1dB
-96.4dB
-95.4dB
-99.8dB
-90.3dB
80.8dB(13.1bit)
Dynamic range
-80.3dBIn-band error power
-84.5dBAmplifier noise
-86.0dBkT/C noise
DAC error
-89.4dBCap. mismatch leakage(σC = 0.05% | 0.1%)
DC gain leakage
Ideal
0.5%FSDAC INL3-bit QUANTIZER
3nsResolution time
±10mVOffset
20mVHysteresis
COMPARATORS
6nV/sqrt(Hz)Input equivalent noise
±1.8VOutput swing
800V/μsSlew rate (1.5pF)
265MHzGB (1.5pF)
3000 (70dB)DC gain
AMPLIFIER
150ΩSwitch on-resistance
1%Bottom parasitic cap.
±20%Cap. tolerance
0.05%Cap. sigma (MiM, 1pF)
0.66pFSampling capacitor
FRONT-END INTEGRATOR
15ps (0.1%)Clock jitter
70.4MHzClock frequency
1.5VReference voltage
16Oversampling ratio
2-1-1(3b)
MODULATOR
TopologyBlocks SpecsBlocks Specs
EQUATION DATABASE
Corner analysis:Corner analysis:
Fast and slow devices modelsTemperature range: [-40ºC, +110ºC]±5% variation in the 2.5-V supply
TypicalWorstCase
DTDT--ΣΔΣΔMs: Ms: Case StudyCase Study
20
3939© IMSE-CNM ΣΔ Design Group
Clock jitter
Thermal noise
Quantization noise
-90.1dB
-84.8dB
-88.1dB
-82.2dB
-86.2dB
82.8dB(13.5bit)
-82.3dB
-87.5dB
-88.1dB
-96.4dB
-95.4dB
-99.8dB
-90.3dB
80.8dB(13.1bit)
Dynamic range
-80.3dBIn-band error power
-84.5dBAmplifier noise
-86.0dBkT/C noise
DAC error
-89.4dBCap. mismatch leakage(σC = 0.05% | 0.1%)
DC gain leakage
Ideal
0.5%FSDAC INL3-bit QUANTIZER
3nsResolution time
±10mVOffset
20mVHysteresis
COMPARATORS
6nV/sqrt(Hz)Input equivalent noise
±1.8VOutput swing
800V/μsSlew rate (1.5pF)
265MHzGB (1.5pF)
3000 (70dB)DC gain
AMPLIFIER
150ΩSwitch on-resistance
1%Bottom parasitic cap.
±20%Cap. tolerance
0.05%Cap. sigma (MiM, 1pF)
0.66pFSampling capacitor
FRONT-END INTEGRATOR
15ps (0.1%)Clock jitter
70.4MHzClock frequency
1.5VReference voltage
16Oversampling ratio
2-1-1(3b)
MODULATOR
Topology
TypicalWorstCase
DTDT--ΣΔΣΔMs: Ms: Case StudyCase Study
4040© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Case StudyCase Study
GB = 265MHz(assuming that 85% ofthe clock cycle is useful)
Standard switches(no clock-boosting)
GB > 2.5fs is ideally enough to limit settling errors (this architecture w/ OSR = 16).
Integrator DynamicsIntegrator Dynamics
Switch on-resistance slows down the effective amplifier response:
Ron ~ 150Ω requires just GB > 3.2fs
Slew rate must be large enough to let the linear dynamic to correctly settle.
Partially slew-rate limited operation of the front-end integrator introduces distortion.
6.5 SR = 800V/μs
21
4141© IMSE-CNM ΣΔ Design Group
OPAOPA OPBOPB
6nV/sqrt(Hz)
±1.80V
800V/μs
265MHz
3000 (70dB)
0.66pF
INTEG. 1
6nV/sqrt(Hz)
±1.80V
800V/μs
265MHz
3000 (70dB)
0.45pF0.66pF
INTEG. 2INTEG. 1
50nV/sqrt(Hz)
±1.60V
350V/μs
210MHz
600 (56dB)
0.45pF
INTEG. 4INTEG. 3
Input equivalent noise
Output swing
Slew rate (1.5pF)
GB (1.5pF)
DC gain
Unit capacitor SC CMFB netsSC CMFB nets
pMOS input schemepMOS input scheme
DTDT--ΣΔΣΔMs: Ms: Case StudyCase StudyAmplifiersAmplifiers
Cancelled body effect(substrate noise coupling)
Smaller 1/f noise
4242© IMSE-CNM ΣΔ Design Group
6nV/sqrt(Hz)
±1.80V
800V/μs
265MHz
3000 (70dB)
0.45pF0.66pF
INTEG. 2INTEG. 1
50nV/sqrt(Hz)
±1.60V
350V/μs
210MHz
600 (56dB)
0.45pF
INTEG. 4INTEG. 3
Input equivalent noise
Output swing
Slew rate (1.5pF)
GB (1.5pF)
DC gain
Unit capacitor
Power consumption
Input capacitance
Input eq. noise
Output swing
SR (1.5pF)
PM (1.5pF)
GB (1.5pF)
DC gain
19.4mW
129fF
5.5nV/sqrt(Hz)
±1.86V
883V/μs
57.9º
331.5MHz
73.5dB
17.2mW
126fF
5.1nV/sqrt(Hz)
±2.09V
1059V/μs
64.0º
446.8MHz
78.6dB
Worst CaseTypical
OPAOPA 22--stage amplifierstage amplifier Telescopic 1st stage2-path compensation
AmplifiersAmplifiers
DTDT--ΣΔΣΔMs: Ms: Case StudyCase Study
SC CMFB netsSC CMFB nets
pMOS input schemepMOS input scheme
Cancelled body effect(substrate noise coupling)
Smaller 1/f noise
22
4343© IMSE-CNM ΣΔ Design Group
6nV/sqrt(Hz)
±1.80V
800V/μs
265MHz
3000 (70dB)
0.45pF0.66pF
INTEG. 2INTEG. 1
50nV/sqrt(Hz)
±1.60V
350V/μs
210MHz
600 (56dB)
0.45pF
INTEG. 4INTEG. 3
Input equivalent noise
Output swing
Slew rate (1.5pF)
GB (1.5pF)
DC gain
Unit capacitor
Power consumption
Input capacitance
Input eq. noise
Output swing
SR (1.5pF)
PM (1.5pF)
GB (1.5pF)
DC gain
6.9mW
343fF
5.1nV/sqrt(Hz)
±1.72V
373V/μs
67.7º
331.7MHz
56.8dB
6.6mW
300fF
4.1nV/sqrt(Hz)
±1.97V
377V/μs
70.3º
393.5MHz
58.0dB
Worst CaseTypical
OPBOPB foldedfolded--cascode amplifiercascode amplifier
DTDT--ΣΔΣΔMs: Ms: Case StudyCase StudyAmplifiersAmplifiers
SC CMFB netsSC CMFB nets
pMOS input schemepMOS input scheme
Cancelled body effect(substrate noise coupling)
Smaller 1/f noise
4444© IMSE-CNM ΣΔ Design Group
Standard CMOS switches
Ron ~ 150Ω
nMOS: 8.5/0.25pMOS: 36.5/0.25
Switch onSwitch on--resistanceresistance
Slow-down of the integrators dynamics
Incomplete sampling (RC time constant)
Dynamic distortion (front-end integrator)
No clock-boostingNo low-Vt transistors
DTDT--ΣΔΣΔMs: Ms: Case StudyCase Study
23
4545© IMSE-CNM ΣΔ Design Group
0.85Vpd @ 366kHz
Sinewave inputSinewave input
Dynamic distortionDynamic distortionevaluated throughevaluated through
electrical simulationelectrical simulation
DMT inputDMT input
DTDT--ΣΔΣΔMs: Ms: Case StudyCase StudySwitch onSwitch on--resistanceresistance
4646© IMSE-CNM ΣΔ Design Group
CMOS tech with mixed-signal facilities
MiM capacitorsMiM capacitors
Also MiM caps in OPA, OPA, in the SC CMFB nets, SC CMFB nets, and in the antianti--aliasing filter aliasing filter
Integrators weights:Integrators weights:
M4
M5
M3
TOP
BOTTOM
thinoxide
Thin oxide betweenmetal 4 and metal 5
±20%Cap. spread
1%Bottom plate parasitic
0.05% (1pF)Cap. matching
Front-end integ, 0.66pF: 27μm x 27μm
Remaining integs, 0.45pF: 22μm x 22μm
Very good matching (0.1% assumed for 6-σ design)
Helps to limit the capacitive load to integrators
DTDT--ΣΔΣΔMs: Ms: Case StudyCase Study
24
4747© IMSE-CNM ΣΔ Design Group
ResistiveResistive--ladder DACladder DAC
References obtained from the on-chip analog supply
700-Ω ladder between references +2V/+0.5V (14x50Ω, 3.21mW)
Unsalicided n+ poly used in resistors
Flash ADCFlash ADC
Extra differential pair in comparators
Static input scheme (no caps)
33--bit Quantizerbit Quantizer
Reduces capacitive load to 4th integratorSaves silicon area
Power consumption
Resolution time, HL
Offset
0.3mW
2.8ns
6.3mV
100fF
3.9ns127.5μV
Input capacitance
Resolution time, LH
Hysteresis
ComparatorComparator
(Different supplies)
PrePre--amp + Regenerative latch + SR latchamp + Regenerative latch + SR latch
DTDT--ΣΔΣΔMs: Ms: Case StudyCase Study
4848© IMSE-CNM ΣΔ Design Group
Dedicated analog, mixed, and digital supplies
Layout symmetry and common-centroid techniques
Guard rings with dedicated pad/pinIncreased distance among analog and digital blocks
Shielded bus for distributing the clock signals
Extensive on-chip decoupling Pad ring divided blocking cells Multiple bonding techniques
2.78mm2.78mm22 w/o padsw/o pads
4444--pin plastic QFPpin plastic QFPCMOS 0.25CMOS 0.25μμmm
44--layer PCBlayer PCB
DTDT--ΣΔΣΔMs: Ms: Case StudyCase Study
Layout & PrototypingLayout & Prototyping
25
4949© IMSE-CNM ΣΔ Design Group
DTDT--ΣΔΣΔMs: Ms: Case StudyCase StudyExperimental resultsExperimental results
SFDR = 90dB
-6dBV @ 160kHz
THD = -87dB
Part of a commercial modem
In mass production (STMicroelectronics)
5050© IMSE-CNM ΣΔ Design Group
CT-ΣΔM Non-Idealities
Building-block Errors Architectural Timing Errors
Quantizer metastability
Excess loop delay
Clock jitter
Opamp finite (non-linear) DC gain
Integrator transientresponse
Element tolerances
Time-constant error
Non-linearity (Front-endV-I and DAC)
Noise
CTCT--ΣΔΣΔMs : Ms : Overview of CTOverview of CTOverview of CT---ΣΔΣΔΣΔM NonM NonM Non---idealities idealities idealities
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5151© IMSE-CNM ΣΔ Design Group
Basic building blocks − CT Integrators
A Gm-MC implementation
- 2nd-order single-loop ΣΔM
- 1-bit switched-current DAC
- 1-bit (latch) comparator
CTCT--ΣΔΣΔMs: Ms: Basic building blocksBasic building blocksBasic building blocks
5252© IMSE-CNM ΣΔ Design Group
Integrator Transfer Function (ITF) degraded by circuit non-idealities
CTCT--ΣΔΣΔMs: Ms: NonNonNon---ideal Integrator Transfer Functionideal Integrator Transfer Functionideal Integrator Transfer Function
27
5353© IMSE-CNM ΣΔ Design Group
Opamp finite DC gain (I)
RC integrators [Gerf03]
- Same IBN degradation as in SC ΣΔMs
CTCT--ΣΔΣΔMs: Ms: Effect of finite DC gain errorEffect of finite DC gain errorEffect of finite DC gain error
5454© IMSE-CNM ΣΔ Design Group
Opamp finite DC gain (II) – Gm-C integrators
Power Spectral Density of an Lth-order ΣΔM
Relative increase of PQ in a 2nd-order ΣΔM
CTCT--ΣΔΣΔMs: Ms: Effect of finite DC gain errorEffect of finite DC gain errorEffect of finite DC gain error
28
5555© IMSE-CNM ΣΔ Design Group
Integrator transient response (I)
Less critical than in DT ΣΔMsNeed to be taken into account, specially in broadband applications
Influence of GBW [Gerf03]
3rd-order single-loop RC CT-ΣΔM
Other dynamic effects
2nd-order polesSlew-rate
Complex analysis
Simulation-basedstudy [Ruiz03]
CTCT--ΣΔΣΔMs: Ms: Integrator transient responseIntegrator transient responseIntegrator transient response
5656© IMSE-CNM ΣΔ Design Group
Model of GBW for RC-active based CT-ΣΔMs [Ortm04]
Modeled as a gain error (GE) and extra loop delayEach delay is different for each feeback path
CTCT--ΣΔΣΔMs: Ms: Integrator transient responseIntegrator transient responseIntegrator transient response
29
5757© IMSE-CNM ΣΔ Design Group
Element tolerancesScaling coefficients accuracy limited by random errors in resistors/capacitors
Especially critical in:• High-order single-loop architectures (instability)• Cascade architectures (analog/digital coefficient ratios)
Two types of random errors:• Absolute tolerances: variations from chip to chip (10-20%)• Relative mismatches: variations from device to device on one chip (0.5-1%)
Electrical control of frequency tuning
1
1.5
2
2.5
0 0.20.40.60.81
4
6
8
10
12
14
σc(%)σgm(%)
System-level optimization and synthesis method
CTCT--ΣΔΣΔMs: Ms: Circuit element tolerancesCircuit element tolerancesCircuit element tolerances
5858© IMSE-CNM ΣΔ Design Group
Direct synthesis method of CT cascade architectures [Tort06]:
Optimum placement of poles/zeroes of the NTFSynthesis of both analog and digital part of the cascade CT ΣΔ ModulatorReduced number number of analog componentsReduced sensitivity to element tolerances
DT-to-CT
MethodDirect
Method
CTCT--ΣΔΣΔMs: Ms: Circuit element tolerancesCircuit element tolerancesCircuit element tolerances
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5959© IMSE-CNM ΣΔ Design Group
1 1.5
2 2.5
0 0.20.40.60.81
8
10
12
14
16
18
σc(%)σgm(%)
SN
R L
oss
(dB
)
1
1.5
2
2.5
0 0.20.40.60.81
4
6
8
10
12
14
σc(%)σgm(%)
Direct synthesis of cascade architectures (I) [Tort06]
Sensitivity to mismatch (gm,C)A 2-1-1 example
DT-to-CT synthesis method Direct synthesis method
CTCT--ΣΔΣΔMs: Ms: Circuit element tolerancesCircuit element tolerancesCircuit element tolerances
6060© IMSE-CNM ΣΔ Design Group
Direct synthesis of cascade architectures (II) [Tort06]
CTCT--ΣΔΣΔMs: Ms: Circuit element tolerancesCircuit element tolerancesCircuit element tolerances
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6161© IMSE-CNM ΣΔ Design Group
Synthesized cascaded CT ΣΔMs to cope with 12-bit@20-MHz
2-1-1-1 CTΣΔM 2-2-1 CTΣΔM
3-2 CTΣΔM
CTCT--ΣΔΣΔMs: Ms: Circuit element tolerancesCircuit element tolerancesCircuit element tolerances
6262© IMSE-CNM ΣΔ Design Group
A case study: A 12-bit@20MHz, 4-b, 2-1-1 CT ΣΔM (RC/Gm Integrators)
CTCT--ΣΔΣΔMs: Ms: Synthesis MethodsSynthesis MethodsSynthesis Methods
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6363© IMSE-CNM ΣΔ Design Group
Integrator time-constant error (I)
CTCT--ΣΔΣΔMs: Ms: Integrator timeIntegrator timeIntegrator time---constant errorconstant errorconstant error
6464© IMSE-CNM ΣΔ Design Group
Integrator time-constant error (II)
Optimum SNR for:
CTCT--ΣΔΣΔMs: Ms: Integrator timeIntegrator timeIntegrator time---constant errorconstant errorconstant error
33
6565© IMSE-CNM ΣΔ Design Group
Non-linearity (I): Causes
Intrinsic non-linearity of the resistor materialModulation of thickness of the conductive layer with resistor voltage
V-I transformation in RC integrators
V-I transformation in Gm-C integrators
CTCT--ΣΔΣΔMs: Ms: NonNonNon---linear errorslinear errorslinear errors
6666© IMSE-CNM ΣΔ Design Group
Non-linearity (II): Effect on Gm-C CT-ΣΔMs [Bree01]
Linearization strategies
CTCT--ΣΔΣΔMs: Ms: NonNonNon---linear errorslinear errorslinear errors
34
6767© IMSE-CNM ΣΔ Design Group
Non-linearity (III) –Commonplace architecture
RC-active front-end integratorGm-C subsequent integrators
Other sources of non-linearityMulti-bit DACsLinearity must be the same or lower than the required resolutionCorrected by same techniques as those employed in SC ΣΔMs
• DEM• Calibration
Circuit noiseDominated by noise sources from thefront-end integrator and DACFlicker noise reduced by proper sizingand/or chopper techniquesUnsampled noise – effect of samplingreduced by the loop gain
CTCT--ΣΔΣΔMs: Ms: NonNonNon---linear errorslinear errorslinear errors
6868© IMSE-CNM ΣΔ Design Group
Comparator metastability
Modeled as a jitter noise[Cher00]
Signal-dependent
Delay
Can be cancelled by usingadditiona latches [Dagh04]
CTCT--ΣΔΣΔMs: Ms: Comparator Comparator Comparator metastabilitymetastabilitymetastability
35
6969© IMSE-CNM ΣΔ Design Group
Excess loop delay (I)
Adds additional poles to STF/NTFCauses instabilityStability condition:
• 2nd-order
• Lth-order
DAC transient response delay
CTCT--ΣΔΣΔMs: Ms: Excess loop delayExcess loop delayExcess loop delay
7070© IMSE-CNM ΣΔ Design Group
Excess loop delay (II) – an example of instability
CTCT--ΣΔΣΔMs: Ms: Excess loop delayExcess loop delayExcess loop delay
36
7171© IMSE-CNM ΣΔ Design Group
Excess loop delay (III) –cancellation techniques
Extra feedback paths (DACs) with tunable gains [Cher00]Additional DAC and twolatches [Yan04]
Level trigered
Edge trigered
Y(n) (without DAC_Band latches)
DAC_B output
Y(n)
CTCT--ΣΔΣΔMs: Ms: Excess loop delayExcess loop delayExcess loop delay
7272© IMSE-CNM ΣΔ Design Group
Excess loop delay (IV) - Digital compensation [Font05]Implemented in a 3rd-order single loop architecture with 5-level quantizer
• 90nm CMOS• 74-dB SNDR-peak, 600kHz bandwidth• 6.0mW, 1.5V
Excess loop delay compensated in the digital domainHalf-a-clock-cycle delay
• Relax comparators speed• Provide maximum isolation between quantizer and DAC switch events
CTCT--ΣΔΣΔMs: Ms: Excess loop delayExcess loop delayExcess loop delay
37
7373© IMSE-CNM ΣΔ Design Group
Clock jitter (I)
S/H• Shaped by the modulator NTF• Can be neglected
DAC• Directly adds with the input• Increases the in-band noise power
DT DAC waveform CT DAC waveform
CT ΣΔMs are more sensitive toclock jitter than DT ΣΔMs
White noise model approximation (NRZ DAC) [Cher00][Zwan96]
Standard deviation of jitter error:
SNR degradation:
CTCT--ΣΔΣΔMs: Ms: Clock jitter errorClock jitter errorClock jitter error
7474© IMSE-CNM ΣΔ Design Group
Clock Jitter (II) – White noise model approximation (NRZ/RZ DAC) [Tao99a]
Bandpass CT-ΣΔMs
Lowpass CT-ΣΔMs
CTCT--ΣΔΣΔMs: Ms: Clock jitter errorClock jitter errorClock jitter error
38
7575© IMSE-CNM ΣΔ Design Group
Clock Jitter (III) – lingering effect [Olia03a]
Jitter-induced noise includes both white and shaped componentsState-space analysis of CT-ΣΔMs with RZ DAC shows that:
Multi-bit NRZ DACs
Commonly used in CT-ΣΔMs for brodband telecom applicationsLess sensitive to clock jitter
RZ DAC NRZ DAC
CTCT--ΣΔΣΔMs: Ms: Clock jitter errorClock jitter errorClock jitter error
7676© IMSE-CNM ΣΔ Design Group
- Using state-space formulation of NTF:
[Ris94]
Clock Jitter (IV) – Multi-bit NRZ DACs [Tort05]
CTCT--ΣΔΣΔMs: Ms: Clock jitter errorClock jitter errorClock jitter error
39
7777© IMSE-CNM ΣΔ Design Group
Assuming that SNRjitter is dominated by the signal-dependent term:
[Boser, JSSC, 1988]
If the modulator-dependent term dominates (single-bit quantization):
[Van der Zwan, JSSC, 1996]
CTCT--ΣΔΣΔMs: Ms: Clock jitter errorClock jitter errorClock jitter errorClock Jitter (V): Comparison of [Tort05] with previous approaches
7878© IMSE-CNM ΣΔ Design Group
Clock Jitter (VI) – Multi-bit NRZ DACs [Tort05]
Two cases:
- CTΣΔM1: B=2bit, fs=400MHz
- CTΣΔM2: B=5bit, fs=160MHz
CTΣΔM1
CTΣΔM2
CTCT--ΣΔΣΔMs: Ms: Clock jitter errorClock jitter errorClock jitter error
40
7979© IMSE-CNM ΣΔ Design Group
Clock Jitter (VII) – Compensation techniques
Multi-bit quantization (non-linear DAC)Switched-capacitor DAC [Veld03]
• Voltage-mode operation (proper for active RC integrators)• Slower than switched-current (current steering) DAC
FIRDAC to generate a multilevel signal [Putt04]
CTCT--ΣΔΣΔMs: Ms: Clock jitter errorClock jitter errorClock jitter error
8080© IMSE-CNM ΣΔ Design Group
Building-block specifications130nm mixed-signal CMOS, 1P8MCascade 3-2 multi-bit (4b) CT ΣΔMGm-C loop-filter implementationCurrent-steering feedback DACs + DEM12-bit effective resolution40MS/s output rate (20MHz bandwidth)240MHz clock frequency1.2V ± 10% analog/digital power supplyOn-chip tuning of analog componentsEstimated power consumption is 45mW
Loop-filter coefficients
A case study: A Gm-C 12-bit@20MHz, 4-b, 3-2 CT ΣΔM
CTCT--ΣΔΣΔMs: Ms: Case StudyCase StudyCase Study
41
8181© IMSE-CNM ΣΔ Design Group
Resistive source degenerated front-end transconductorLoop-filter transconductors based on quadratic term cancellation
Transistor-level performance
Transconductors
CTCT--ΣΔΣΔMs: Ms: Case StudyCase StudyCase Study
8282© IMSE-CNM ΣΔ Design Group
2 360-μA P-type gain-boosted current sources15 N-type regulated-cascode current cells
Worst-Case Transistor-level performance
Current-steering DACs
CTCT--ΣΔΣΔMs: Ms: Case StudyCase StudyCase Study
42
8383© IMSE-CNM ΣΔ Design Group
M-i-M Capacitors
Transimpedances
Loop-Filter Transconductors
Front-End Transconductors
DAC1s
DAC2sClockLatches & DEM
Quantizers
Chip implementation
CTCT--ΣΔΣΔMs: Ms: Case StudyCase StudyCase Study
8484© IMSE-CNM ΣΔ Design Group
SNDR = 75.3 dB (12.2 bits) @ 20-MHz bandwidth
Transistor-level simulation results
CTCT--ΣΔΣΔMs: Ms: Case StudyCase StudyCase Study
43
8585© IMSE-CNM ΣΔ Design Group
Low-resistive bulkMost Standard Most Standard
CMOS technologiesCMOS technologies
Epitaxial process with heavily-doped bulk
Impact of the on-chipswitching activity
The deep-substrate is a low-impedance path for injected disturbances.
Traditional layout techniques (guard rings, separation of blocks) have a limited effectiveness.
Circuits & Errors: Circuits & Errors: Layout & PrototypingLayout & PrototypingLayout & Prototyping
8686© IMSE-CNM ΣΔ Design Group
Dedicated analog and digital supplies:
- Analog core- Digital core- Digital output buffers
Open pad ring
Common-centroid layout techniques
Guard rings
Increased distance among analog and digital blocks
Circuits & Errors: Circuits & Errors: Layout & PrototypingLayout & PrototypingLayout & PrototypingTypical ΣΔM layout example
44
8787© IMSE-CNM ΣΔ Design Group
Dedicated analog, mixed, and digital supplies
Layout symmetry and common-centroid techniques
Guard rings with dedicated pad/pinIncreased distance among analog and digital blocks
Shielded bus for distributing the clock signals
Extensive on-chip decoupling Pad ring divided blocking cells Multiple bonding techniques
Circuits & Errors: Circuits & Errors: Layout & PrototypingLayout & PrototypingLayout & Prototyping
8888© IMSE-CNM ΣΔ Design Group
Dedicated analog, mixed, and digital supplies
Layout symmetry and common-centroid techniques
Guard rings with dedicated pad/pinIncreased distance among analog and digital blocks
Shielded bus for distributing the clock signals
Extensive on-chip decoupling Pad ring divided blocking cells Multiple bonding techniques
2.78mm2.78mm22 w/o padsw/o pads
4444--pin plastic QFPpin plastic QFPCMOS 0.25CMOS 0.25μμmm
44--layer PCBlayer PCB
The chip also includes other blockspertaining to the final application
PLLPLLDecimation filterDecimation filter
(2x, 4x)(2x, 4x)
(( 8, 8, 16, 16, 32)32)
Test SetTest Set--UpUp ΣΔΣΔMMPLL +PLL + ΣΔΣΔM + FilterM + Filter
Circuits & Errors: Circuits & Errors: Layout & PrototypingLayout & PrototypingLayout & Prototyping
Example: A ΣΔM in 0.25μm for ADSL/ADSL+
45
8989© IMSE-CNM ΣΔ Design Group
Circuits & Errors: Circuits & Errors: Test PCBTest PCBTest PCB
9090© IMSE-CNM ΣΔ Design Group
Circuits & Errors: Circuits & Errors: Test PCBTest PCBTest PCB
46
9191© IMSE-CNM ΣΔ Design Group
Circuits & Errors: Circuits & Errors: Chip PackageChip PackageChip Package
Double-bonding and multiple pins for supplies
Different pin assignment for analog, mixed and digital
9292© IMSE-CNM ΣΔ Design Group
Novel tech (characterization notyet confirmed by silicon results)
TwoTwo--layer PCBlayer PCB
Decoupling
Impedance termination
Soldered samples
Anti-aliasing filter
Independent control of amplifier bias currentsIndependent control of amplifier bias currents
Low-distortionsignal generator
Digital test unit
WorkstationWorkstation
PCBPCB clocksupply, reference
input bit streams
bit streams
Test SetTest Set--UpUpCancellation logic64k-sample FFT
(in order to avoid socket parasitics)
(passive, 1st order)
Circuits & Errors: Circuits & Errors: Test SetTest SetTest Set---upupup
47
9393© IMSE-CNM ΣΔ Design Group
[Boser88] B.E. Boser and B.A. Wooley, “The Design of Sigma-Delta Modulation Analog-to-Digital Converters”. IEEE Journal of Solid-State Circuits, vol. 23. pp. 1298-1308, December 1988.
[Bran97] B. Brandt, P.F. Ferguson, and M. Rebeschini, “Analog Circuit Design of ΣΔ ADCs”, Chapter 11 in Delta-Sigma Data Converters: Theory, Design and Simulation (S.R. Norsworthy, R. Schreier, and G.C. Temes, Editors).IEEE Press, 1997.
[Enz96] C.C. Enz and G.C. Temes, “Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization”. Proceedings of the IEEE, vol. 84, no. 11, pp. 1584-1614, November 1996.
[Fisc82] J.H. Fischer, “Noise Sources and Calculation Techniques for Switched Capacitor Filters”. IEEE Journal of Solid-State Circuits, vol. 17, no. 4, pp. 742-752, August 1982.
[Geer02] Y. Geerts, M. Steyaert, and W. Sansen, Design of Multi-Bit Delta-Sigma A/D Converters. Kluwer Academic Publishers, 2002.
[Mede99] F. Medeiro, B. Pérez-Verdú, and A. Rodríguez-Vázquez, Top-Down Design of High-Performance Modulators. Kluwer Academic Publishers, 1999.
[Rio00] R. del Río, F. Medeiro, B. Pérez-Verdú, and A. Rodríguez-Vázquez, “Reliable Analysis of Settling Errors in SC Integrators: Application to ΣΔ Modulators”. IEE Electronics Letters, vol. 36, no. 6, pp. 503-504, March 2000.
[Yin94] G. Yin and W. Sansen, “A High-Frequency and High-Resolution Fourth-Order ΣΔ A/D Converter in BiCMOS Technology”. IEEE Journal of Solid-State Circuits, vol. 29, pp. 857-865, August 1994.
More details on errors and case study …[Rio06] R. del Río, F. Medeiro, B. Pérez-Verdú, J.M. de la Rosa, and A. Rodríguez-Vázquez, CMOS Cascade Sigma-
Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design. Springer, 2006.
DTDT--ΣΔΣΔMs: Ms: ReferencesReferencesReferences
9494© IMSE-CNM ΣΔ Design Group
[Bree00] L.J. Breems, E.J. Van der Zwan and J. Huijsing, “A 1.8-mW CMOS ΣΔ Modulator with Integrated Mixer forA/D Conversion of IF Signals”. IEEE Journal of Solid-State Circuits, Vol. 35, pp. 468-475, April 2000.
[Bree01] L. Breems and J.H. Huijsing, Continuous-Time Sigma-Delta Modulation for A/D Conversion in Radio Receivers. Kluwer Academic Publishers, 2001.
[Cher00] J.A. Cherry and W.M. Snelgrove, Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion. Kluwer Academic Publishers, 2000.
[Font05] P. Fontaine, A. N. Mohieldin and A. Bellaourar, “A Low-Noise Low-Voltage CT ΔΣ Modulator with Digital Compensation of Excess Loop Delay”. Proc. of the 2005 IEEE Int. Solid-State Circuits Conf., pp. 498-499, 2005.
[Gerf03] F. Gerfers, M. Ortmanns and Y. Manoli, “A 1.5-V 12-bit Power-Efficient Continuous-Time Third-Order ΣΔModulator”. IEEE Journal of Solid-State Circuits, Vol. 38, pp. 1343-1352, August 2003.
[Olia03a] O. Olieai, “State-Space Analysis of Clock Jitter in Continuous-Time Oversampling Data Converters”. IEEE Transactions on Circuits and Systems I, Vol. 50, pp. 31-37, January 2003.
[Olia03b] O. Olieai, “Design of Continuous-Time Sigma-Delta Modulators With Arbitrary Feedback Waveform”. IEEE Transactions on Circuits and Systems II, Vol. 50, pp. 437-444, August 2003.
[Ortm01] M. Ortmanns, F. Gerfers, and Y. Manoli, “On the synthesis of cascaded continuous-time Sigma-Delta modulators”. Proc. of the 2001 IEEE Int. Symp. on Circuits and Systems, Vol. 5, pp. 419-422, May 2001.
[Ortm04] M. Ortmanns, F. Gerfers and Y. Manoli, “Compensation of Finite Gain-Bandwidth Induced Errors in Continuous-Time Sigma-Delta Modulators”. IEEE Transactions on Circuits and Systems I, Vol. 51, pp. 1088-1099, June 2004.
[Ortm05] M. Ortmanns, F. Gerfers and Y. Manoli: “A Case Study on 2-1-1 Cascaded Continuous-Time Sigma-Delta Modulators”. IEEE Transactions on Circuits and Systems I, Vol. 52, pp. 1515-1525, August 2005.
CTCT--ΣΔΣΔMs: Ms: ReferencesReferencesReferences
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9595© IMSE-CNM ΣΔ Design Group
[Tao99a] H. Tao, L. Toth and M. Khoury, “Analysis of Timing Jitter in Bandpass Sigma-Delta Modulators”. IEEE Transactions on Circuits and Systems I, Vol. 46, pp. 991-1001, August 1999.
[Tao99b] H. Tao and J.M. Khoury, “A 400MS/s Frequency Translating BandPass Delta-Sigma Modulator”. IEEE Journalof Solid-State Circuits, Vol. 34, pp. 1741-1752, December 1999.
[Tort05] R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández, “Analysis of Clock Jitter Error in Multibit Continuous-Time ΣΔ Modulators with NRZ Feedback Waveform”. Proc. Of the 2005 Int. Symposiumon Circuits and Systems (ISCAS), May 2005.
[Tort06] R. Tortosa, J.M. de la Rosa, F.V. Fernández and A. Rodríguez-Vázquez: “A New High-Level SynthesisMethodology of Cascaded Continuous-Time Sigma-Delta modulators”. IEEE Trans. On Circuits andSystems – II: Express Briefs, pp. 739-743, August 2006.
[Tort07] R. Tortosa, A. Aceituno, J.M. de la Rosa, F.V. Fernández and A. Rodríguez-Vázquez: “A 12-bit@40Ms/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator”. Proc. Of the 2007 Int. Symposium on Circuitsand Systems (ISCAS), May 2007.
[Yan04] S. Yan and E. Sánchez-Sinencio, “A Continuous-Time ΣΔ Modulator With 88-dB Dynamic Range and 1.1-MHz Signal Bandwidth”. IEEE Journal of Solid-State Circuits, pp. 75-86, January 2004.
CTCT--ΣΔΣΔMs: Ms: ReferencesReferencesReferences