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Soft errors in adder circuitsSoft errors in adder circuits
Rajaraman Ramanarayanan, Mary Jane Irwin, Vijaykrishnan Narayanan, Yuan
XiePenn State University
Kerry BernsteinIBM
Ramanarayanan 177/MAPLD ‘04
Talk OverviewTalk Overview
Introduction
Soft errors Introduction Impact on data-path circuits Modeling soft errors in logic circuits
Experimental setup and methodology Error injection mechanism Adder circuits considered Methodology
Results
Conclusions and Future work (Lessons learned)
Ramanarayanan 177/MAPLD ‘04
Talk OverviewTalk Overview
Introduction
Soft errorsSoft errors IntroductionIntroduction Impact on data-path circuitsImpact on data-path circuits Modeling soft errors in logic circuitsModeling soft errors in logic circuits
Experimental setup and methodologyExperimental setup and methodology Error injection mechanismError injection mechanism Adder circuits consideredAdder circuits considered MethodologyMethodology
ResultsResults
Conclusions and Future work (Lessons learned)Conclusions and Future work (Lessons learned)
Ramanarayanan 177/MAPLD ‘04
IntroductionIntroduction
Soft errors, which are transient errors caused due to external radiations, affected mainly memory circuits.
Soft error rates (SER) in data-path structures and combinational logic have been increasing due to: Continuous device scaling. Voltage scaling and increased speed. increasing pipeline lengths.
Ramanarayanan 177/MAPLD ‘04
IntroductionIntroduction
Adder circuits form an integral part of data-path.
Hence, in this work, we Analyze SER in different types of adder
circuits. Analyze the effect of voltage and
frequency scaling on SER. Experimented techniques to improve
the error rates in adder circuits based on above results.
Ramanarayanan 177/MAPLD ‘04
Talk OverviewTalk Overview
IntroductionIntroduction
Soft errors Introduction Impact on data-path circuits Modeling Soft errors in logic circuits
Experimental setup and methodologyExperimental setup and methodology Error injection mechanismError injection mechanism Adder circuits consideredAdder circuits considered MethodologyMethodology
ResultsResults
Conclusions and Future work (Lessons learned)Conclusions and Future work (Lessons learned)
Ramanarayanan 177/MAPLD ‘04
Soft errors - IntroductionSoft errors - Introduction
Soft errors or transient errors are circuit errors caused due to excess charge carriers induced primarily by external radiations.
These errors cause an upset event but the circuit it self is not damaged.
Ramanarayanan 177/MAPLD ‘04
Soft errors - Impact on data-path circuitsSoft errors - Impact on data-path circuits
In data-path circuits, an error is caused when the pulse generated by a particle is latched on at the output by a flip-flop.
Here, the critical charge (Qcritical), can be defined, as the minimum charge required to latch on to the pulse.
There are three masking effects in combinational circuits that affect the propagation of any given pulse: Logical masking Electrical masking Latching window masking
Ramanarayanan 177/MAPLD ‘04
REGISTERS
I1
I2
I3
I4
I5
I6
I7C
E
D
B
REGISTERS
O2
O1
1
1
1
0
1
0
10
Soft error
No Soft error
Particle strike
Effect of electrical masking
Masking effects in data-pathMasking effects in data-path
Ramanarayanan 177/MAPLD ‘04
Modeling soft errorsModeling soft errors
*Courtesy - K. Bernstein
*
Simulated 150 MEV Proton-induced charge collection for 90 nm and 130 nm bulk technologies; per-bit SER per unit collection
Ramanarayanan 177/MAPLD ‘04
Modeling soft error in logic circuitsModeling soft error in logic circuits
Massengill et al. developed a model for a tool, which would predict the probability of an error occurring in a given combinational circuit.
Probability that a random particle hit (resulting in a current pulse) at a node N in a clock cycle C will be latched on by the output latch or flip-flop (PSF
C,N).
Probability of soft errors occurring in a given circuit can be determined using the above probability.
Ramanarayanan 177/MAPLD ‘04
Modeling soft error in logic circuitsModeling soft error in logic circuits
In this work, we propose a model that can accurately models the above probability.
We borrow the term “Timing Vulnerability” defined in the work by S. Mukherjee et al. This is defined as the fraction of time in a
clock cycle in which a given node in a circuit is vulnerable (tv).
For example, a latch has a tv of 50%.
Thus, PSFC,N = ∑ PQcoll * tv , where PQcoll is the
collected charge at a given node.
Ramanarayanan 177/MAPLD ‘04
Talk OverviewTalk Overview
IntroductionIntroduction
Soft errorsSoft errors IntroductionIntroduction Impact on in data-path circuitsImpact on in data-path circuits Modeling Soft errors in logic circuitsModeling Soft errors in logic circuits
Experimental setup and methodology Error injection mechanism Adder circuits considered Methodology
ResultsResults
Conclusions and Future work (Lessons learned)Conclusions and Future work (Lessons learned)
Ramanarayanan 177/MAPLD ‘04
Error injection mechanismError injection mechanism
Based on the models provided by previous works, We modeled our current pulse as an
exponential wave form with a pulse width of 50 ps in our HSPICE simulations.
Charge colleted at a node can be determined using the following expression: Q = ∫ Id dt, where Id =Drain Current.
Ramanarayanan 177/MAPLD ‘04
Adder Designs ConsideredAdder Designs Considered
€ €
€ €
P0,G0 P1,G1 P2,G2 P3,G3
S0 S1 S2 S3
€ €
€
P0,G0 P1,G1 P2,G2 P3,G3
S0 S1 S2 S3
€
€
(a) Brent-kung (B-K) (b) Kogge-stone (K-S)
C0 C1 C2 C3P3P2P1P0
C0 C1 C2 C3P3P2P1P0
Ramanarayanan 177/MAPLD ‘04
MethodologyMethodology
Our analysis consists of: Measuring Qcritical at different nodes affecting
different outputs in B-K adders. Comparing B-K with K-S and Ripple Carry (RC)
adders. Measuring Qcritical and tv after scaling voltage and
frequency.
Next we consider techniques to improve the above two quantities to increase the robustness of adders: Use a Flip-Flop with better tv values.
Using a Semi-dynamic Flip-Flop (SDFF) instead of a Transmission gate Flip-Flop (TGFF) used initially.
Increase threshold voltage, which increases Qcritical.
All circuits were custom designed and laid out in 70nm technology.
Ramanarayanan 177/MAPLD ‘04
Talk OverviewTalk Overview
IntroductionIntroduction
Soft errorsSoft errors IntroductionIntroduction Impact on data-path circuitsImpact on data-path circuits Modeling Soft errors in logic circuitsModeling Soft errors in logic circuits
Experimental setup and methodologyExperimental setup and methodology Error injection mechanismError injection mechanism Adder circuits consideredAdder circuits considered MethodologyMethodology
Results
Conclusions and Future work (Lessons learned)Conclusions and Future work (Lessons learned)
Ramanarayanan 177/MAPLD ‘04
Qcritical for B-K, K-S and RC addersQcritical for B-K, K-S and RC adders
1.00E-20
1.00E-19
1.00E-18
1.00E-17
1.00E-16
1.00E-15
1.00E-14
1.00E-13
1.00E-12
S1
S2
S3
S2
& S
3
S1
& S
2
S1,
S2
& S
3
S1
S2
S3
S2
& S
3
S2
S3
S2
& S
3
S2
S3
S3
C0 P1 C1 G1 G2
Pulse at nodes and outputs affected
Qcr
itic
al
BK
KS
RC
Ramanarayanan 177/MAPLD ‘04
Results – B-K addersResults – B-K adders
For B-K adders (at node C0): Qcritical’s for a node to cause a flip at all the sum
outputs are similar. Qcritical for all outputs flipping together is
higher.
Ramanarayanan 177/MAPLD ‘04
Adder comparisonsAdder comparisons
For B-K and K-S, Qcritical at a node for flipping different outputs are comparable while RC has progressively increasing Qcritical.
Qcritical is smaller in K-S adders due to shortest path carry chains.
Also KS adders have greater area susceptible to soft errors due to larger number of carry cells.
B-K adder has more nodes that fan’s out equally to many outputs Hence, a single particle strike at a node can
cause multi-bit errors.
Ramanarayanan 177/MAPLD ‘04
Voltage and frequency scalingVoltage and frequency scaling
1.00E-21
1.00E-20
1.00E-19
S1
, C0
S2
, C0
S3
, C0
S2
& S
3, C
0
S1
& S
2, C
0
S1
,S2
& S
3, C
0
S1
, P1
S2
, P1
S3
, P1
S2
& S
3, P
1
S2
, C1
S3
, C1
S2
& S
3, C
1
nodes
Qc
riti
ca
l (C
)
1V, 1 GHz 0.8V, 0.833GHz 0.6V, 0.5 GHz
Ramanarayanan 177/MAPLD ‘04
Voltage and Frequency scalingVoltage and Frequency scaling
The adders were run at 1 GHz, 0.833GHz and 0.5 GHz with 1V, 0.8 V and 0.6V as supply voltages respectively.
As both voltage and frequency are scaled, Qcritical reduces slightly at many nodes.
Reducing frequency reduces tv, but reduction in Qcritical plays a much important role.
Ramanarayanan 177/MAPLD ‘04
Optimization TechniquesOptimization Techniques
Using Flip-Flop with lesser set-up and hold time (SDFF) Improves timing vulnerability.
Also improves Qcritical for multi-bit errors.
Increasing threshold voltage Increases Qcritical as it increases the gain
of the logic circuit. But it increases the timing vulnerability
also.
Ramanarayanan 177/MAPLD ‘04
Conclusions and lessons learntConclusions and lessons learnt
The timing vulnerability determines the occurrences of multi-bit errors in adders.
Trade-offs have to be considered in using different type of adders. K-S adders have lesser Qcritical and higher soft
error rate. Multi-bit errors can be more common in B-K
adders
Voltage and frequency scaling worsens the soft error rate.
Techniques to improve Qcritical and tv were presented. Trade-offs in choosing these techniques.
Ramanarayanan 177/MAPLD ‘04
ReferencesReferences
L. W. Massengill, A. E. Baranski, D. O. V. Nort, J. Meng, and B. L. Bhuva. Analysis of Single-Event Effects in Combinational Logic – Simulation of the AM2901 Bitslice Processor. IEEE Trans. on Nuclear Science, 47(6):2609–2615, December 2000.
S. K. Reinhardt and S. Mukherjee. Transient Fault Detection via Simultaneous Multithreading. International Symposium on Computer Architecture, pages 25–36, July 2000.