Chapter 9 -- Simplification of Sequential Circuits

Chapter 9 -- Simplification of Sequential Circuits

Redundant States in Sequential Circuits

Removal of redundant states is important because– Cost: the number of memory elements is directly related to the

number of states

– Complexity: the more states the circuit contains, the more complex the design and implementation becomes

– Aids failure analysis: diagnostic routines are often predicated on the assumption that no redundant states exist

Equivalent States

• States S1, S2, …, Sj of a completely specified sequential circuit are said to be equivalent if and only if, for every possible input sequence, the same output sequence is produced by the circuit regardless of whether S1, S2, …, Sj is the initial state.

• Let Si and Sj be states of a completely specified sequential circuit. Let Sk and Sl be the next states of Si and Sj, respectively for input Ip.

Si and Sj are equivalent if and only if for every possible Ip the following are conditions are satisfied.– The outputs produced by Si and Sj are the same,

– The next states Sk and Sl are equivalent.

Equivalent States Illustration

S C

In itia lS ta te

zx

(d )

ABCDE

In p u t S eq u en ces0 0 0 0 0 1 0 1 0 0 11 1 0 0 1 0 1 11 0 11 1

11 111 111 10 0 00 0 0

11 011 011 00 0 10 0 1

1 0 01 0 01 0 00 110 11

1 0 11 0 11 0 10 1 00 1 0

0 110 0 00 0 011 111 1

0 1 00 0 10 0 111 011 0

0 0 00 110 111 0 01 0 1

0 0 10 1 00 1 01 0 11 0 0

(a )

(b )

0 1x

A

B

C

D

E

C /1

C /1

B /1

D /0

E /0

B /0

E /0

E /0

B /1

A /1

(c)

1111110 00 0

1 01 01 00 10 1

0 10 00 01111

0 00 10 11 01 0

ABCDE

In itia lS ta te

In p u t S eq u en ces0 0 0 1 1 011

Figure 9.1

Equivalence Relations

• Equivalence relation: let R be a relation on a set S. R is an equivalence relation on S if and only if it is reflexive, symmetric, and transitive. An equivalence relation on a set partitions the set into disjoint equivalence classes.

• Example: let S = {A,B,C,D,E,F,G,H} and R = {(A,A),(B,B),(B,H),(C,C),(D,D),(D,E),(E,E),(E,D),(F,F),(G,G),(H,H),

(H,B)}. Then P = (A)(BH)(C)(DE)(F)(G)

• Theorem: state equivalence in a sequential circuit is an equivalence relation on the set of states.

• Theorem: the equivalence classes defined by the state equivalence of a sequential circuit can be used as the states in an equivalent circuit.

Methods for Finding Equivalent States

• Inspection

• Partitioning

• Implication Tables

Finding Equivalent States By Inspection

0 1x

(a )

A

B

C

D

B /0

C /0

D /1

C /0

C /1

A /1

B /0

A /1

0 1x

(b )

A

B

C

B /0

C /0

B /1

C /1

A /1

B /0

0 1x

(c)

A

B

C

D

B /0

B /0

D /1

D /0

C /1

A /1B /0A /1

0 1x

(d )

A

B

C

B /0B /0B /1

C /1

A /1

B /0

0 1x

(e)

A

B

C

D

B /0

D /0

D /1B /0

C /1A /1B /0A /1

Figure 9.2

Finding Equivalent States by Partitioning

Partition blocks ActionPartition P0

Output for x = 0

Output for x = 1

Partition P1

Next state for x = 0


Partition P2



Partition P3



Partition P4 = P3

(ABCDE)1110000011

Separate (ABC) and (DE)Separate (ABC) and (DE)

(ABC)CCBBEE Separate (A) and (BC)

Separate (D) and (E)(BC)CBEE

(DE)DEBA

(A)CB

(BC)CBEE

(D)DB

(E)EA

States B and C are equivalent

(A)CB

(DE)DEBA

(BC)(A) (D) (E)

Figure 9.3

Example 9.2 -- Partitioning example

(a)

(b)

x0 1

E/0

A/1

C/0

B/0

D/1

C/0

H/1

C/1

D/0

F/0

A/1

A/0

C/0

D/1

G/1

B/1

A'

B'

C'

D'

E'

B'/0

A'/1

C'/0

E'/1

C'/1

A'/0

C'/0

A'/1

D'/1

B'/1

0 1xA

B

C

D

E

F

G

H

Figure 9.4

Example 9.3 -- Another partitioning example

(a)

(b)

x0 1

A/0

H/1

E/0

C/1

C/1

F/1

B/0

H/1

B/0

C/0

B/0

D/0

E/0

G/1

F/0

C/0

A'

B'

C'

D'

E'

F'

A'/0

B'/1

F'/0

E'/0

E'/1

C'/1

E'/0

D'/1

E'/0

B'/0

C'/0

F'/0

0 1x

A

B

C

D

E

F

G

H

Figure 9.5

Example 9.4 -- Yet another partitioning example

(a)

(b)

x1x200 01

D/0

C/1

C/1

D/0

C/1

D/0

G/0

B/1

D/0

D/0

D/0

B/0

F/0

D/0

G/0

D/0

A'

B'

C'

D'

E'

C'/0

B'/1

C'/0

B'/1

E'/0

C'/0

C'/0

B'/0

A'/0

E'/0

00 01x1x2A

B

C

D

E

F

G

H

11 10

11 10F/0

E/1

E/1

A/0

E/1

A/0

A/0

E/1

A/0

F/0

A/0

F/0

A/0

F/0

A/0

A/0

A'/0

D'/1

A'/0

D'/1

A'/0

A'/0

A'/0

A'/0

A'/0

A'/0

Figure 9.6

Finding Equivalent States by Implication Tables

Figure 9.7

(b )

B

C

D

E

B C DA

(a )

0 1x

A

B

C

D

E

C /1

C /1

B /1

D /0

E /0

B /0

E /0

E /0

B /1

A /1

(c )

B

C

D

E

B C DA

(d )

B

C

D

E

B E

B CB E

A B

B C DA

(e )

(f)

B

C

D

E

ABCD

B E

-(B C )

--

P K = (A )(B C )(D )(E )

B CB E

A B

B C DA

Example 9.5 -- Using implication tables to find equivalent states

(b )

(c )

B

C

D

E

ABCDEFG

(A D )(B E )(C F )

----

P K = (A D )(B E )(C F )(G )(H )

B E

C H

B C DA

(a )

0 1x

A

B

C

D

E

F

G

H

E /0

A /1

C /0

B /0

D /1

C /0

H /1

C /1

D /0

F /0

A /1

A /0

C /0

D /1

G /1

B /1

A D

A DC F

B G

F GE

F

G

H

Figure 9.8

Example 9.6 -- An implication table example

(b )

B

C

D

E

ABCDEFG

(A F )(B C )(B H )(C H )----

N o te : (B C )(B H )(C H ) = (B C H )

B D

B C

B C DA

(a )

0 0 0 1x 1x 2

A

B

C

D

E

F

G

H

D /0

C /1

C /1

D /0

C /1

D /0

G /0

B /1

D /0

D /0

D /0

B /0

F /0

D /0

G /0

D /0

B D

A F

D F

D F

F GE

F

G

H

11 1 0

F /0

E /1

E /1

A /0

E /1

A /0

A /0

E /1

A /0

F /0

A /0

F /0

A /0

F /0

A /0

A /0

A F

D F

D G

A F

B G

A F

D G

A F

A FB C B C

(c )

P K = (A F )(B C H )(D )(E )(G )

A F

Incompletely Specified Circuits

• Next states and/or outputs are not specified for all states

• Applicable input sequences: an input sequence is applicable to state, Si, of an incompletely specified circuit if and only if when the circuit is in state Si and the input sequence is applied, all next states are specified except for possible the last input of the sequence.

• Compatible states: two states Si and Sj are compatible if and only if for each input sequence applicable to both states the same output sequence will be produced when the outputs are specified.

• Compatible states: two states Si and Sj are compatible if and only if the following conditions are satisfied for any possible input Ip

– The outputs produced by Si and Sj are the same, when both are specified

– The next states Sk and Sl are compatible, when both are specified.

• Incompatible states: two states are said to be incompatible if they are not compatible.

Compatibility Relations

• Compatibility relation: let R be a relation on a set S. R is a compatibility relation on S if and only if it is reflexive and symmetric. A compatibility relation on a set partitions the set into compatibility classes. They are typically not disjoint.

• Example: let S = {A,B,C,D,E} and

R = {A,A),(B,B),(C,C),(D,D),(E,E),(A,B),(B,A),(A,C),(C,A), (A,D), (D,A),(A,E),(E,A),(B,D),(D,B),(C,D),(D,C),(C,E),(E,C)}

Then the compatibility classes are (AB)(AC)(AD)(AE)(BD)(CD)(CE)(ABD)(ACD)(ACE)

The incompatibility classes are (BC)(BE)(DE)

• Compatible pairs may be found using implication tables

• Maximal compatibles may be found using merger diagrams

Examples 9.8 and 9.9 -- Generating Maximal Compatibles and Incompatibles

(c )

GFEEDCCBAAA

(G H )(G H )(F G )(E G )(E H )(G H )(F G )(F G )(E G H )(D G )(F G )(E G H )(C G )(C F )(C E )(C D )(D G )(F G )(E G H )(C E G )(C D G )(C F G )(E G H )(B C )(B G )(C E G )(C D G )(C F G )(E G H )(A E )(A G )(A H )(B C )(B G )(C E G )(C D G )(C F G )(E G H )(A E G )(A G H )(A E H )(B C G )(C E G )(C D G )(C F G )(E G H )(A E G H )(B C G )(C D G )(C E G )(C F G )

GFEDDCBBBAA

-(F H )(F H )(E F )(F H )(E F )(D H )(D F )(D E )(F H )(D H )(D E F )(C H )(F H )(D H )(D E F )(B H )(B F )(B E )(B D )(C H )(F H )(D H )(D E F )(B H )(B D E F )(C H )(F H )(D H )(B D E F )(C H )(B D F H )(A B )(A C )(A D )(A F )(B D E F )(C H )(B D F H )(A B D F )(A C )(B D E F )(C H )(B D F H )

(d )(b )

B

C

D

E

A C

B C DA

C D

A C

A B

F GE

F

G

H

A G

C D

A C

B GA E

B C

A CC GC E

A C

A C

A D B D D GA E A C

A DA C

C G A G E G C G A GC G

D GA G

A D G H

D E

C H

C D

D H

A DC D D GA H(a )

0 1x

A

B

C

D

E

F

G

H

A /-

B /-

G /-

C /1

A /1

D /-

G /-

H /-

C /1

A /-

E /0

C /-

C /-

A /-

G /-

D /-

Merger diagrams

B

CA

(a ) (b )

(c ) (d )

A

B

D

C

A

E

C

D

B

B

A

D

E

C

F

Figure 9.11

Example 9.10 -- Merger diagrams for example 9.8

(b)

A

H

B

G

C

F

D

E

(a)

A

H

B

G

C

F

D

E

Figure 9.12

Minimization Procedure

Select a set of compatibility classes so that the following conditions are satisfied

• Completeness: all states of the original machine must be covered

• Consistency: the chosen set of compatibility classes must be closed

• Minimality: the smallest number of compatibility classes is used

Bounding the number of states

• Let U be the upper bound on the number of states needed in the minimized circuit

• Then U = minimum (NSMC, NSOC)– where NSMC = the number of sets of maximal compatibles

– and NSOC = the number of states in the original circuit

• Let L be the lower bound on the number of states needed in the minimized circuit

• Then L = maximum(NSMI1, NSMI2,…, NSMIi)

– where NSMIi = the number of states in the ith group of the set of maximal incompatibles of the original circuit.

State Reduction Algorithm

• Step 1 -- find the maximal compatibles

• Step 2 -- find the maximal incompatibles

• Step 3 -- Find the upper and lower bounds on the number of states needed

• Step 4 -- Find a set of compatibility classes that is complete, consistent, and minimal

• Step 5 -- Produce the minimum state table

Example 9.11 -- Reduced state table corresponding to example 9.8

(a) (b)

AGH

BG

CG

DG

AG

CDG

AEG

CEG

AEG

CEG

(AEGH)

(BCG)

(CDG)

(CFG)

(CEG)

x0 1

A'/1

B'/-

B', C', D', E'/1

A'/1

C'/-

C'/1

A'/0

D'/0

D'/0

A'/0

A'

B'

C'

D'

E'

x0 1

Figure 9.13

Example 9.12 -- State reduction problem

(d )

A

E

C

D

B

(c )

A

E

C

D

B

(b )

B

B C DA

C

D

E

A C

A D

B CA D

x0 1

(a)

A

B

C

D

E

x0 1 x

0 1

A /-

C /1

D /0

-/-

A /0

-/-

B /0

-/1

B /-

C /1

(e )

(A B D )

(A C D )

(A C E )

A C

A D

A D

B

B

C(f)

A '

B '

B '/1

A '/0

A '/0

B '/1

Figure 9.14

Example 9.13 -- Another state table reduction problem

(b )

B

B C DA

C

D

E

B D

B D

x0 1

(a)

A

B

C

D

E

F

B /1

-/-

E /0

B /1

-/-

-/0

D /0

B /0

D /-

A /0

C /1

E /1

A B

C D

D E C E

E

F

x0 1

(d )

(A B D )

(B C )

(E )

(F )

B

E

-

-

A B D

B D

C

E

(c )

B

A

D

E

C

F

(e )

B

A

D

E

C

F

x0 1

(f)

A '

B '

C '

D '

A ', B '/1

C '/0

-/-

-/0

A '/0

A '/0

B '/1

C '/1

Figure 9.15

Example 9.14 -- Yet another state reduction problem

(b )B C DA

B

C

D

x0 1

(a)

A

B

C

D

E

D /-

E /0

D /0

C /-

C /1

A /-

A /-

B /-

C /-

B /-

D E

B C

B CE

A B

A CC D

A BC D

A BD E

A C

C E

(d )

A

E

C

D

B

(c )

A

E

C

D

B

0 1

(f)

(A B C )

(A C D )

(A D E )

D E

C D

C D

x

A B

A B C

A B C

0 1

(A B C )

(D E )

D E

C

x

A B

B C

0 1

A '

B '

B '/0

A '/1

x

A '/-

A '/-

(g )(e )

Figure 9.16

Example 9.15 -- Optimal state assignments

x0 1

A

B

C

D

E

F

G

B/0

C/0

D/0

A/1

G/0

A/0

F/0

E/0

G/0

F/0

A/0

C/0

A/1

D/0

Presentstate

Next state/output

Figure 9.17

Unique State Assignments for Four States

x0 1

A

B

C

D

A/0

A/0

C/0

C/1

B/0

C/0

D/0

A/0

Presentstate

States

Assignments

1 2 3

ABCD

00011110

10110100

00101101

y1 y2

(a) (b)

y1 y2 y1 y2

Figure 9.18

State Assignments for a Four State Machine

x0 1

A

B

C

D

C/0

C/0

B/0

A/1

D/0

A/0

D/0

B/1

Figure 9.19

D flip-flop realization for assignment 1

y 2 y 1

x

0

0 1

0 0

0 1

1 1

1 0

0

0 0

0 0

1 1

(b ) (c ) (d )

Y 2 Y 1 /z

y 1

y 2

z

x

y 2 y 1

x

1

0 1

0 0

0 1

1 1

1 0

1

1 0

0 1

0 0

y 1

y 2

D 2

x

y 2 y 1

x

1

0 1

0 0

0 1

1 1

1 0

0

1 0

1 0

0 1

y 1

y 2

D 1

x

(a )

y 2y 1 0 1x

0 0

0 1

1 1

1 0

11 /0

11 /0

0 1 /0

0 0 /1

1 0 /0

0 0 /0

1 0 /0

0 1 /1

Figure 9.20


y 2 y 1

x

0

0 1

0 0

0 1

11

1 0

0

0 0

0 0

1 1

(b ) (c ) (d )

Y 2 Y 1 /z

y 1

y 2

z

x

y 2 y 1

x

0

0 1

0 0

0 1

11

1 0

1

1 1

0 0

0 1

y 1

y 2

D 2

x

y 2 y 1

x

1

0 1

0 0

0 1

11

1 0

0

1 0

1 0

0 1

y 1

y 2

D 1

x

(a )

y 2y 1 0 1x

0 0

0 1

11

1 0

0 1 /0

11 /0

0 1 /0

0 0 /1

1 0 /0

1 0 /0

0 0 /0

11 /1

Figure 9.21


y 2 y 1

x

0

0 1

0 0

0 1

11

1 0

0

0 0

1 1

0 0

(b ) (c ) (d )

Y 2 Y 1 /z

y 1

y 2

z

x

y 2 y 1

x

0

0 1

0 0

0 1

11

1 0

1

1 1

0 1

0 0

D 2

x x

1

0 1

0 0

0 1

11

1 0

1

0 1

0 0

1 0

D 1

x

(a )

y 2y 1 0 1x

0 0

0 1

11

1 0

0 1 /0

1 0 /0

0 0 /1

0 1 /0

11 /0

11 /0

1 0 /1

0 0 /0

y 2 y 1

y 2 y 2

y 1y 1

Figure 9.22

State adjacencies for four-state assignments

(a)

0 1

0

1

(b) (c)

A

B

D

C

y1 0 1

0

1

A

C

D

B

0 1

0

1

A

C

B

D

y2y1

y1

y2y2

Figure 9.23

Assignment 1 Assignment 2 Assignment 3

Example 9.18 -- Implication Graphs

x0 1

(a)

(b )

B D A B A C C D A D B C

B /0

D /0

A /1

D /1

C /0

A /1

D /0

B /1

A

B

C

D

Figure 9.24

Example 9.19 -- Closed subgraphs

x0 1

(a)

B /0

C /1

B /0

A /0

B /1

E /0

D /1

A /0

D /0

A /1

A

B

C

D

E

(b )

C D A B B C A D D E

B DA C

A E

C lo sed su b g rap h

C lo sed su b g rap h

Figure 9.24

Example 9.20 -- Optimal state assignment

x

1

0 1

0 0

0 1

11

1 0

0

0 1

1 1

1 0

(b )

Y 2 Y 1 /z

y 2

D 2

x x

0

0 1

0 0

0 1

11

1 0

1

0 1

1 0

1 0

D 1

x x

0

0 1

0 0

0 1

11

1 0

0

1 0

1 1

0 1

z

x

(a )

y 2y 1 0 1x

0 0

0 1

11

1 0

1 0 /0

0 0 /1

11 /1

11 /0

0 1 /0

11 /0

1 0 /1

0 0 /1

A

C

D

B

y 2y 1 y 2y 1y 2y 1

y 2 y 2

y 1 y 1 y 1

Figure 9.26

x

0 1

(a)(b )

E /0

A /1

E /0

A /0

D /0

B /0

D /1

A /0

B /1

C /0

A

B

C

D

EC lo sed su b g rap h

A D A E B C

B E C D A B

B D

D EA C

C E

C lo sedsu b g rap h

y 1

y 3 y 2

A

0 0 0 1 11 1 00 2 6 4

1 3 7 5

0

1

y 2

y 1

D B C

E

y 3

(c )

Example 9.21 -- Another state assignment problem

Figure 9.27

A D flip-flop realization of the previous example

Y 3 Y 2 Y 1 /z

(a )

y 3 y 2 y 1 0 1x

0 0 0

1 1 0

1 0 0

0 1 0

0 0 1

0 0 1 /0

0 0 0 /1

0 0 1 /0

0 0 0 /0

0 1 0 /0

1 1 0 /0

0 1 0 /1

0 0 0 /0

1 1 0 /1

1 0 0 /0

A

B

C

D

E

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 1 1

2 6 1 4 1 0

0 0

0 1

1 1

1 0

1

d d

d d d d

x

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 1 1

2 6 1 4 1 0

0 0

0 1

1 1

1 0

1

d d1

d d d d

1

x

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 1 1

2 6 1 4 1 0

0 0

0 1

1 1

1 0

1

d d 1

d d d d

1

x

1

1

(c ) (d ) (e )

y 2 y 1

xy 3

0 0 0 1 1 1 1 00 4 1 2 8

1 5 1 3 9

3 7 1 5 1 1

2 6 1 4 1 0

0 0

0 1

1 1

1 0

d d

d d d d

1

y 1

y 2

y 3

x

1

(b )

1

y 2 y 1y 2 y 1

y 2 y 1

xy 3 xy 3 xy 3

y 3 y 3y 3

y 2 y 2 y 2

y 1 y 1 y 1

Figure 9.28

Example 9.24 -- Closed partitions

x0 1

(a)

D /0

E /0

F /1

A /1

C /0

B /0

C /0

A /1

B /0

F /1

E /0

D /1

A

B

C

D

E

F

(b )

A BD E

A C

E F B C

D F

Figure 9.29

Example 9.25 -- Cross dependency

0 ,1

(a ) (b )

P resen tb lo ck

In p u t

P 3 : B 3 1B 3 2

B 2 1B 2 2

0 ,1

0 ,1

0 ,1

B 2 1B 2 2

P 2 : B 2 1B 2 2

B 3 2B 3 1

B 3 2B 3 1

0 1B 3 2

B 3 1

B 2 1

B 2 2

Figure 9.30

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Chapter 9 -- Simplification of Sequential Circuits