Chapter #2: Two-Level Combinational Logic Section 2.1, 2.2 -- Logic Functions and Gates

Contemporary Logic DesignTwo-Level Logic

© R.H. Katz Transparency No. 3-1

Chapter #2: Two-Level Combinational Logic

Section 2.1, 2.2 -- Logic Functions and Gates



Two-Level Combinational Logic

• Gates and Truth Tables• Switches• Minimization• Boolean Algebra• Canonical Forms• Waveforms• Positive/Negative Logic



Logic Functions: Boolean Algebra

Description Z = 1 if X and Y are both 1

Gates Truth TableXY Z Y

0 1 0 1

X 0 0 1 1

Z 0 0 0 1

NOT

AND

OR

Description If X = 0 then X ' = 1 If X = 1 then X ' = 0

Gates

X X 0 1

X 1 0

T ruth T able

X

Description Z = 1 if X or Y (or both) are 1

Gates T ruth T able X Y Z X

0 0 1 1

Y 0 1 0 1

Z 0 1 1 1



Logic Functions: NAND, NOR, XOR, XNOR

NAND

NOR

Description Z = 1 if X is 0 or Y is 0

Gates T ruth T able X 0 0 1 1

Y 0 1 0 1

X Y Z

Description Z = 1 if both X and Y are 0

Gates T ruth T able X Y

Z X 0 0 1 1

Y 0 1 0 1

Z 1000

z1110



Logic Functions: NAND, NOR Implementation

Any Boolean expression can be implemented by NAND, NOR, NOT gates

In fact, NOT is superfluous (NOT = NAND or NOR with both inputs tied together)

X0

1

Y0

1

X NOR Y1

0

X0

1

Y0

1

X NAND Y1

0



Logic Functions: XOR, XNORXOR: X or Y but not both ("inequality", "difference")XNOR: X and Y are the same ("equality", "coincidence")

X Y = XY’ + X’Y X Y = X’Y’ + XY

(a) XOR (b) XNOR

Description Z = 1 if X has a different

value than Y

Gates

T ruth T able

X Y

Z

X 0 0 1 1

Y 0 1 0 1

Z

Description Z = 1 if X has the same value as Y

Gates

T ruth T able

X Y

Z

X 0 0 1 1

Y 0 1 0 1

Z

0110

1001




Switches

X Y

X • Y

false

true

NOT

AND

OR

Switches

X

T rue

False X

Switches

X Y

X + Y

False

T rue



Logic Functions: NAND, NOR, XOR, XNOR

NAND

NOR

Switches

X Y

X • Y

False

T rue

Switches

X Y

X + Y False

T rue



Logic Functions: From Expressions to GatesMore than one way to map an expression to gates

E.g., Z = A' • B' • (C + D) = (A' • (B' • (C + D)))T1

T2

Literal: each appearance of a variable or its complement in an expressionE.g., Z = A B' C + A' B + A' B C' + B' C

3 variables, 10 literals

2-input gates3-input gate



Logic Functions: Rationale for Simplification

Logic Minimization: reduce complexity of the gate level implementation

• reduce number of literals (gate inputs)

• reduce number of gates

• reduce number of levels of gates

fewer inputs implies faster gates in some technologies

fan-ins (number of gate inputs) are limited in some technologies

fewer levels of gates implies reduced signal propagation delays

minimum delay configuration typically requires more gates

number of gates (or gate packages) influences manufacturing costs

Traditional methods: reduce delay at expense of adding gates

New methods: trade off between increased circuit delay and reduced gate count



Logic Functions: Alternative Gate Realizations

ABC’ + A’C + B’CTwo-Level Realization(inverters don't count)

((AB) C’) + ((AB)’ C)Multi-Level Realization

Advantage: Reduced Gate Fan-ins

(AB) CComplex Gate: XOR

Advantage: Fewest Gates

TTL Package Counts: Z1 - three packages (1x 6-inverters, 1x 3-input AND, 1x 3-input OR) Z2 - three packages (1x 6-inverters, 1x 2-input AND, 1x 2-input OR) Z3 - two packages (1x 2-input AND, 1x 2-input XOR)

0 1 0 1 0 1

A B C

0

0

Z 1

Z 2

Z 3

0

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Z 0 1 0 1 0 1 1 0

Z = A’B’C + A’BC + AB’C + ABC’




Algebraic structure consisting of:

set of elements B

binary operations {+, •}

unary operation {'}

such that the following axioms hold:

1. B contains at least two elements, a, b, such that a b

2. Closure a,b in B, (i) a + b in B (ii) a • b in B

3. Commutative Laws: a,b in B, (i) a + b = b + a (ii) a • b = b • a

4. Identities: 0, 1 in B (i) a + 0 = a (ii) a • 1 = a

5. Distributive Laws: (i) a + (b • c) = (a + b) • (a + c) (ii) a • (b + c) = a • b + a • c

6. Complement: (i) a + a' = 1 (ii) a • a' = 0



Gate Logic: Laws of Boolean AlgebraDuality: a dual of a Boolean expression is derived by replacing AND operations by ORs, OR operations by ANDs, constant 0s by 1s, and 1s by 0s (literals are left unchanged).

Any statement that is true for an expression is also true for its dual!

Useful Laws/Theorems of Boolean Algebra:Operations with 0 and 1:

Idempotent Law:

Involution Law:

Laws of Complementarity:

Commutative Law:

1. X + 0 = X2. X + 1 = 1

1D. X • 1 = X2D. X • 0 = 0

3. X + X = X 3D. X • X = X

4. (X')' = X

5. X + X' = 1 5D. X • X' = 0

6. X + Y = Y + X 6D. X • Y = Y • X



Gate Logic: Laws of Boolean Algebra (cont)

Distributive Laws:

Simplification Theorems:

DeMorgan's Law:

Duality:

Theorems for Multiplying and Factoring:

Consensus Theorem:

8. X • (Y+ Z) = (X • Y) + (X •Z)� 8D. X + (Y• Z) = (X + Y) • (X + Z)

9. X • Y + X • Y' = X10. X + X • Y = X11. (X + Y') • Y = X • Y

9D. (X + Y) • (X + Y') = X10D. X • (X + Y) = X11D. (X • Y') + Y = X + Y

12. (X + Y + Z + ...)' = X' • Y' • Z' • ...13. {F(X1,X2,...,Xn,0,1,+,•)}' = {F(X1',X2',...,Xn',1,0,•,+)}

12D. (X • Y • Z • ...) ' = X' + Y' + Z' + ...

14. (X + Y + Z + ...) = X • Y • Z • ...

15. {F(X1,X2,...,Xn,0,1,+,•)} = {F(X1,X2,...,Xn,1,0,•,+)}

D

D14D. (X •Y • Z • ...) = X + Y + Z + ...D

16. (X + Y) • (X' + Z) = X • Z + X' • Y 16D. X • Y + X' • Z = (X + Z) • (X' + Y)

17. (X • Y) + (Y • Z) + (X' • Z) = X • Y + X' • Z

17D. (X + Y) • (Y + Z) • (X' + Z) = (X + Y) • (X' + Z)

Associative Laws:7. (X + Y) + Z = X + (Y + Z) = X + Y + Z

7D. (X • Y) • Z = X • (Y • Z) = X • Y • Z



Gate Logic: Laws of Boolean AlgebraDeMorgan's Law

(X + Y)' = X' • Y'

(X • Y)' = X' + Y'

NOR is equivalent to ANDwith inputs complemented

NAND is equivalent to ORwith inputs complemented

DeMorgan's Law can be used to convert AND/OR expressionsto OR/AND expressions

X 0 0 1 1

Y 0 1 0 1

X 1 1 0 0

Y 1 0 1 0

X + Y

X•Y

X 0 0 1 1

Y 0 1 0 1

X 1 1 0 0

Y 1 0 1 0

X + Y

X•Y



Gate Logic: Laws of Boolean AlgebraApply the laws and theorems to simplify Boolean equations

Example: full adder's carry out functionCout = A' B Cin + A B' Cin + A B Cin' + A B Cin =



Gate Logic: Laws of Boolean AlgebraApply the laws and theorems to simplify Boolean equations

Example: full adder's carry out functionCout = A' B Cin + A B' Cin + A B Cin' + A B Cin

= A' B Cin + A B' Cin + A B Cin' + A B Cin + A B Cin

= A' B Cin + A B Cin + A B' Cin + A B Cin' + A B Cin

= (A' + A) B Cin + A B' Cin + A B Cin' + A B Cin

= (1) B Cin + A B' Cin + A B Cin' + A B Cin

= B Cin + A B' Cin + A B Cin' + A B Cin + A B Cin

= B Cin + A B' Cin + A B Cin + A B Cin' + A B Cin

= B Cin + A (B' + B) Cin + A B Cin' + A B Cin

= B Cin + A (1) Cin + A B Cin' + A B Cin

= B Cin + A Cin + A B (Cin' + Cin)

= B Cin + A Cin + A B (1)

= B Cin + A Cin + A B

identity

associative



Gate Logic: Laws of Boolean AlgebraProving theorems via axioms of Boolean Algebra:

E.g., prove the theorem: X • Y + X • Y' = X

E.g., prove the theorem: X + X • Y = X



Gate Logic: Laws of Boolean Algebra

Example: -- Apply DeMorgan’s TheoremZ = A' B' C + A' B C + A B' C + A B C'

Z’ =

Z' = (A + B + C') • (A + B' + C') • (A' + B + C') • (A' + B' + C)



Gate Logic: 2-Level Canonical Forms

Truth table is the unique signature of a Boolean function

Many alternative expressions (and gate realizations) may have the same truth table

Canonical form: standard form for a Boolean expression provides a unique algebraic signature

Sum of Products Formalso known as disjunctive normal form, minterm expansion

F =

F' =

F 0 0 0 1 1 1 1 1

F 1 1 1 0 0 0 0 0

C 0 1 0 1 0 1 0 1

B 0 0 1 1 0 0 1 1

A 0 0 0 0 1 1 1 1



Gate Logic: Two Level Canonical Forms

Sum of Products

Shorthand Notation forMinterms of 3 Variables

product term / minterm:ANDed product of literals in which eachvariable appears exactly once, in true orcomplemented form (but not both!)

F in canonical form:

F(A,B,C) = m(3,4,5,6,7)= m3 + m4 + m5 + m6 + m7= A' B C + A B' C' + A B' C + A B C' + A B C

A B C = m 1 A B C = m 2 A B C = m 3 A B C = m 4 A B C = m 5 A B C = m 6 A B C = m 7

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Minterms A B C = m 0

F’(A,B,C) = m(0,1,2)



F = A' B C + A B' C' + A B' C + A B C' + A B C

canonical form/minimal form

F =

F’ =

2-Level AND/OR

Realization



Gate Logic: 2 Level Canonical FormsProduct of Sums / Conjunctive Normal Form / Maxterm Expansion

Maxterm Shorthand Notationfor a Function of Three Variables

Maxterm:ORed sum of literals in which eachvariable appears exactly once in eithertrue or complemented form, but not both!

Maxterm form:Find truth table rows where F is 00 in input column implies true literal1 in input column implies complemented literal

F(A,B,C) = M(0,1,2) = M0 • M1 • M2= (A + B + C) (A + B + C') (A + B' + C)

F’(A,B,C) = M(3,4,5,6,7) = M3 • M4 • M5 •M6 •M7= (A + B' + C') (A' + B + C) (A' + B + C') (A' + B' + C) (A' + B' + C')

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Maxterms A + B + C = M 0 A + B + C = M 1 A + B + C = M 2 A + B + C = M 3 A + B + C = M 4 A + B + C = M 5 A + B + C = M 6 A + B + C = M 7



A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

W 0 0 0 0 0 0 0 1 1 0 X X X X X X

X 0 0 0 1 1 1 1 0 0 0 X X X X X X

Y 0 1 1 0 0 1 1 0 0 0 X X X X X X

Z 1 0 1 0 1 0 1 0 1 0 X X X X X X

Gate Logic: Incompletely Specified Functionsn input functions have 2 possible input configurations

for a given function, not all input configurations may be possible

this fact can be exploited during circuit minimization!

E.g., Binary Coded Decimal Digit Increment by 1BCD digits encode the decimal digits 0 - 9 in the bit patterns 0000 - 1001

n

2 2

These input patterns shouldnever be encountered in practice

associated output values are"Don't Cares"

Off-set of W

On-set of W

Don't care (DC) set of W



Gate Logic: Incompletely Specified FunctionsDon't Cares and Canonical Forms

Z = m0 + m2 + m4 + m6 + m8 + d10 + d11 + d12 + d13 + d14 + d15

Z = m(0, 2, 4, 6, 8) + d(10, 11, 12, 13, 14, 15)

Z = M1 • M3 •M5 • M7 • M9 • D10 • D11 • D12 • D13 • D14 • D15

Z= M(1, 3, 5, 7,9) + D(10, 11, 12, 13, 14, 15)

Canonical Representations of the BCD Increment by 1 Function:



Gate Logic: Two-Level Canonical FormsMapping Between Forms

1. Minterm to Maxterm conversion: rewrite minterm shorthand using maxterm shorthand replace minterm indices with the indices not already used

E.g., F(A,B,C) = m(3,4,5,6,7) = M(0,1,2)

2. Maxterm to Minterm conversion:rewrite maxterm shorthand using minterm shorthandreplace maxterm indices with the indices not already used

E.g., F(A,B,C) = M(0,1,2) = m(3,4,5,6,7)

3. Minterm expansion of F to Minterm expansion of F':in minterm shorthand form, list the indices not already used in F

E.g., F(A,B,C) = m(3,4,5,6,7) F'(A,B,C) = m(0,1,2) = M(0,1,2) = M(3,4,5,6,7)

4. Minterm expansion of F to Maxterm expansion of F':rewrite in Maxterm form, using the same indices as F

E.g., F(A,B,C) = m(3,4,5,6,7) F'(A,B,C) = M(3,4,5,6,7) = M(0,1,2) = m(0,1,2)



Gate Logic: Two-Level Canonical FormsFour Alternative Implementations of F:

Canonical Sum of Products

F1 = A’BC + AB’C’ + AB’C + ABC’ + ABCm(3,4,5,6,7)

Minimized Sum of ProductsF2 = BC + A

Canonical Products of Sums

F3 = (A+B+C) (A+B+C’) (A+B’+C)(0,1,2)

Minimized Products of SumsF4 = (A+B) (A+C)

A

B

F 2

F 3

F 4

F 1 C

A A’ B B’ C C’



Gate Logic: Two-Level Canonical FormsWaveform Verification of the Three Alternatives

Eight Unique Combinationsof Three Inputs

Except for timing glitches,output waveforms of the

three implementations areessentially identical

100 200

A B C F 1

F 2

F 3

F4



Gate Logic: Positive vs. Negative LogicNormal Convention: Postive Logic/Active High

Low Voltage = 0; High Voltage = 1

Alternative Convention sometimes used: Negative Logic/Active Low

Behavior in termsof Electrical Levels

Two Alternative InterpretationsPositive Logic ANDNegative Logic OR

Dual Operations

Negative Logic Positive Logic V oltage T ruth T able

F low low low high

F

F

A low low

high high

B low

high low

high

B 0 1 0 1

A 0 0 1 1

A 1 1 0 0

B 1 0 1 0

F

0001

1110



Gate Logic: Positive vs. Negative LogicConversion from Positive to Negative Logic

Positive Logic NOR:

Negative Logic NAND:

Dual operations: AND becomes OR, OR becomes AND Complements remain unchanged

Negative Logic Positive Logic V oltage T ruth T able

F high low low low

F

F

A low low high high

B low high low high

B 0 1 0 1

A 0 0 1 1

A 1 1 0 0

B 1 0 1 0

F



Homework Assignment

HW #3 -- Chapter 2: Sections 2.1 and 2.2

Documents

Chapter #2: Two-Level Combinational Logic Section 2.1, 2.2 -- Logic Functions and Gates