Ch2 Com Bi National Logic Circuits

8/14/2019 Ch2 Com Bi National Logic Circuits

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Dr. I. Damaj 1

Chapter 2

Combinational Logic Circuits

Dr. I. Damaj 2

Overview

n Part 1 Gate Circuits and Boolean Equationsn Binary Logic and Gates

n Boolean Algebra

n Standard Forms

n Part 2 Circuit Optimizationn Two-Level Optimization

n Map Manipulation

n Multi-Level Circuit Optimization

n Part 3 Additional Gates and Circuitsn Other Gate Types

n Exclusive-OR Operator and Gates

n High-Impedance Outputs


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Binary Logic and Gates

n Binary variables take on one of two values.

n Logical operators operate on binary values and binary variables.

n Basic logical operators are the logic functions AND, OR andNOT.

n Logic gates implement logic functions.

n Boolean Algebra: a useful mathematical system for specifyingand transforming logic functions.

n

We study Boolean algebra as foundation for designing andanalyzing digital systems!

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Binary Variables

n Recall that the two binary values havedifferent names:

n True/False

n On/Off

n Yes/No

n 1/0

n We use 1 and 0 to denote the two values.

n Variable identifier examples:

n A, B, y, z, or X1 for now

n RESET, START_IT, or ADD1 later


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Logical Operations

n The three basic logical operations are:

n AND

n OR

n NOT

n AND is denoted by a dot ().

n OR is denoted by a plus (+).

n NOT is denoted by an overbar ( ), a single

quote mark (') after, or (~) before the variable.

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n Examples:

n Y = A.B is read Y is equal to A AND B.

n z = x + y is read z is equal to x OR y.

n

X = ~A is read X is equal to NOT A.

Notation Examples

Note: The statement:

1 + 1 = 2 (read one plus one equals two)

is not the same as

1 + 1 = 1 (read 1 or 1 equals 1).


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Operator Definitions

Operations are defined on the values "0" and "1" for

each operator:

OR

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 1

NOT

10 =

01 =

AND

0 0 = 0

0 1 = 0

1 0 = 0

1 1 = 1

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01

10

X

NOT

XZ =

Truth Tables

n Truth table a tabular listing of the values of a functionfor all possible combinations of values on its arguments.

n Example: Truth tables for the basic logic operations:

111

001

010

000

Z = XYYX

AND

111

101

110

000

Z = X+YYX

OR


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n Using Switches

n For inputs:

n logic 1 is switch closed

n logic 0 is switch open

n For outputs:

n logic 1 is light on

n logic 0 is light off.

n NOT uses a switch such

that:

n logic 1 is switch open

n logic 0 is switch closed

Logic Function Implementation

Switches in series => AND

Switches in parallel => OR

CNormally-closed switch => NOT

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Logic Gates

n In the earliest computers, switches were opened andclosed by magnetic fields produced by energizingcoils in relays. The switches in turn opened andclosed the current paths.

n Later, vacuum tubes that open and close current

paths electronically replaced relays.

n Today, transistors are used as electronic switchesthat open and close current paths.


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(b) Timing diagram

X 0 0 1 1

Y 0 1 0 1

X Y(AND) 0 0 0 1

X 1 Y(OR) 0 1 1 1

(NOT) X 1 1 0 0

(a) Graphic symbols

OR gate

XY

Z 5 X 1 YXY

Z 5 X Y

AND gate

X Z 5 X

NOT gate orinverter

Logic Gate Symbols and Behavior

n Logic gates have special symbols:

n And waveform behavior:

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Logic Diagrams and Expressions

n Boolean equations, truth tables and logic diagrams describe the samefunction!

n Truth tables are unique; expressions and logic diagrams are not. This givesflexibility in implementing functions.

X

Y F

Z

Logic Diagram

Equation

ZYXF +=

Truth Table

11 1 1

11 1 0

11 0 1

11 0 0

00 1 1

00 1 0

10 0 1

00 0 0

X Y Z ZYXF .+=


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Boolean Algebra

An algebraic structure defined on a set of at least two elements , B,

together with three binary operators (denoted +, and ~ ) thatsatisfies the following basic identities:

1.

3.

5.

7.

9.

11.

13.

15.17.

Commutative

Associative

DistributiveDeMorgans

2.

4.

6.

8.

X . 1 X=

X . 0 0=

X.X X=

0=X.X

10.

12.

14.16.

X + Y Y + X =

(X + Y) Z+ X + (Y Z)+=

X(Y + Z) XY XZ+=X + Y X . Y=

XY YX =

(XY)Z X(Y Z)=

X + YZ (X + Y) (X + Z)=X. Y X+ Y=

X + 0 X=

+X 1 1=

X + X X =

1=X + X

X=X

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Some Properties of Identities

& the Algebran The identities above are organized into pairs. These pairs have names as

follows:n 1-4 Existence of 0 and 1

n 5-6 Idempotencen 7-8 Existence of complement

n 9 Involutionn 10-11 Commutative Laws

n 12-13 Associative Lawsn 14-15 Distributive Lawsn 16-17 DeMorgans La ws

n The dual of an algebraic expression is obtained by interchanging + and and interchanging 0s and 1s.

n Example: F = (A + C) B + 0

dual F = (A C + B) 1 = A C + B


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Boolean Operator Precedence

1. Parentheses2. NOT

3. AND

4. OR

n The order of evaluation in a Boolean

expression is:

n Consequence: Parentheses appeararound OR expressions

n Example: F = A(B + C)(C + D)

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Example 1: Boolean Algebraic Proof

n A + A B = A (Absorption Theorem)

Proof Steps Justification (identity or theorem)

A + A B

= A 1 + A B X = X 1= A ( 1 + B) X Y + X Z = X(Y + Z)(Distributive Law)

= A 1 1 + X = 1= A X 1 = X

n Our primary reason for doing proofs is to learn:

n Careful and efficient use of the identities and theorems of Boolean algebra,and

n How to choose the appropriate identity or theorem to apply to make forwardprogress, irrespective of the application.


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Overview Canonical Forms

n What are Canonical Forms?

n Minterms and Maxterms

n Index Representation of Minterms and Maxterms

n Sum-of-Minterm (SOM) Representations

n Product-of-Maxterm (POM) Representations

n Representation of Complements of Functions

n Conversions between Representations

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Canonical Forms

n It is useful to specify Boolean functions in a

form that:

n Allows comparison for equality.

n

Has a correspondence to the truth tables

n Canonical Forms in common usage:

n Sum of Minterms (SOM)

n Product of Maxterms (POM)


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Minterms

n Minterms are AND terms with every variable present in either trueor complemented form.

n Given that each binary variable may appear normal (e.g., x) orcomplemented (e.g., x), there are 2nminterms for nvariables.

n Example: Two variables (X and Y) produce2 x 2 = 4 combinations:

n XY (both normal)

n XY (X normal, Y complemented)

n XY (X complemented, Y normal)

n XY (both complemented)

n Thus there are four minterms of two variables.

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Maxterms

n Maxterms are OR terms with every variable in true orcomplemented form.

n Given that each binary variable may appear normal(e.g., x) or complemented (e.g., x), there are 2n

maxterms for nvariables.

n Example: Two variables (X and Y) produce2 x 2 = 4 combinations:n X + Y (both normal)

n X + Y (X normal, Y complemented)

n X+ Y (X complemented, Y normal)

n X+ Y (both complemented)


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n Examples: Two variable minterms and

maxterms.

n The index above is important for describing which

variables in the terms are true and which arecomplemented.

Maxterms and Minterms

x + yx y3

x + yx y2

x + yxy1

x + yx y0

MaxtermMintermIndex

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Purpose of the Index

n The index for the minterm or maxterm, expressed asa binary number, is used to determine whether thevariable is shown in the true form or complementedform.

n For Minterms:n 1 means the variable is Not Complemented and

n 0 means the variable is Complemented.

n For Maxterms:

n 0 means the variable is Not Complemented and

n 1 means the variable is Complemented.


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Index Example in Three Variables

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Index Example in Three Variables


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Index Examples Four Variables

Index Binary Minterm Maxterm

i Pattern mi Mi0 0000

1 0001

3 0011

5 0101

7 0111

10 1010

13 110115 1111

dcba dcba +++

dcba

dcba +++

dcba dcba +++

dcba +++

dcba dcba +++

dbadcba dcba +++

?

?

?

?c

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n Two-variable example:

and

Thus M2 is the complement of m2 and vice-versa.

n giving:

and

Thus Mi is the complement of mi.

Minterm and Maxterm Relationship

yxM2 += yxm2 =

i mM = i ii Mm =


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x y z index m1 + m4 + m7 = F1

0 0 0 0 0 + 0 + 0 = 0

0 0 1 1 1 + 0 + 0 = 1

0 1 0 2 0 + 0 + 0 = 0

0 1 1 3 0 + 0 + 0 = 0

1 0 0 4 0 + 1 + 0 = 1

1 0 1 5 0 + 0 + 0 = 01 1 0 6 0 + 0 + 0 = 0

1 1 1 7 0 + 0 + 1 = 1

Minterm Function Example

n Example: Find F1 = m1 + m4 + m7

n F1 = xyz + xyz + xyz

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Maxterm Function Example

n Example: Implement F1 in maxterms:

F1 = M0 M2 M3 M5 M6

)zyz)(xy(xz)y(xF1 ++++++=

z)yx)(zyx( ++++

x y z i M0 M2 M3 M5 M6 = F1

0 0 0 0 0 1 1 1 = 0

0 0 1 1 1 1 1 1 1 = 1

0 1 0 2 1 0 1 1 1 = 0

0 1 1 3 1 1 0 1 1 = 0

1 0 0 4 1 1 1 1 1 = 1

1 0 1 5 1 1 1 0 1 = 0

1 1 0 6 1 1 1 1 0 = 0

1 1 1 7 1

1 1 1 1 = 1

1


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F = A + B C + BC

n L (literal count) counts the AND inputs and the single literal ORinput.

n G (gate input count) adds the remaining OR gate inputsn GN(gate input count with NOTs) adds the inverter inputs

Cost Criteria (continued)

A

BC

F

L = 5

G= L + 2 = 7

GN = G + 2 = 9

Reading Assignment

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n F = ABC + ABD

n L = 6 G = 8 GN = 11

n F = (A+ C)(B+C)(A+B)

n L = 6 G = 9 GN = 12

n Same function and same

literal cost

n But first circuit has better

gate input count and better

gate input count with NOTs

n Select it!

Cost Criteria (continued)

ABC

F

F

ABC

Reading Assignment


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Boolean Function Optimization

n Minimizing the gate input (or literal) cost of a (a set of) Boolean equation(s)reduces circuit cost.

n We choose gate input cost.

n Boolean Algebra and graphical techniques are tools to minimize cost criteriavalues.

n Some important questions:n When do we stop trying to reduce the cost?n Do we know when we have a minimum cost?

n Treat optimum or near-optimum cost functions for two-level (SOP and POS)circuits first.

n Introduce a graphical technique using Karnaugh maps (K-maps, for short)

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Karnaugh Maps (K-map)

n A K-map is a collection of squares

n Each square represents a minterm

n The collection of squares is a graphical representation ofa Boolean function

n Adjacent squares differ in the value of one variable

n Alternative algebraic expressions for the same functionare derived by recognizing patterns of squares

n The K-map can be viewed asn A reorganized version of the truth table

n A topologically-warped Venn diagram as used to visualizesets in algebra of sets


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K-Map and Truth Tables

n The K-Map is just a different form of the truth table.

n Example Two variable function:

n We choose a,b,c and d from the set {0,1} to implement a particular

function, F(x,y).

Function Table

K-MapInputValues

(x,y)

Function

Value

F(x,y)

0 0 a

0 1 b

1 0 c1 1 d

y = 0 y = 1

x = 0 a b

x = 1 c d

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K-Map Function Representation

n Example: F(x,y) = x

n For function F(x,y), the two adjacent cells containing 1scan be combined using the Minimization Theorem:

F = x y = 0 y = 1

x = 0 0 0

x = 1 1 1

xyxyx)y,x(F =+=


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n Example: G(x,y) = x + y

n For G(x,y), two pairs of adjacent cells containing 1s canbe combined using the Minimization Theorem:

G = x+y y = 0 y = 1

x = 0 0 1

x = 1 1 1

( ) ( ) yxyxxyyxyx)y,x(G +=+++=

Duplicate xy

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Three Variable Maps

n A three-variable K-map:

n Where each minterm corresponds to the product terms:

n Note that if the binary value for an index differs in one bit position,the minterms are adjacent on the K-Map

yz=00 yz=01 yz=11 yz=10

x=0 m0 m1 m3 m2

x=1 m4 m5 m7 m6

yz=00 yz=01 yz=11 yz=10

x=0

x=1

zyx zyx zyx zyx

zyx zyx zyx zyx

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Alternative Map Labeling

n Map use largely involves:

n Entering values into the map, and

n Reading off product terms from the map.

n

Alternate labelings are useful:y

z

x

10 2

4

3

5 67

x

y

zz

yy z

z

10 2

4

3

5 67

x

0

1

00 01 11 10

x


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Example Functions

n By convention, we represent the minterms of F by a "1

n

Example:

n Example:

n Learn the locations of the 8

indices based on the variable

order shown (x, most significant

and z, least significant) on the

map boundaries

y

x

10 2

4

3

5 67

1

11

1

z

x

y10 2

4

3

5 671 11

1

z

mF(x,y,z) (2,3,4,5)=

mG(a,b,c) (3,4,6,7)=

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Combining Squares

n By combining squares, we reduce number of literals in aproduct term, reducing the literal cost, thereby reducingthe other two cost criteria.

nOn a 3-variable K-Map:n One square represents a minterm with three variables

n Two adjacent squares represent a product term withtwo variables

n Four adjacent terms represent a product term withone variable

n Eight adjacent terms is the function of all ones (novariables) = 1.


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Three-Variable Maps

n Example Shapes of 4-cell Rectangles:

n Read off the product terms for the rectangles

shown

y0 1 3 2

5 64 7x

z

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Three Variable Maps

y

11

x

z

1 1

1

z yx

K-Maps can be used to simplify Boolean functions by

systematic methods. Terms are selected to cover the

1sin the map.

Example: Simplify

F(X,Y,Z) = Z + XY

)(1,2,3,5,7z)y,F(x, m=


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Example

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Example


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Three-Variable Map Simplification

n Use a K-map to find an optimum SOP

equation for

,7)(0,1,2,4,6Z)Y,F(X, m=

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Four Variable Maps

nMap and location of minterms:

8 9 1011

12 13 1415

0 1 3 2

5 64 7

X

Y

Z

W

00 01 11 10

00

01

11

10

wx

yz


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Four Variable Terms

Four variable maps can have rectanglescorresponding to:

A single 1 = 4 variables, (i.e. Minterm)

Two 1s = 3 variables,

Four 1s = 2 variables

Eight 1s = 1 variable,

Sixteen 1s = zero variables (i.e. Constant

"1")

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Four-Variable Maps

n Example Shapes of Rectangles:

8 9 1011

12 13 1415

0 1 3 2

5 64 7

X

Y

Z

W


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Four-Variable Maps


X

Y

Z

8 9 1011

12 13 1415

0 1 3 2

5 64 7

W

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Four-Variable Maps



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Example

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Multiple-Level Optimization

Multiple-level optimization is performed by

applying transformations to circuitsrepresented by equations while evaluating

cost


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Transformation Examples

n Algebraic Factoring

F = ACD + ABC + ABC + ACD -- G = 16

n Factoring:

n F = A(CD + BC) + A (BC + CD) -- G = 16

n Factoring again:

n F = AC(B + D) + AC (B + D) -- G = 12

n Factoring again:F = (AC + AC) (B + D) -- G = 10

Reading Assignment

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n Decomposition

n The terms B + D and AC+ AC can be

defined as new functions E and H respectively,

decomposing F:

F = E H, E = B + D, and H = AC + AC G = 10

n This series of transformations has reduced G from 16 to10, a substantial savings. The resulting circuit has threelevels plus input inverters.

Reading Assignment


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n Substitution of E into F

nReturning to F just before the final factoring step:nF = AC(B + D) + AC (B + D) -- G = 12

nDefining E = B + D, and substituting in F:

nF = ACE + ACE -- G = 10

nThis substitution has resulted in the same cost as thedecomposition

Reading Assignment

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n Elimination

n Beginning with a new set of functions:

n X = B + C

n Y = A + B

n Z = AX + C Y G = 10

n Eliminating X and Y from Z:

n Z = A(B + C) + C (A + B) G = 10

n Flattening (Converting to SOP expression):

n Z = AB + AC + AC + BC G = 12

n This has increased the cost, but has provided a new SOP expression fortwo-level optimization.

Reading Assignment


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n Two-level Optimization

nThe result of 2-level optimization is:Z = AB + C G = 4

n This example illustrates that:

nOptimization can begin with any set of equations, notjust with minterms or a truth table

n Increasing gate input count G temporarily during a

series of transformations can result in a final solutionwith a smaller G

Reading Assignment

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n Extraction

nBeginning with two functions:

E = ABD + ABD

H = BCD + BCD G = 16

nFinding a common factor and defining it as a function:

F = BD + BD

nWe perform extraction by expressing E and H as the

three functions:

F = BD + BD, E = AF, H = CF G = 10

nThe reduced cost G results from the sharing of logicbetween the two output functions

Reading Assignment


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Other Gate Types

n Why?

n Implementation feasibility and low costn Power in implementing Boolean functions

n Convenient conceptual representation

n Gate classifications

n Primitive gate - a gate that can be described using asingle primitive operation type (AND or OR) plus anoptional inversion(s).

n Complex gate - a gate that requires more than oneprimitive operation type for its description

n Primitive gates will be covered first

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Buffer

n A buffer is a gate with the function F = X:

n In terms of Boolean function, a buffer is thesame as a connection!

n So why use it?

n A buffer is an electronic amplifier used to

improve circuit voltage levels and increase the

speed of circuit operation.

X F


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NAND Gate

n The basic NAND gate has the following symbol,

illustrated for three inputs:n AND-Invert (NAND)

n NAND represents NOT AND, i. e., the AND functionwith a NOT applied. The symbol shown is an AND-Invert. The small circle (bubble) represents the

invert function.

X

Y

Z

ZYX)Z,Y,X(F =

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NOR Gate

n The basic NOR gate has the following symbol,illustrated for three inputs:

n OR-Invert (NOR)

n NOR represents NOT - OR, i. e., the OR function witha NOT applied. The symbol shown is an OR-Invert.The small circle (bubble) represents the invertfunction.

X

YZ

ZYX)Z,Y,X(F+

+=


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Exclusive OR/ Exclusive NOR

n The eXclusive OR (XOR) function is an important Boolean

function used extensively in logic circuits.

n The XOR function may be;

n implemented directly as an electronic circuit (truly a gate) or

n implemented by interconnecting other gate types (used as a

convenient representation)

n The eXclusive NOR function is the complement of the XOR

function.

n By our definition, XOR and XNOR gates are complex gates.

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Exclusive OR/ Exclusive NOR

n Uses for the XOR and XNORs gate include:n Adders/subtractors/multipliers

n Counters/incrementers/decrementers

n Parity generators/checkers

n Definitionsn The XOR function is:n The eXclusive NOR (XNOR) function, otherwise

known as equivalenceis:

n Strictly speaking, XOR and XNOR gates do no existfor more that two inputs. Instead, they are replacedby odd and even functions.

YXYXYX +=

YXYXYX +=


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Truth Tables for XOR/XNOR

n Operator Rules: XOR XNOR

n The XOR function means:

X OR Y, but NOT BOTH

nWhy is the XNOR function also known as theequivalencefunction, denoted by the operator ?

X Y XY

0 0 0

0 1 1

1 0 1

1 1 0

X Y

0 0 1

0 1 0

1 0 0

1 1 1

or X Y(X Y)

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XOR/XNOR (Continued)

n The XOR function can be extended to 3 or more variables. For

more than 2 variables, it is called an odd functionor modulo 2

sum(Mod 2 sum), not an XOR:

n The complement of the odd function is the even function.

n The XOR identities:

== X1XX0X

1XX0XX ==XYYX =

ZYX)ZY(XZ)YX( ==

+++= ZYXZYXZYXZYXZYX


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Odd and Even Functions

n The odd and even functions on a K-map form

checkerboard patterns.n The 1s of an odd function correspond to minterms

having an index with an odd number of 1s.

n The 1s of an even function correspond to mintermshaving an index with an even number of 1s.

n Implementation of odd and even functions for greater

than 4 variables as a two-level circuit is difficult, so weuse trees made up of :

n 2-input XOR or XNORsn 3- or 4-input odd or even functions

Reading Assignment

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Odd and Even FunctionsReading Assignment


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Odd and Even FunctionsReading Assignment

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Parity Generators and Checkers

n In Chapter 1, a parity bit added to n-bit code to produce an n + 1 bit code:n Add odd parity bit to generate code words with even parityn Add even parity bit to generate code words with odd parityn Use odd parity circuit to check code words with even parityn Use even parity circuit to check code words with odd parity

n Example: n = 3. Generate even

parity code words of length 4 withodd parity generator:

n Check even parity code words oflength 4 with odd parity checker:

n Operation: (X,Y,Z) = (0,0,1) gives(X,Y,Z,P) = (0,0,1,1) and E = 0.If Y changes from 0 to 1 betweengenerator and checker, then E = 1 indicates an error.

XY

ZP

XY

ZE

P

Reading Assignment


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Hi-Impedance Outputs

n Logic gates introduced thus far

n have 1 and 0 output values,

n cannot have their outputs connected together, and

n transmit signals on connections in only one direction.

n Three-state logic adds a third logic value, Hi-Impedance (Hi-Z),giving three states: 0, 1, and Hi-Z on the outputs.

n What is a Hi-Z value?

n The Hi-Z value behaves as an open circuit

n This means that, looking back into the circuit, the outputappears to be disconnected.

n It is as if a switch between the internal circuitry and the output

has been opened.

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The 3-State Buffer

n For the symbol and truth table, IN is thedata input, and EN, the control input.

n For EN = 0, regardless of the value on IN(denoted by X), the output value is Hi-Z.

n For EN = 1, the output value follows theinput value.

n Variations:

n Data input, IN, can be inverted

n Control input, EN, can be inverted

by addition of bubbles to signals.

IN

EN

OUT

EN IN OUT

0 X Hi-Z

1 0 0

1 1 1

Symbol

Truth Table


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Transmission Gates

n The transmission gate is one of the designs for an

electronic switch for connecting and disconnectingtwo points in a circuit.

Reading Assignment

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n Exclusive OR F = A C

n The basis for the function implementation is TG-controlled paths to the output

Circuit Example Using TG

(b)

A

0

0

1

1

C

0

1

0

1

TG1

No path

Path

No path

Path

TG0

Path

No path

Path

No path

F

0

1

1

0

(a)

C

A

F

TG0

TG1

+

Reading Assignment


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Problems

n No. 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.10,

2.12, 2.14, 2.15, 2.16, 2.17, 2.18, 2.19, 2.20,2.21, 2.22, 2.23, 2.24, 2.27, 2.31, 2.32, 2.34.

Documents

Ch2 Com Bi National Logic Circuits