Upload
vuongthien
View
229
Download
5
Embed Size (px)
Citation preview
Advanced IP SolutionsAdvanced IP Solutions
J l R bJoel RosenbergVirage Logic CorporationVirage Logic Corporation Sr. Marketing Director
Virage Logic’s Expanding IP PortfolioHi hl Diff ti t d t M t A li ti R i tHighly Differentiated to Meet Application Requirements
© 2009 Virage Logic Corporation
Industry Market DriversyDigital Imaging
Computing Networking
MarketSegmentationSegmentation
RFID, Zigbee Handheld
StorageStorage
© 2009 Virage Logic Corporation
IP Application DomainWide Range of IP to Meet Area, Performance & Power Requirements
Embedded Processor Blocks:
High SpeedSiWare™ Tradeoffs
HS Compiler & Library
High Speed
High Density, performance mode
High Density, low power mode
Proc Proc
Critical speed path
Proc ProcTop Level Voltage Domain
Multi-Voltage Domains
Voltage Domain #2
Voltage Domain #3
Voltage Domain #4Voltage Domain #4
SiWare HD SRAM and/Register FilesSiWare HD or UHD Library With Power Optimization Kit
© 2009 Virage Logic Corporation
Low Power Design Solutionsg
d i h hi i i i• Power density on the chip is increasing
• SoC design techniques require memory and library IP to reduce standby and active powerto reduce standby and active power
Proc Proc
Step Lightly . . .
Standby Leakage Adaptive Dual Rail
D i P
Active Leakage CLKGating
Dynamic Freq
Scaling(DFS)
DynamicVoltageScaling(DVFS)
VoltageScaling(AVS)
Dual RailSRAM
Dynamic Power
© 2009 Virage Logic Corporation
SiWare Memory Compiler DashboardAdvanced Features to Offset Process Challenges
Lowest Vddmin
Design For Manufacturability
Lowest Vddmin
User-selectablecompile-timeoptions
Advanced Power Management(Light Sleep, Deep Sleep, Shutdown)
options
Dynamic Voltage Scaling
(Light Sleep, Deep Sleep, Shutdown)
Yield Configurability (Built‐in Repair, Margin Adjustment)Base Architectures:More than 500 memory
Area, Speed, Dynamic Power Configurability
More than 500 memory compilers across many technology generations
Established Nodes90nm and above
65nm 40nm 32/28nm and beyond
© 2009 Virage Logic Corporation
Compile-Time Test & Repair Optionsp p p
SiWare ‐ LT SiWare - IT SiWare ‐ STSiWare IT SiWare ST
Row Decoders
Row Decoders
Row Decoders
Redun
Memory Array Memory Array Memory Array
Sense Amp & Output BuffersControl Sense Amp & Output BuffersControl
Integrated Test (BIST Muxes I/O Scan Flops
Sense Amp & O/P BuffersControl
Integrated Test (BIST Muxes I/O Scan Flops
ndanc
STAR Memory System or Third Party BIST interface
Control Signals Input /Output Data
Control Signals Input/Output Data
Integrated Test (BIST Muxes, I/O Scan Flops,Comparator and Capture Logic)
STAR Memory System Interface
Control Signals Input/Output Data
Integrated Test (BIST Muxes, I/O Scan Flops,Comparator and Capture Logic)
Programmable serial register and d d f d d i f i
y
Input/Output Data,
y y
Input/Output Data,C t l Si l FUSE
STAR Memory System Interfacedecoder for redundancy information
Control Signals Control Signals eFUSEInput/Output Data,Control Signals
© 2009 Virage Logic Corporation© 2009 Virage Logic Corporation
SiWare Logic Libraries at 65nm, 45/40nm & 32/28nmB d P t t d d P t t P di T h lBased on Patented and Patent Pending Technology
• SiWare Logic Dashboard Options for Flexibilityg p y– Three library architectures – each optimized for density, speed, and low power applications
• Area vs. Performance• Area vs. Power
M l i Ch l lib i f dd d i– Multi-Channel libraries for added power savings
• Power Optimization Kits (POK) for Low Power Design Flows– Level-shifters for multi-voltage operation– Power-gating cells to reduce leakage power– State retention flip-flops for standby/sleep mode– Offset biasing to reduce leakage
• Engineering change order (ECO) extension library kits for f t t l l d i difi tifast metal-only design modifications
• Supporting industry-standard design flows and low power design flows frompp g y g p gCadence, Magma and Synopsys
© 2009 Virage Logic Corporation
Library Architectures for Optimal Performance, P & A (PPA)Power & Area (PPA)
1.44 HS1.44 HS
High Speed (HS)
ance
ance
High Speed (HS)30% faster than HD
erfo
rma
1.22HD
erfo
rma
1.22HD High Density (HD)
Up to 20% smaller area than competition
ativ
e Pe
UHDativ
e Pe
UHD
Up to 20% smaller area than competition
Rel
a
1
UHD
Rel
a
1
UHD
30% smaller than HD20% less dynamic power50% less static power
Ultra-High Density (UHD)
R l ti R t d A
1 1.2 1.42
R l ti R t d A
1 1.2 1.4250% less static power
© 2009 Virage Logic Corporation
Relative Routed AreaRelative Routed Area
SiWare Memory & SiWare Logic BenefitsSiWare Memory & SiWare Logic Benefits• Ultra-low power techniques proven in four generations of silicon, from 180nm to 65nm,
applied to the full memory product line• Compile-time options for power saving modes, read and write margin extensions,
ultra-low voltage operation, and innovative design for at-speed test
Performanceversus
Power Performance Testabilityversus Area
versusPerformance
versus Yield
versusArea
• Select between High-Density vs. High-Speed compilers for 30-70% performance improvement
• Memory compilers with multiple built-in power management modes in the same compiler
• Read/Write Margin settings and Sigma-based design characterization to manage local
• Options for external, integrated at-speed test and redundancy
• Supported by STAR Memoryp p p• Ultra low voltage operation at
20% below nominal voltage reduces 40% dynamic power
gprocess variance based on memory size and number of memories per chip
Supported by STAR Memory System for test and repair
© 2009 Virage Logic Corporation
Embedded Non-Volatile Memory (NVM)M k t & A li tiMarkets & Applications
S it / E tiWireless / RF
Security / EncryptionUses• Encryption keys• Counters
Uses• Configuration settings• EEPROM replacement• Customer settings (i e volume)
Markets• Flash controllers• Hard disk drives• Home entertainment devices (HDMI)
Customer settings (i.e. volume)
Markets• 802.11• BlueTooth
Zi b
EmbeddedMTP
EmbeddedMTP Home entertainment devices (HDMI)
• Digital content devices• Zigbee• GPS• RFID
MTP on Std. CMOS
Process
MTP on Std. CMOS
Process
AnalogUses High Reliability
ProcessProcess
Uses• Post package trim• Fuse replacement• In-field calibration
High ReliabilityUses• Real time status and control• Configuration settings
Markets• Precision analog (i.e. ADCs)• Silicon Clocks• MEMS pressure sensors
Markets• Power management• Automotive• Military
g g
© 2009 Virage Logic Corporation
• Accelerometers / gyroscopesMilitary
Intelli™ DDR System Aware IP SolutionHigh Performance ApplicationsIntelli™ DDR System Aware IP SolutionHigh Performance ApplicationsHigh Performance ApplicationsHigh Performance Applications
• First commercially available all-digital DDR3-1600 solution on TSMC 65nm GPFirst commercially available all digital DDR3 1600 solution on TSMC 65nm GP• Intelli LPDDR/LPDDR2 interface IP solutions for low power applications• Intelli DDR/LPDDR Controllers deliver lower system costs
Package
© 2009 Virage Logic Corporation
Virage Logic Expands Interface IP PortfolioVirage Logic Expands Interface IP Portfolio
• Silicon proven product portfolio through licensing agreement with AMDSilicon proven product portfolio through licensing agreement with AMD– PCI Express 2.0/1.1/1.0a
• PHY: Hard Macro- TSMC 40GPHY: Hard Macro TSMC 40G• Endpoint and Root complex Controller: RTL
– MIPIMIPI• D-PHY: Hard Macro- TSMC 65LP then 40LP• CSI Receiver: RTL• DSI Transmitter: RTL
– HDMI/DVI/DisplayPortp y• Transmitter PHY: Hard Macro- TSMC 40G• Transmitter Controller: RTL
(DisplayPort 1.1a, HDMI 1.3 and DVI 1.0 with HDCP 1.2 and 1.3)
© 2009 Virage Logic Corporation
The Sure Path to 40nm SuccessVirage Logic The Semiconductor Industry’s Trusted IP PartnerVirage Logic – The Semiconductor Industry s Trusted IP Partner
• Leading the way with a broad portfolio of 40nm IP solutionsead g t e ay t a b oad po t o o o 0 so ut o s
• Virage Logic’s embedded Memory/Logic/NVM/Interface IP is highly differentiated for today’s SoCs and ready for the next generation– Increased features / functionality– Reduced cost / power
• Solutions are available and fully qualified from leading foundries for a• Solutions are available and fully qualified from leading foundries for a wide range of process nodes 250nm 32/28nm
• Learn more at: www.viragelogic.com/SurePathto40nmSuccess
© 2009 Virage Logic Corporation
Thank youThank you
• Explore more about Virage Logic and related IP at ChipEstimate.com
• Use IP specific to Virage Logic to plan your next chip!
• Please stay and talk with Joel Rosenberg
Visit Virage Logic at the TSMC OIP Booth #822Visit Virage Logic at the TSMC OIP Booth #822
15