Advanced CMOS SOC Status Today and Outlook Tomorrow

8/8/2019 Advanced CMOS SOC Status Today and Outlook Tomorrow

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FunctionalityDigital(incl. eSRAM)Mixed Signal / RFeDRAMeNVM

Advanced CMOS System on a Chip Technology Platforms-Status Today & Outlook TomorrowReinhard Mahnkopf

INFINEON TECHNOLOGIES CORPORATIONSt.- Martin- Strasse 76D- 81541 MunichGermany

Mask Adder10070+ 15-25 ?+ 25 - 35 Yo+40 - 50%

AbstractDuring the last few years there has been anincreasing interest of the product communityto integrate more different features andfunctions on just one chip with minimumprocess complexity and yield impact. Thissystem on a chip integration is definitely achallenge for process technology because allthe parts have to be combined in a modularway allowing the designers to re-use thesame IP in various products. A technologyplatform allows system on a chip integrationfor a broad spectrum of products, but key isto take advantage of the potential benefits ofSOC with respect to performance, power andcost. This requires system know how as wellas leading edge technology.Technology PlatformToday system on a chip integration of Digital,Mixed SignaVRF, embedded SRAW DRAM /NVM, BiCMOS and even MEMS has beendemonstrated already [l], 2], [3].There are alot of chances and opportunities, economical-ly and technically. The availability of eDRAM& eNVM functionality offers the productcommunity the unique chance to addressnew segments and realize new products bytaking advantage of having these features onchip with regard to performance and power.

Digital

Fig.1 SoC Platform Concept at lnfineon0-7803-6520-8/01/$10.00 Q 2001 IEEE.

The bases for a SoC technology platform is ageneric digital CMOS process. Additionalprocess modules are usually added in amodular manner to provide the requiredfunctionality. In todays state of the arttechnology platforms a lot of differenttechnology options are already available. Forexample, Infineons 0.18pm [4], 0.13pm [5] &0.10pm platforms, called C10, C l l & C12 areoffering the following technology optionswhich are kind of representative for theindustry - only the technical implementationoften differs from company to company:digital, mixed signal/RF, embedded SRAM /DRAM NVM (see fig.1).A rough estimation of the additional processcomplexity which comes with SOC isindicated in tab.1 taking mask count as ameasure. The exact numbers might differdepending on the technology featuresincluded, the specific requirements on thesefeatures and the technical realization, but acertain range can be given: A complete SOCintegration including all features mentionedabove is achievable with roughly 2x processcomplexity. Yield deterioration and test costincrease not taken into account.

compared to puredigitalw/ 4 levelsof metalTab.1 Process Complexity Adders for System ona Chip optionsFig.2 shows the modularity of the SOCtechnology concept used by lnfineon for the


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35last technology nodes in more detail (eNVMnot shown here). The process modules forthe different features can be added or left outwithout effecting each other. The concept willbe described n more detail later on.

MixedSignal CMOS Digital eDRAM

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Fig9 Infineons modular SOC technology conceptwith additional mixed signal & eDRAM processmodules. .igital ProcessThe core of each SOC platform is a genericdigital process. Table 2 shows an overview ofthe digital platform processes of lnfineon withthe relevant key figures:Feature I c10 I c11 I c12

I I ISupply Voltage / V

Tab.2 Infineons Digital Platform Technologies w/key figuresThe digital processes already offer the choicebetween different transistor options to coverall needs from ultra low power to highestperformance for ASIC & FP applications. Anoverview of the transistor key data forInfineons platform technologies is given intab.3 with typical gate delay data for aringoszillator with FI = FO = 1. Besides theactual device data additional curves forconstant off currents of 10pNpm , I nN pnand 100nNFm are plotted n fig.3.

nFETl nFET1 nFET/1.84 1.2V 1.5 V 1.OV 1.24

5w1210 375/150 600/25528.5 28 2015/15 so/% 8om onered offered

Mx)/zM) 5001210 7301335 500/EU 700/3GQ1 1 ;:,; 1 I 1.5,/,l.5 1 2 . 3 7 17601320 5601240 820/385 655/295 89014102001100 6 / 6 10/10 5 0 / 5 0 Bo le015.5 11.5Tab.3 Device menu for the digital processesThe leakage current specs have to be relaxedto insure the typically required performanceincrease of 20% per generation. This willbecome even more a challenge for theupcoming technology nodes with supplyvoltages below 1V.

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c10 c11 c12Technology GenerationFig.3 Gate delay vs. technology generation fordifferent off current specsIn addition the generic platform processesoffer DG (Dual Gate oxide) devices with athicker gate dielectric to satisfy the I/Orequirements. Often this thick GOX is usedfor mixed signal transistors as well. Thescaling of the most important ground rulescan be seen in table 4 exhibiting the 2x indensity per generation. Leading edgelithography and masks and sophisticated dataengineering is needed: technical as well aseconomical problems have to be resolved to


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36continue this trend for the next technologynodes.

Groundrule I c10 I c11 I c12I I I

Tab.4 Groundrule scaling over generationsFig.4 shows top views of the 6T SRAM cellsfor C10 and C11 with the isolation and gatelevel patterns. A lot of process optimizationand yield learning was needed, but thesecells can now be implemented withoutincreasing process complexity. In additionthese technologies offer a 6T dense cellversion by aggressively tightening the groundrules. Again, 2x boost in density pergeneration is achieved as shown in Fig.5.

Fig.4 The 6 Transistor - SRAM cells for C10 &C11- SEM top views (nearly on scale)

Cl0 c11 c12TechnologyGeneration

Fig.5 SRAM cell size vs. technology generationsolid line: standardcells; data points: densecellsFor wiring the lnfineon technologies are usingcopper -since CIO- for up to 10 levels (forC12) for maximum backend performance

I

while the last levels can be chosen to be fineor relaxed pitch. The copper processpromises an up to 40% reduction in wiringresistance compared to an aluminumtechnology of equivalent dimensions.Integration of a true low k material (startingwith C11) resulted in superior interconnectperformance (30% performance advantagecompared to oxide based BEOL solutions) ataggressive pitches. Wirebond or flipchippackaging can be used in these technologiesfor off-chip connections.

Fig.6 Cu wiring of a DS P core in Infineons C10Technology ( 0 . 1 8 ~ )Mixed signal / RF:Especially for products in the wireless marketthe availability of mixed signal & RF featuresbecomes increasingly important. Usuallymixed signal functionality includes analogtransistors and passive components, like highprecision resistors, high linearity metal-insulator-metal capacitors (MIMCAP) andinductors, intrinsic inductors with standardmetallization or high Q value inductors withthick wire metallization [6]. ifferent materialsare being used for the MIM capacitors asdielectric like oxides, nitrides or high kmaterials already [7]. salicide blockingmask is used to realize non salicided polyand diffusion resistors; a whole range ofsheet rhos can be offered by combiningdifferent device implants. The analogtransistors are designed for low outputconductance and low substrate biassensitivity with a modified well construction.The matching behavior of these devices is of


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37major importance. With reduced supplyvoltage SOC integration of mixed signalbecomes more and more an issue, fromtechnology and circuit design point of view.

Fig.7 Highly linear Metal- Isolator- Metal-Capacitor (MIMCAP) in Cu Dual DamasceneMetallizationAdvanced CMOS becomes more and moreinteresting for RF applications, with reducedgate length the RF capability of the silicondevices is entering a regime which was up tonow entirely dominated by lllNsemiconductors. The cutoff frequencies of thetransistors start to exceed 100 GHz (fig.8).These numbers have been achieved by justoptimizing the transistor layout, without anyadditional technology measures. Substrateloss and cross talk are becoming more andmore an issue in this regime.

t10.0I10 c11 c12TechnologyGeneration

Figd Maximum cutoff frequency f vs.technology generation

ed DRAM:For some products it is crucial to have logicand embedded DRAM functionality on onechip. Typical areas of application are graphics,disk drives, digital video and networking.Different concepts for eDRAM technologieshave been proposed, integration of highperformance devices into commodity DRAM[8], integration of a DRAM cell into state-of-the-art CMOS logic [9], with different storagecells. The technology plalform concept forSOC integration of eDRAM functionalitywithin lnfineon relies -as can be seen alreadyin fig.2- on a trench based cell concept. Atrench based cell is much more favorable forSOC than a stacked cell concept. The heatcycle of the storage capacitor has beencompleted before isolation and before theformation of the high performance logicdevices without complex topology in mid ofline. The borderless contact usually used incommodity DRAM is omitted to avoid thenegative impact of the DRAM gate stack onthe high speed logic channel length control. ASEM cross section of the cell in 0.18pmtechnology s shown in fig.9. A comparison ofthe DRAM cell areas achieved with thisconcept and the SRAM cell sizes of the sametechnology node exhibit a factor of 8 inbetween (fig.10).hW* & UnnUlCldMJvnstian

Fig.9 Cross section of the eDRAM' cell in'Infineon's C10-0.18pm-SoC platform


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0,lWI10 c11 c12TechnologyGenerationFig.10 eDRAM & SRAM cell sizes vs. technologygenerationSome products can benefit significantly fromhaving logic and RAMs on the same chip;performance requirements and / or costaspects determine if an eDRAM- or aneSRAM integration is the preferable concept.For non-performance critical circuits the costtradeoff between process complexity and cellsize is dependent on the ratio between logic& memory density (fig.11).#of LogicGates

Amount ofMemory

Fig.11 Areas of application eDWM vs. eSWMFmbeddedNVM;Embedded non- volatile memory functionalityis needed whenever non- volatile on chipdata or program storage is required. Areas ofapplication are in consumer, computerperipherals, automotive & industrial. For NVMintegration several different technologies and

concepts are known with their respective prosand cons [lo]. Within lnfineon the stackedgate flash concept is used for sometechnology generations already. HV devicesand the stacked cell itself need to beintegrated which requires a significantamount of additional processing. The stackedgate cell concept uses uniform channelprogramming. Fig.12 shows a SEM crosssection after the gate stack etch with poly2 Idielectric / poly1

Fig.12 SEM cross section of the stacked cell afterpoly etch (C10 - 0 . 1 8 ~echnology)There are other technology features whichcan be integrated on chip as well as part ofSoC like BiCMOS [ l l ] or MEMS, butsometimes a multi chip module (MCM) orsytem in a package (SIP) is the more costeffective solution here.Future TrendsFirst announcements of silicon manufacturersare indicating that the system-on-a-chiptrend described above will continue at leastfor the next one or two technologygenerations (0.07pm and 0.05pm) eventhough a modular and cost effectiveintegration of all different functions on justone chip becomes increasingly difficult. Butone innovation which attracted more andmore attention in the last years couldinfluence this trend: Sol. While SO1 is clearlyadvantageous for digital applications, thereare still some uncertainties about thesuitabil ity of this material for mixed signalapplications and RAMs. Some papers have


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39been published on this topic alreadydemonstrat ing feasibility e.g. for mixedsignal/RF [12] and for eDRAM [13], ut theuse of SO1 could shift the optimum designpoint for SoC significantly.From todays point of view there seems to bea close link between the future of planarCMOS and SoC integration: The SoCplatform concept will continue as long as wecontinue scaling planar CMOS successfully.AcknowledgmentsThe author would like to thank the LEAD team(INFINEON, IBM, UMC) in East Fishkill, NY, USAfor their support and Josef Winnerl, lnfineonMunich or his helpful suggestions.References[l] . Ootsuka, et al.: A Highly Dense, High-Performance 130nm node CMOS Technology forLarge Scale System-on-a-Chip Applications,IEDM Tech. Digest (2000)[2] A.H. Perera, et al.: A versatile 0.13um CMOSPlatform Technology supporting HighPerformance and Low Power Applications, IEDMTech. Digest (2000)[3] M. Yoshida, et al.: An Embedded 0.405um2Stacked DRAM Technology Integrated with high-performance 0.2um CMOS Logic and 6-levelmetalization, IEDM Tech. Digest (1999)[4] R. Mahnkopf, et al.: System on a ChipTechnology Platform for 0.18p-i Digital, MixedSignal & eDRAM Applications, IEDM Tech. Digest(1 999)[5] T. Schiml, et al.: A 0.13um CMOS Platformwith Cu/low-k Interconnects for System on a ChipApplications, 2001 Symposium on VLSlTechnology, (2001)[6] M.R. Frei, et al.: Integration of high4inductors in a latch-up resistant CMOSTechnology; IEDM Tech. Digest (1999)[7] K. Miyashita, et al.: A High Performance 100nm Generation SOC Technology (CMOS IV) forHigh Density Embedded and Mixed Signal LSls;2001 Symposium on VLSl Technology, (2001)[8] H. Wurzer, et al.: A 0.17um Embedded DRAMTechnology with 0.23um2 cell size and advancedCMOS logic; 2000 Symposium on VLSlTechnology, (2000)[9] K. Kokubun, et al.: New Embedded DRAMTechnology using Self-aligned Salicide Block(SSB) Process for 0.18um SOC (System on a

Chip); 1999 Symposium .on VLSl Technology,(1999)[lo] G. Tempel: System-on-a-Chip Technology-Embedded Non Volatile Memory ; IEDM ShortCourse; December 1997[ll] .S. Carroll, et al.: A 0.16um ModularBiCMOS (COM2 - BiCMOS) Technology for RFCommunication Cs; IEDM Tech. Digest (1999)[12]S. Maeda, et al.: Impact of 0.18um SO1CMOS Technology using Hybrid Trench Isolationwith High Resistivity Substrate on EmbeddedRF/Analog Applications; 2000 Symposium onVLSl Technology, (2000)[13] R. Hannon, et al.: 0.25um Merged BulkDRAM and SO1 Logic using Patterned Sol;2000Symposium on VLSl Technology, (2000)

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Advanced CMOS SOC Status Today and Outlook Tomorrow