May 26, 2015 1 © Yun Chiu

Radiation-Tolerant SAR ADC Architecture and Digital Calibration Techniques

Yun ChiuUniversity of Texas at Dallas

PH-ESE Seminar, CERNMay 26, 2015

May 26, 2015 2 © Yun Chiu

DetectorOutput Signal

Potential Phase-II FEB Upgrade (On detector)

MUX&

Serializer Optical Links

To Back-endAnalog Shaper

ADC

Preamp

ADC

Phase-II LAr AFE Upgrade Needs

• Trigger-less, continuous signal digitization & data transmission• Potential technical challenges: Minimum 12-bit, 40-MSPS ADC w/ low power Back-end signal processing w/ elevated pileup noise (80

MSPS can significantly aid the energy resolution…)

May 26, 2015 3 © Yun Chiu

Plan I Plan IIGain Segmentation 4 scales 2 scales

ADC Resolution 12 bits 14 bitsSample Rate 40 / 80 MS/s 40 / 80 MS/sTechnology CMOS SiGe & CMOS

Feature SoC integrated MCM integration

Potential ADC Specs for P2 Upgrade

• Our (TxACE, UTD) goals and approaches: 12/14 bit, 40/80 MS/s, 25 mW, 1.2 V, 65-nm CMOS SAR architecture [1] and digital calibration [2, 3] TID results presented at TWEPP’14, SEE/SEU will be

addressed in the current design (R&D of FY15)

May 26, 2015 4 © Yun Chiu

SRC Texas Analog Center

SRC Industry Advisory Board

(AMD, Freescale, GlobalFoundries,

IBM, Intel, TI)

TI TxACE Research Advisory Board

Our proposed ADC work for LAr Phase-II upgrade will be carried out in TxACE, an SOA A/MS/RF R&D facility

May 26, 2015 5 © Yun Chiu

SAR ADC Architecture

SAR = 1 comparator + 1 DAC + digital logic

May 26, 2015 6 © Yun Chiu

Trend of SAR and Pipelined ADCs

1E+10

1E+11

1E+12

1E+13

1E+14

1E+15

1E-16 1E-15 1E-14 1E-13 1E-12 1E-11

Pipeline (<2005)Pipeline (2005-2010)Pipeline (2010-2013)SAR (<2005)SAR (2005-2010)SAR (2010-2013)

ISSCC & VLSI data

100mW

1W

10mW1mW100μW10μW

Efficiency = Power/(2·BW·3ENOB)

Perf

orm

ance

= 2

·BW

·3EN

OB

10W

PipelineADC

SARADC

May 26, 2015 7 © Yun Chiu

12-bit, 45-MS/s, 0.13-μm CMOS ADCSub-binary DAC ODC

C0C1C13

SAR Logic

–VR

d0d1d13

CMPp

+VR

VX

C0

Vin

C13,d C6,dC∆

ReadyCMPn

CLKCLK

ACLK

...

SUB-BINARYREDUNDANCY

CA

LIB

RAT

ION

May 26, 2015 8 © Yun Chiu

+FS

-FS

1111111011011100101110101001100001110110010101000011001000010000

in

X

Binary Search

• When everything is ideal…

May 26, 2015 9 © Yun Chiu

+FS

-FS

11111110

1100101110101001100001110110010101000011001000010000

in

X

1101

Binary Search w/ Dynamic Error

• Settling error, comparator hysteresis etc.

May 26, 2015 10 © Yun Chiu

Overlapping Search Ranges

• Results indicate decision trajectory, no longer binary-coded

+FS

-FS

1111111011011100101110101001100001110110010101000011001000010000

in

X

1

10

0

May 26, 2015 11 © Yun Chiu

Redundancy of Sub-binary Search

• Dynamic decision errors absorbed by redundancy

+FS

-FS

1111111011011100101110101001100001110110010101000011001000010000

in

X

May 26, 2015 12 © Yun Chiu

SAR ADC w/ Redundancy

• Redundant conversion consumes more bit cycles, but can recover intermediate decision errors.

• Redundancy can be exploited to expedite conversion progress or to save power.

• Redundancy can also be exploited to reduce SEE.

• Redundancy can also be exploited to enable digital calibration.

May 26, 2015 13 © Yun Chiu

Sub-binary Redundancy (1)

MSB = 1

MSB = 0

FS/2Vin

No redundancy

2

Dout

1

2N

2N-1

0 FS

Super-binary Binary Sub-binary

• Sub-binary redundancy results in overlapped decision segments.

• Within the overlap, one analog input is mapped to two digital codes.

May 26, 2015 14 © Yun Chiu

Sub-binary Redundancy (2)N = 14

= 011…1 VH

= 100…0 VL

Note: only one transitionedge shows up

VL VHVi

Redundant region

1

Do

2

2N

2N-1

0 FSMSB = 1

MSB = 0

Do

May 26, 2015 15 © Yun Chiu

Exploiting Redundancy for Cal.

A

B

PN = 0 PN = 1

May 26, 2015 16 © Yun Chiu

Exploiting Redundancy for Cal.

Slope correction

to eliminate

gapA (PN=0)

B (PN=1)

May 26, 2015 17 © Yun Chiu

Do

d o

Digital Bit-Weight Calibration

jw = bit weights

Nraw = 14 Nnet = 12

j2d -1N-1

io

j=0j

FS

wVd = =V

May 26, 2015 18 © Yun Chiu

12-bit, 45-MS/s, 0.13-μm CMOS ADC

Die size: 0.06 mm2

• 12 b, 45 MS/s in FG mode

• 3-mW power (36.3 fJ/step)

• Most read JSSC article Nov. 2011

C0C1C13

SAR Logic

–VR

d0d1d13

CMPp

+VR

VX

C0

Vin

C13,d C6,dC∆

ReadyCMPn

CLKCLK

ACLK

May 26, 2015 19 © Yun Chiu

Measured ADC Spectra (BG Mode)

0 5 10-120

-100

-80

-60

-40

-20

0

dB

Freq [MHz]0 5 10

-120

-100

-80

-60

-40

-20

0

dB

Freq [MHz]

After Cal.Before Cal.

SNDR = 60.2dBSFDR = 66.4dBTHD = -61.7dB

SNDR = 70.7dBSFDR = 94.6dBTHD = -89.1dB

May 26, 2015 20 © Yun Chiu

Comparison with 12-bit ADCs

2000 2002 2004 2006 2008 201010

-2

10-1

100

101

Year

Fo

M (

pJ/

con

v. s

tep

)

2000 2002 2004 2006 2008 201010

-2

10-1

100

101

102

Year

Act

ive

area

(m

m2 )

0.06 mm2

46 fJ/step @ 22.5 MS/s31 fJ/step @ 45 MS/s

Total Power: 3.0 mW

(@ time of publication)

May 26, 2015 21 © Yun Chiu

12-bit, 160-MS/s, 40-nm CMOS ADC

• (5b + 8b) synchronous two-step pipelined SAR architecture• First-stage capacitor weights identified w/ opportunistic DAC dither

May 26, 2015 22 © Yun Chiu

Die Photo and Power Breakdown

Die photo(0.042 mm2)

300μm

139μ

m

Powerbreakdown

Total Power: 5.0 mW

May 26, 2015 23 © Yun Chiu

10 80 30055

60

65

70

75

80

85

90

Fin [MHz]

dB

SNDRSFDR

100 160 20055

60

65

70

75

80

85

90

Fs [MHz]

dB

SNDRSFDR

Measured ADC Performancefs = 160MHz after cal. fin = 25MHz after cal.

fNyq=80MHz fs=160MHz

fin [MHz] fs [MHz]

May 26, 2015 24 © Yun Chiu

TID Test Setup

• DUT under X-ray radiation when powered up w/ clock input• ADC performance (e.g., SNDR, SFDR, power, etc.) measured

after irradiation

SMU TID setup ADC test board

May 26, 2015 25 © Yun Chiu

Measured SNDR/SFDR (80MS/s)

100

102

66

66.5

67

67.5

68

68.5

69

SN

DR

[dB]

100

101

102

10310.67

10.75

10.84

10.92

11.00

11.09

11.17

EN

OB

[bit]

Radiation dose [krad]

fin=10MHzfin=25MHzfin=40MHz

100

102

80

82

84

86

88

90

92

SFD

R [d

B]

100

101

102

10313.00

13.33

13.66

14.00

14.33

14.66

15.00

EN

OB

[bit]

Radiation dose [krad]

May 26, 2015 26 © Yun Chiu

Performance Comparison

1E+10

1E+11

1E+12

1E+13

1E+14

1E+15

1E-16 1E-15 1E-14 1E-13 1E-12 1E-11

Pipeline (<2005)Pipeline (2005-2010)Pipeline (2010-2013)SAR (<2005)SAR (2005-2010)SAR (2010-2013)

ISSCC & VLSI data

100mW

1W

10mW1mW100μW10μW

Efficiency

Perf

orm

ance

10W

12b,160MS/s5mW

May 26, 2015 27 © Yun Chiu

Current Design: 14b, 80MSPS

• Architecture: redundant 2-step SAR• Digital circuits: protected with TMR• Analog circuits (the focus of this work): Sub-binary + inter-stage redundancy [1, 2] Split-ADC (redundancy, calibration) [3] Summing-node SEE detector (recently

proposed needs verification)

May 26, 2015 28 © Yun Chiu

SEE – Split-ADC Redundancy

• If ∆Do is large, chose the output of the ADC that is not hit.• A 3-dB SNR gain with normal operation (i.e., no hit).• Split-ADC also enables digital background calibration [3].

May 26, 2015 29 © Yun Chiu

SEE – Modeling

100Time[ps]

Current[mA]

10

0 200

175 nm

90 nm

Impactpoint

2 1-t /τ -t /τtot

2 1

QI = e - et τ - τ [4]

May 26, 2015 30 © Yun Chiu

SEE – Hit Detector

• For QSEE = 100fC and CTOT = 2pF, Verr = 50mV ! [4]

• SEE detector is formed by a pair of resistors, a “substrate-current amplifier”, and some digital logic.

May 26, 2015 31 © Yun Chiu

Preliminary Circuit Simulation

ISEE

CLK_samp

SEE_Amp

SEE_Out

• The total charge collected due to SEE is set to 5.5fC, causing a 2.75mV voltage error on a 2pF DAC (~20 LSBs).

• The detector is reset during each sampling phase.

0.6V0.97V

May 26, 2015 32 © Yun Chiu

Split-ADC Calibration

A A,i A,ii

d = w D

B B,i B,ii

d = w D

LMS update:

A,i A,i A,iw (n+1) = w (n) - μ ε D

B,i B,i B,iw (n+1) = w (n) + μ ε D [3]

May 26, 2015 33 © Yun Chiu

Behavior Simulation Setup

Capacitor mismatch (1st stage, 2nd stage) σ = 1%

1st stage Comparator offset (A) 16 mV

1st stage Comparator offset (B) -18 mV

2nd stage Comparator offset (A) 7 mV

2nd stage Comparator offset (B) -8 mV

1st stage Comparator noise (σ) 1 mV

2nd stage Comparator noise (σ) 0.5 mV

Amplifier output noise (σ) 1 mV

Sampling noise (C=2pF) (σ) 65 μV

Amplifier gain error 2%

May 26, 2015 34 © Yun Chiu

Behavior Simulation Results

0 0.5 1 1.550

60

70

80

90

100

SFDRSNDR

Calibration converges in < 1 million samples

MSamples

[dB

]

May 26, 2015 35 © Yun Chiu

Preliminary Circuit Sim. Results

Corner SNDR (dB) SFDR (dB)TT 82.9 96.9SS 83.2 95.2FF 81.6 88.9LV 82.5 97.6HT 81.6 88.4

HVLT 84.3 99.8

TT w/ noise 76.4, single ADC79.1, average

93.3, single ADC95.3, average

LV/HV: power supply, reference, and common mode ×0.9/1.1

LT/HT: -40ºC/70ºC

May 26, 2015 36 © Yun Chiu

Summary

Thank you for your attendance!

• Features of low power and small die size make the SAR ADC a strong candidate for LAr readout Phase-II Upgrade of the ATLAS experiment.

• With preliminary TID results obtained, our future design will focus on SEE/SEU strategies for analog circuits.

• Architectural redundancy and digital calibration present a viable and efficient way to combat SEE and TID based on our studies.

• Expecting first prototype demonstration in Q2 of 2016.

May 26, 2015 37 © Yun Chiu

References

[1] Y. Zhou, B. Xu, and Y. Chiu, “A 12 bit 160 MS/s two-step SAR ADC with

background bit-weight calibration using a time-domain proximity detector,” IEEE

J. Solid-State Circuits, vol. 50, pp. 920-931, Apr. 2015.

[2] W. Liu, P. Huang, and Y. Chiu, “A 12-bit, 45-MS/s, 3-mW redundant successive-

approximation-register analog-to-digital converter with digital calibration,” IEEE J.

Solid-State Circuits, vol. 46, pp. 2661-2672, Nov. 2011.

[3] S. Sarkar, Y. Zhou, B. Elies, and Y. Chiu, “PN-assisted deterministic digital

background calibration of multistage split-pipelined ADC,” IEEE Trans. Circuits

and Systems I: Regular Papers, vol. 62, pp. 654-661, Mar. 2015.

[4] D. G. Mavis and P. H. Eaton, “SEU and SET modeling and mitigation in deep

submicron technologies,” in Proc. IEEE Int. Rel. Physics Symp., Apr. 2007, pp.

293-305.