Mitglie

d d

er

Helm

holtz-G

em

ein

schaft

A new ADC chip Vulcan for PMT

readout

Next Generation Nucleon Decay and

Neutrino Detectors (NNN‘16)

2-Nov-16 | Christian Grewing

Forschungszentrum Jülich GmbH,

Central Institute of Engineering, Electronics and Analytics - Electronic Systems (ZEA-2)

on behalf of the JUNO Cooperation

Mitglie

d d

er

Helm

holtz-G

em

ein

schaft

2-Nov-16 Christian Grewing NNN'16 2

Juno Detector Introduction

Jiangmen Underground Neutrino Observatory• 20kton Liquid Scintillator in an acrylic sphere

with a stainless steel structure• Detector is in a water filled cavity with ca 720m

overburden (1900m w.e.)• Including: 18,000 20 “ and 36,000 3” PMT• 100m Cable attached to data concentrators

(BEC) on top of the detector • The receiver electronics are attached to the

PMT underwater for:• Lower data bandwidth on the cable• Programmable signal threshold modes• Local data storage (RAM) for supernova

events• Programmable digital signal pre-processing

to further reduce data bandwidth• Intelligent PMT developed together with

several groups in Asia and Europe

GCU

ADU

HV

BIAS

PCU

DAQ

~10

0m

PM

TR

ecei

ver

Elec

tro

nic

s

LiquidScintilator

BEC

Mitglie

d d

er

Helm

holtz-G

em

ein

schaft

GCU

ADU

HV

BIAS

PCU

DAQ

~10

0m

PM

TR

ecei

ver

Elec

tro

nic

s

LiquidScintilator

BEC

2-Nov-16 Christian Grewing NNN'16 3

Receiver Chain Details

BackEnd Electronics (BEC): Université Libre de Bruxelles• Connection between ca 32 receivers to the DAQ and Trigger system• Highspeed data transfer• Reference clocks• Power over Ethernet to supply the PCU

Cables: Institute of High Energy Physics• 100m CAT5 Ethernet cable

Power Control Unit (PCU):RWTH Aachen Experimentalphysik III• Supplying all local electronics• Separating the clock from the powerfeed

Trigger system:Tsinghua University• Global trigger generation

Mitglie

d d

er

Helm

holtz-G

em

ein

schaft

GCU

ADU

HV

BIAS

PCU

DAQ

~10

0m

PM

TR

ecei

ver

Elec

tro

nic

s

LiquidScintilator

BEC

2-Nov-16 Christian Grewing NNN'16 4

Receiver Chain Details cont’d

General Control Unit (GCU): Instituto Nazionale di Fisica Nucleare, Università di Padova• Connection to the BEC and control of the HV and ADU• LVDS signal interface to the ADU• Dedicated fast memory (2GB) for local signal storage (supernova)• Configurable digital processing of the signal and signal over threshold

generation

Analog to Digital conversion Unit (ADU), Vulcan System on Chip: Forschungszentrum Jülich, ZEA-2• Highly linear, low noise receiver• 3 - 8bit, 1Gb/s Flash ADC with programmable characteristics• Programmable data reduction and low jitter clock generation• Configurable trigger schemes, overshoot compensation• All integrated regulators w/o external capacitors for all internal supplies

High Voltage Unit (HV)Joint Institute For Nuclear Research• 2kV Bias Voltage for the bias circuitry of the PMT

Mitglie

d d

er

Helm

holtz-G

em

ein

schaft

GCU

ADU

HV

BIAS

PCU

DAQ

~10

0m

PM

TR

ecei

ver

Elec

tro

nic

s

LiquidScintilator

BEC

2-Nov-16 Christian Grewing NNN'16 5

System Architecture of Vulcan SoC

1. Approx. 80dB linearity by using 3 signal chains for 3 different signal ranges

2. Control loop to suppress DC variations for increased dynamic range and reduced noise

3. On chip clock generation from reference clock

4. No analog delay line, reducing noise and distortions

5. Flexible solution for different applications

6. Overshoot compensation7. No external components

neededSoC is named after Vulcan, the son of Juno in ancient Greek mythology

VULCAN

AU

RX

RX

RX

2.5V

TEST

CU

1.2V

BIAS

Trigger

ADCFrontend

DAC

TIA

ADC

DACADC

REF

overshoot compensation

1

REG

2V5

REG

1V2

BIAS DAC

DAC

REF

DAC

PLL

REG1V2GND

REG2V5GND

3V3VDD

TIAGND

TIAIN

OSCOUT

OSCIN

ADCANAGND

ADCMIXGND

ADCDIGGND

DACGND

TRGOUT

TRGLVL

ADCOUT

ADCREFLVL

BIASLVL

BIASCTRL

TRGCTRL

ADCCTRL

DACIN

OSCCTRL

TIACTRL

DACREF

TRG

OSCGND

ADCTEST

ADCCLK1G

ANA1V2VDD

TESTCTRL

TEST

ANA1V8VDD

3V3VDD

TIAIN

TIAGND

TEST

REG

1V2MIX1V2VDD

MIX1V8VDD

REG

1V2DIG1V2VDD

DIG1V8VDD

2V5VDD

8

1024

8

8

8

Mitglie

d d

er

Helm

holtz-G

em

ein

schaft

VULCANADC3

ADC2

ADC1

CU

HV

GCU

i SIG

NA

L

t

2-Nov-16 Christian Grewing NNN'16 6

Small Signal Mode

1 2 4 8 16 31 64 128 256 512 1024 2048

1 4

16

64

256 ADC High Gain ADC Medium Gain ADC Low Gain

Charge[photo electron; p.e.]

ADC out[]

1b=0.06p.e. 1b=0.4p.e. 1b=8 p.e.

Two signal chains with programmable gainsand parallel TIA inputs, combined input resistance R ≈ 5Ω

Mitglie

d d

er

Helm

holtz-G

em

ein

schaft

2-Nov-16 Christian Grewing NNN'16 7

Large Signal Mode

1 2 4 8 16 31 64 128 256 512 1024 2048

1 4

16

64

256 ADC High Gain ADC Medium Gain ADC Low Gain

Charge[photo electron; p.e.]

ADC out[]

1b=0.06p.e. 1b=0.4p.e. 1b=8 p.e.

With larger input currents >20mA the TIA inputs saturate, the ESD diodes open with a combined resistance R ≈ 5Ω, The voltageover the diodes is measured withthe third signal chain

VULCANADC3

ADC2

ADC1

CU

HV

GCU

i SIG

NA

L

t

vSIGNAL

Mitglie

d d

er

Helm

holtz-G

em

ein

schaft

2-Nov-16 Christian Grewing NNN'16 8

Concept Verification by FE-Prototype

Hamamatsu R12860, dark box, HVand function generator provided byPhysics Institute III B, RWTH Aachen

Demonstrator board containingtwo TIAs, voltage buffer, ADC anddiodes attached to Aachen base

Mitglie

d d

er

Helm

holtz-G

em

ein

schaft

• Best result by high

gain amplifier

(green)

• Low gain amplifier

(blue) and buffer

(yellow) provide

similar signals at

low amplitudes

2-Nov-16 Christian Grewing NNN'16 9

FE-Prototype:

Output Signals @ Low Occupancy

Mitglie

d d

er

Helm

holtz-G

em

ein

schaft

2-Nov-16 Christian Grewing NNN'16 10

FE-Prototype:

Output Signals @ High Occupancy

• High gain amplifier

(green) and low

gain amplifier

(blue) clip

• Buffer (yellow) still

provides useful

output signal

Mitglie

d d

er

Helm

holtz-G

em

ein

schaft

From the Conceptual Design Report (CDR):

• Noise level should be below 0.1 pe for single photoelectron detection.

Vulcan: 8 bit for 16 pe – equivalent input noise of the TIA is much

smaller than one LSB: 𝐼𝑛𝑜𝑖𝑠𝑒 ≪ 𝐿𝑆𝐵.

2-Nov-16 Christian Grewing NNN'16 11

Noise Requirements

ENOB pe Resolution [1/pe]

8 16 0.0625

7,33 16 0.1

7 16 0.125

7 14 0.109

Mitglie

d d

er

Helm

holtz-G

em

ein

schaft

From the Conceptual Design Report (CDR):• Waveform sampling should be available over the whole energy range with a sampling

rate of 1 GS/s.

• Arrival time resolution, e.g. by fitting of the signal leading edge, should be 𝜎𝑡 ≈ 100 ps.

Vulcan: ADC Sampling Clock 500 MHz using both edges

2-Nov-16 Christian Grewing NNN'16 12

Time Resolution Requirements

vref1

vref2

vref3

vref4

vsignal

Integration after sub-ranging with respect to 4 voltage references

QQSE

T

CLR

S RQQ

SET

CLR

S RQQ

SET

CLR

S RQQ

SET

CLR

S R

De

cod

er

QQSE

T

CLR

S RQQ

SET

CLR

S RQQ

SET

CLR

S RQQ

SET

CLR

S R

Dec

ode

r

Mitglie

d d

er

Helm

holtz-G

em

ein

schaft

Initial jitter requirement: 𝑡𝑗 < 100fs

2-Nov-16 Christian Grewing NNN'16 13

Concept Verification by Test-Chip: PLL

Requirement (sim. results) PN spectrum (test-chip)

RMS JITTER ≈ 0.58ps

50K

Mitglie

d d

er

Helm

holtz-G

em

ein

schaft

2-Nov-16 Christian Grewing NNN'16 14

Overshoot Compensation

VULCAN

i SIG

NA

L

t

iSIGNAL iTIAiOvershoot

Ccoup

Rbias

Rin=low

VULCANi S

IGN

AL

t

iSIGNAL iTIAiOvershoot

Ccoup

RbiasCcoup2

vOvershoot vOvershoot2

iOvershoot2

Rbias2

Rin=low

Rin=high

The signal is distorted by the AC coupling at the PMT, causing inter symbol interferences and reducing the signal to noise ratio (Signal Overshoot).

Vulcan features an integrated compensation for the Signal Overshoot:• Sensing the voltage over the bias

resistor• Compensation current is

generated on a copy of the bias resistor

• Needs additional coupling capacitance at the bias resistor

(patented)

Mitglie

d d

er

Helm

holtz-G

em

ein

schaft

2-Nov-16 Christian Grewing NNN'16 15

OSC Implementation VULCAN

Test signal generation

Package and bonding modell

Low gain voltage buffer Medium and high gain TIA Overshoot compensation buffer

Mitglie

d d

er

Helm

holtz-G

em

ein

schaft

-10mA

0 A

10mA

20mA

30mA

40mA

50mA

60mA

70mA

80mA

90mA

0 s 2us 4us 6us 8us 10us 12us 14us 16us 18us 20us

curr

ent

time

Ccap Current

OSC Current

TIAin Current

-400

-200

0

200

400

0 s 2us 4us 6us 8us 10us

curr

ent

(uA

)

time

Ccap CurrentOSC CurrentTIAin Current

2-Nov-16 Christian Grewing NNN'16 16

Special Feature: OSC Sim Results VULCAN

Mitglie

d d

er

Helm

holtz-G

em

ein

schaft

• Start-Up Controller (HAL)

• ADC Regulator (ADC_REF)

• Digital PLL Controller (DIG_PLL)

• Build-In Self Test (BIST)

• ADC Encoder (ADC_ENC)

• Main Data Processing (PAM)

• Trigger Generation (DSP)

• LVDS Multiplexer (LVDS)

2-Nov-16 Christian Grewing NNN'16 17

Features of the Digital Part (CU)

ADUCU AU

RX

PCUPLL

TDC

BIAS

P rogramable A daptiveM emory

Registers

GCU

RA

MS

oC

ADC_REF erence regulation

Dig_ italPLL control

B uild I nS elfT est

16

ADC

REFCLK

DATA<15:0>

3

TRG<2:0>

RXTDC

BIAS

ADC

RXTDC

BIAS

ADC

VDD_3V3

H ead ofA assignedL iabilities

D igitalS ignalP rocessing

PLL_ Controller

AD

C_

En

cod

er

LVD

S_

MU

X

J ointT estA ction G roup controller

A DCP assT hrough

Mitglie

d d

er

Helm

holtz-G

em

ein

schaft

2-Nov-16 Christian Grewing NNN'16 18

Configurable Approach: Signal over Threshhold

0 1 2 3 4 5 6 7 x 10-7-0.024

-0.022

-0.02

-0.018

-0.016

-0.014

-0.012

time [s]

volta

ge

[V]

Input signal and ADC output

bit

[]

0001

0000

0010

0100

0011

0101

0111

0110

1000

integral trigger

analog trigger

digital trigger

ins ignal

adcoutp ut

3 LVDS trigger lines are available one for each of the 3 ADC Configurable trigger modes:

• Analog voltage comparator for fastest trigger• Digital threshold value • Integrating the last 8/16/32 values and compare with digital threshold

Mitglie

d d

er

Helm

holtz-G

em

ein

schaft

• Purpose:

- Select ADC gain mode and buffer data

- Generate meta information (timing, modes, etc.)

- Minimize output data by selecting relevant information

Basic PAM structure:

2-Nov-16 Christian Grewing NNN'16 19

Main Data Processing (PAM)

ADCADC

ADC

ADC Analyzer Ring Buffer(RB)Header gen.

Readout logic

LVDS

4 3 2 3 3 2 2 4

3 5 4 2 5 4 3 3

2 4 6 4 4 6 1 5

4 5 5 8 5 5 6 2

RST

&

HDR

28 31 2 36 833 64 71 23 5 RST

&

HDR42 18 18 97 89 30 165 74 21 7 11

210 94 4 50 86

6 182 47

7

4

186 RST

&

HDR

RST

&

HDR0

2 3

6 04

signal

time

LVDSdata

noise HG mode noiseHG mode MG mode

noise level

threshold HG -> MG

Mitglie

d d

er

Helm

holtz-G

em

ein

schaft

2-Nov-16 Christian Grewing NNN'16 20

Chip Layout and Photo

RX PLL

CU

ADCTIA+OPC

PLL

LDO

DIG

ADC

ADC

LDO

LDO

TIA+OPC

TIA+OPC

Area = 4.5mm * 4.5mmTechnology = 65nm TSMC

Mitglie

d d

er

Helm

holtz-G

em

ein

schaft

• Application Engineering

• Definition of measurements

and verification support

• Examination of redesign

potential / future circuitry

• Review of measurement and

application boards

• Model preparation of digital

part to be used in firmware

development

• Silicon Back estimated mid of November

• Prove of concept measurements (Receiver chain

and PMT) in Q1 2017

2-Nov-16 Christian Grewing NNN'16 21

Current Work and Outlook

By Roger Heil (ForschungszentrumJülich GmbH, ZEA-2)