PMT Readout and Floor TriggeringPMT Readout and Floor Triggering• Charge estimation using the times over the thresholds• Event Building and Triggering

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multiplicity

George BourlisGeorge Bourlis

In the framework of the KM3NeT Design Study

ReadOut Electronics

GPS Input

USB PortTrigger Output5 PMT Signal Inputs

25ps accuracy TDC

HPTDC

• 32 channels (LR) – 8 Channels (HR)

•25ps (HR) to 100 ps (LR) accuracy

•Self Calibrating

Time (ns)

Trigger

Input

The Photomultiplier Tube:

PH: XP1912

Charge (pCb)

Single p.e

Gain vs HV

Calibration

@ “nominal” H.V.

gain: ~ 4 105

<charge>/p.e. ~ 0.07pCb

<pulse height>/p.e. ~ 1.05mV

Rise Time: 1.2 ns

Charge (in units of mean p.e. charge)

At the Detector Center

Data

- Monte Carlo Prediction

Charge versus Time Over ThresholdC

ha

rge

(p

C)

Time Over Threshold (s)

1st Threshold only 1st & 2nd Threshold 1st, 2nd & 3rd Threshold

4mV

50mV

15mV

Charge Parameterization

1st & 2nd Threshold 1st, 2nd & 3rd Threshold

kkCharge= a (tot)

Charge Estimation

1st & 2nd Threshold 1st, 2nd & 3rd Threshold

Measured Charge - Estimated Charged

Measured Charge

11% 8%

- Estimated Resolution ~10%

- Better if all thresholds are crossed

Charge Estimation

1st & 2nd Threshold 1st, 2nd & 3rd Threshold

Measured Charge - Estimated Charged

Estimated Error

- σ=(1.01 ± 0.01) (2 thresholds)

- σ=(1.1 ± 0.1) (3 thresholds)

HPTDC is fed by a 40 MHz clock giving us a basic 25 ns period (coarse count).

A PLL (Phase Locked Loop) device inside the chip doesclock multiplication by a factor 8 (3 bits) to 320 MHz (3.125 ns period) .

A DLL (Delay Locked Loop) done by 32 cells fed by the PLL clock acts a 5 bits hit register for each PLL clock (98 ps width LSB = 3.125 ns/32).

4 R-C delay lines divides each DLL bin in 4 parts (R-C interpolation) in high resolution (25ps) mode.

HPTDC architecture

Trigger Matching Logic

ns