Article

A Design and Theoretical Analysis of a 145 mVto 1.2 V Single-Ended Level Converter Circuit forUltra-Low Power Low Voltage ICs †

Yu Huang 1,2,*, Aatmesh Shrivastava 3, Laura E. Barnes 4 and Benton H. Calhoun 1

1 The Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia,Charlottesville, VA 22904, USA; bcalhoun@virginia.edu

2 Department of Computer Science, University of Virginia, Charlottesville, VA 22904, USA3 PsiKick Inc., Charlottesville, VA 22902, USA; aatmeshshrivastava@gmail.com4 Department of System and Information Engineering, University of Virginia, Charlottesville, VA 22904,

USA; lbarnes@virginia.edu* Correspondence: yh3cf@virginia.edu; Tel.: +1-434-466-1362† Y. Huang, A. Shrivastava and B. H. Calhoun, “A 145 mV to 1.2 V single ended level converter circuit for

ultra-low power low voltage ICs,” SOI-3D-Subthreshold Microelectronics Technology Unified Conference(S3S), 2015 IEEE, Rohnert Park, CA, USA, 2015, pp. 1–3, doi:10.1109/S3S.2015.7333489.

Academic Editor: Steven VitaleReceived: 31 March 2016; Accepted: 16 June 2016; Published: 23 June 2016

Abstract: This paper presents an ultra-low swing level converter with integrated charge pumps thatshows measured conversion in a 130-nm CMOS test chip from an input at a 145-mV swing to a 1.2-Voutput. Lowering the input allowable for a single-ended level converter supports energy harvestingsystems that need to use very low voltages.

Keywords: level converter; charge pump; subthreshold; energy harvesting

1. Introduction

Energy autonomy is a critical feature required to enable the large-scale deployment of ultra-lowpower (ULP) systems in the Internet of things (IoT), with energy harvesting being accepted as a moreviable means to provide power. Modern energy harvesting circuits can now harvest energy frominput voltages as low as 10 mV [1]. However, many challenges face energy harvesting circuits, whichrequire operation at very low power and voltage levels [2]. Figure 1 shows the block diagram of ageneric energy harvesting system. The lifetime of the system depends on the energy stored on theenergy harvesting capacitor C to provide power for the system. At runtime, as the energy storedon C is being consumed, the voltage on the capacitor, VCAP, is decreasing. The voltage at whichthe system stops operating (system threshold voltage) must be brought down to increase systemlifetime. The minimum energy point has been proposed as the most optimal point to operate asystem [3]. However, to maximize the utilization of stored energy on a capacitor, the system needsto operate from the lowest possible voltage. From the energy utilization perspective, the systemthreshold voltage should be brought down as low as possible to make full use of the stored energy.To more fully take advantage of the energy stored on the energy harvesting capacitor, SoCs (systemon chip) under ultra-low voltage have been proposed in [4], which operate below 160 mV. Typical ULP(ultra low power) SoCs frequently use timers to keep the circuit functional, even when the voltageis very low [5]. However, the outputs of these ULP subthreshold circuits also operate at a very lowvoltage level, which causes communication problems with the core voltage levels off-chip or withother peripheral circuits. Level converters are necessary in such a system to interface between thelow voltage domain and the nominal voltage domain. In this paper, we present a low swing level

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converter that can convert from the 100-mV (simulation) and 145-mV (measurement) level inputsignals to 1.2 V using a single-ended charge pump-based topology.

Figure 1. Generic energy harvesting-based SoC. This figure was originally used in [6].

A traditional level converter can convert from nearly 400 mV to 1.2 V via a cross-coupledstage. However, in a low power system, the system life time can be extended by lowering theoperation voltage, the same with the energy consumption. Lower input signals can kill the positivefeedback and prevent conversion with the traditional design. Several low voltage level convertercircuits have been proposed in the literature. A low swing level converter can convert from a rangeof 210 mV to 950 mV to 1.2 V with a bootstrapping technique [7]. A dynamic logic level converter canconvert 300 mV to 2.5 V, which is employed with a clock synchronizer [8]. However, being a dynamiccircuit, it can only operate at higher frequencies and uses higher power and area. A single-endedinterconnect circuit achieves level conversion from 300 mV [9], but it is dynamic and higher power.In [10], a current mirror structure is proposed, which allows the conversion from 200 mV acrosstechnologies. A two-stage ULP level converter can convert from 188 mV to 1.2 V achieving ULPoperation [11]. In this work, we present two design constraints for the main stream cross-coupledlevel converter. Furthermore, we propose a level converter that can potentially convert 100 mV to1.2 V using a charge pump. The charge pump stage increases the swing before level conversion,which helps in initiating the positive feedback. Our measurement results show conversion from145 mV to 1.2 V.

This paper is organized as follows: In Section 2, we discuss two main categories of conversiontechniques for level converter design: amplification-based conversion and boosted swing-basedconversion. In this section, we analyze the level conversion techniques in detail and give twodesign constraints of an amplification-based subthreshold level converter, which is the mainstream.In Section 3, we propose our own work integrating the two techniques introduced in Section 2. We firstintroduce our design architecture and two different designs based on this architecture. We then showthe simulation results of the proposed work. In Section 4, we show the chip fabricated using 130-nmCMOS technology and the measurement results of the proposed designs. Lastly, we compare ourwork with the state-of-the-art in Section 5.

2. Level Conversion Techniques

In this chapter, we discuss the state-of-the-art level conversion techniques in the subthresholddomain. We introduce the level conversion techniques in two categories based on their differentfundamental structure and working mechanisms: amplification-based and boosted swing-based levelconversions. Specifically, we discuss in detail the theoretical analysis of the amplification-basedlevel conversion.

2.1. Amplification-Based Level Conversion

The first main type of level converter design is based on an amplification mechanism that aimsto enhance the pull down network. We will analyze this type of design in this subsection.

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2.1.1. Designs of Amplification-Based Level Converters

Figure 2a,b shows two of the most traditional amplification-based level convertertopologies [12]. Following the naming convention in [10], the level converter shown in Figure 2a isthe conventional cross-coupled level converter (CCLC), and the level converter shown in Figure 2b isthe current mirror-based level converter (CMLC). CCLC is a full-swing design, which can pull up theinput low voltage VDDL up to the high voltage rail VDDH by taking advantage of positive feedback.However, also due to the positive feedback, the conversion capability decreases, because it has tomeet the ratio constraint between the pull up network and pull down network. CMLC uses a basiccurrent mirror. CMLC has a stronger conversion capability due to the level shift using the differentialamplifier action. However, CMLC cannot eliminate the direct current when input is high, which leadsto a higher static power consumption.

(a) (b) (c)

Figure 2. Amplification-based level converter structures. (a) Conventional cross-coupled levelconverter (CCLC); (b) current mirror-based level converter (CMLC); (c) subthreshold level converterwith a Wilson current mirror (WCMLC).

Figure 2c is a design with an Wilson current mirror (WCMLC) [13]. As discussed in the paperand [10], WCMLC is robust, but is not repeatable for the Monte Carlo sizing optimization acrossdifferent technologies. In [14], they used a three-stage design based on the topology in Figure 2a,which is able to convert from 200 mV to 1.2 V. This cascaded design requires three supply voltages andsize adjustment for each of the three intermediate conversion stages, which increases the design andpower management complexity. Based on this work in [14], the authors in [11] proposed a two-stagecross-coupled level converter as in Figure 3. They added an NMOS header in the first stage to weakenthe pull up network (PUN) to enhance the conversion of the shifter. This simplified the design of [14]and achieves the conversion from 188 mV in the subthreshold. In this paper, we will note this designas a two-stage CCLC (TSCCLC), as in [10].

Figure 3. Two-stage CCLC (TSCCLC).

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2.1.2. Theoretical Analysis of Amplification-Based Level Converters

We will discuss two design constraints here using the example of CCLC: the sufficient conversioncondition and balanced switching condition. We will prove that the latter gives a stronger designconstraint. We will perform all of the analysis based on the notation in Figure 4. Finally, we discussthe drawbacks of CMLC.

Figure 4. Design constraint analysis of CCLC.

Sufficient Conversion Condition for CCLC

The essential point of a subthreshold amplification-based level converter design is to adjust theratio of the pull up network and pull down network, so that the pull down network is strong enoughto achieve the conversion when the input is ‘high’ in the subthreshold. As in CCLC, we perform aspecific analysis of the design constraints for a sufficient conversion in the subthreshold, as markedin Figure 4.

In the analysis, we use Vtn and Vtp to represent the threshold voltage for NMOS andPMOS, respectively. kn and kp are the gain factor of NMOS and PMOS, while ksn and ks p arefor the subthreshold. When input switches from ‘low’ to ‘high’, at this moment, V1 is VDDH , so M1

works in saturation region:

I1 = kn(Vgs − Vtn)2 = kn(VDDL − Vtn)

2 (1)

I3 works in linear region:

I3 = kp((VDDH − V2 − Vtp)(VDDH − V1)− (VDDH − V1)2) (2)

M2 and M4 are off, so we get I2 and I4:

I2 = IDP0WL

eqVgsnkT = kspe

q(VDDH−V1)nkT (3)

I4 = IDN0WL

ekBqVgs

nkT = ksn (4)

For a successful conversion, when input switches from ‘low’ to ‘high’, the pull up networkshould be able to overcome the pull down network at node V2 to break the internal equilibriumand trigger the positive feedback:

I2 ≥ I4 (5)

Represent I2 and I4 by Equations (3) and (4):

kspeq(VDDH−V1)

nkT ≥ ksn (6)

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Thus, for the minimum scenario:

qVDDH − V1

nkT= ln

ksn

ksp(7)

Then, we get:

VDDH − V1 =nkT

qln

ksn

ksp(8)

Assuming that in subthreshold region, the leakage very slowly charges CL (on the right part ofCCLC), V2 will not rise fast and stays close to zero, and V1 will stay close to VDDH .

Thus, in Equation (2), let V2 = 0:

I3 = kp(VDDH − Vtp)(VDDH − V1) (9)

The sufficient condition for a successful conversion is to break the equilibrium between the pullup network and pull down network and be able to pull down V1:

I1 ≥ I3 (10)

Take Equations (1) and (9). Thus:

kn(VDDL − Vtn)2 ≥ kp(VDDH − Vtp)(VDDH − V1) (11)

Then, take Equation (8) into Equation (11), we get the final sufficient condition for a conversion:

kn

kp≥

VDDH − Vtp

(VDDL − Vtn)2nkT

qln

ksn

ksp(12)

Equation (12) shows that NMOS and PMOS cannot be arbitrarily sized to get the desired ratio forkn and kp, because the sizing of NMOS and PMOS also determines the ratio of ksn and ksp at the sametime. Therefore, the cross-coupled level converter (CCLC) cannot be used reliably for subthresholdoperations, as the subthreshold leakage plays a part in triggering the positive feedback.

Balanced Switching Condition for CCLC

In a level converter design, to get a balance of rising and falling time (i.e., tLH = tHL), we mustconsider the following constraint:

I2 = CLdV2

dt(13)

Additionally, at the same time, I2 is:

I2 = kp(VDDH − V1 − Vtp)2 (14)

Thus, we get:

CLdV2

dt= kp(VDDH − V1 − Vtp)

2 (15)

Similarly for I1L, we have:

I1L = kn(VDDL − Vtn)2 − kp(VDDH − V1 − Vtp)

2 (16)

Additionally:

I1L = CLdV1

dt(17)

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Therefore, we get:

CLdV1

dt= kn(VDDL − Vtn)

2 − kp(VDDH − V1 − Vtp)2 (18)

Let dt = dt using Equations (15) and (18):

[kn(VDDL − Vtn)2 − kp(VDDH − V1 − Vtp)

2]dV2 = kp(VDDH − V1 − Vtp)2dV1 (19)

In a balance design where tLH = tHL, when V1 changes from zero to VDDH , V2 changes fromVDDH to zero. Take this into Equation (19):

∫ 0

VDDH

[kn(VDDL − Vtn)2 − kp(VDDH − V2 − Vtp)

2]dV2 =∫ VDDH

0kp(VDDH − V1 − Vtp)

2dV1 (20)

Solve Equation (20); we get the design constraint for a subthreshold balanced level converter:

kn

kp=

2VDDH(VDDH − Vtp)

(VDDL − Vtn)2 (21)

The balance design constraint Equation (21) is a much stronger bound than the sufficientconversion constraint Equation (12). In other words, it is more difficult to make a subthreshold levelconverter with an equal rising and falling time. The bound of Equation (12) gives a design constraintof a successful conversion, but cannot guarantee the balance of switching performance.

Drawback of CMLC

In the current mirror design (CMLC), the biggest problem is the direct current and the slowconversion in the subthreshold. We will do a simple analysis using Figure 5.

Figure 5. Drawback analysis of CMLC.

When input is ‘high’ (VDDL), M1 works in the saturation region:

I1 = kn(Vgs − Vtn)2 = kn(VDDL − Vtn)

2 (22)

However, in the subthreshold, the case in Equation (22) will be:

I1 = ksneqVDDL

nkT (23)

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With the existence of the current mirror, we also have:

I1 = CVDDHTrise

(24)

Combine Equations (23) and (24):

Trise =CLVDDH

ksn1

eqVDDL

nkT

(25)

From Equation (25), a current mirror level converter has a very slow conversion in thesubthreshold (low VDDL). This is the biggest bottleneck of this kind of design.

2.2. Boosted Swing-Based Level Conversion

The other type of level converter is the boosted swing-based level converter. Different withamplification-based level converters, boosted swing-based conversions happen by pulling the ‘high’input signal higher first through boosting techniques. This is usually achieved by taking advantageof the characteristics of a capacitor.

Designs of Boosted Swing-Based Level Converters

Figure 6 is a design based on the bootstrapping effect as reported in [15], lrc-converter as calledin [7]. The drivers are enhanced by the bootstrapping techniques through the capacitor Cb. In aboosted swing-based level converter like Figure 6, when the input is low, the output is pulled up toVDDH by M4. The left plate of Cb is ‘0’, and the right plate is pulled up to VDDL by M0. When theinput is high (VDDL), M2 passes a ‘0’ to M0’s gate and turns it on, while M1 is turned on at the sametime. In this phase, the left plate of Cb is pulled up from zero to VDDL (in the previous phase), andthe right plate is pulled up from VDDL to 2× VDDL. The boosted 2× VDDL is passed to the gate ofM4. In order to pull down the output to zero, it has to meet this condition to turn off M4 completely:

2×VDDL > VDDH (26)

Figure 6. Boosted swing-based level converter structure [15].

If this condition is not met, it will result in static current through M4. This design requirestwo power supplies, VDDH and VDDL, which increases the design complexity. In conclusion,the major problem of this level converter design is that it is dynamic and only works at high frequency.

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For example in Figure 6, the gate of M4 will slowly decrease to VDDL at a lower frequency of signals,which causes high static current.

The proposed work in [7] is based on the same bootstrapping effects and reduced the circuitcomplexity with an improvement of power and delay. A similar design is proposed in [9]. The boostedswing-based design is usually preferred in the interconnect design to work with reducing the powerconsumption or re-boost the signals to communicate with the core chip.

3. Proposed Low Voltage Level Converter

In this section, we introduce our proposed low power subthreshold single-ended levelconverter. Our design is based on both the amplification-based and boosted swing-based conversiontechniques. The combination of the two design types of level converters achieves a strongerconversion capability that allows a deeper application in subthreshold ICs. This proposeddesign uses a two-staged architecture: boosting stage and conversion stage. The boosting stageis implemented with a subthreshold charge pump design, while the conversion stage uses theamplification-based techniques.

First, we propose the boosting part: a subthreshold charge pump. Next, we introduce our uniformdesign architecture, which takes advantage of this subthreshold charge pump. According to thearchitecture, we introduce two level converter designs and show the simulation results accordingly.

3.1. Subthreshold Charge Pump

Figure 7 shows the schematic of a 2× charge pump used in the proposed work and its sizing.When VIN is low, M1 turns on, which turns on M3. X is pulled up to VDDL, while B is pulled down toGND by the inverter connected to it. Next, VIN goes high and turns on M2 and M5, which leads to theup-conversion of B from zero to VDDL. Since X was charged to VDDL previously, the up-conversionof B causes X to go from VDDL to 2× VDDL at the output of the charge pump. In this design, M4

works as a capacitor to implement the boosting.

Figure 7. Schematic of the 2× charge pump used in the proposed work.

In deep subthreshold operation with a VDD between 100 mV and 300 mV, node X falls ideallyat 200 mV and 600 mV, respectively. However, in the subthreshold, the low slew rate prevents a fulldoubling of voltage when VDD is very low (<200 mV) because of the higher discharge caused byleakage. Thus, we enhanced the pull down network. In this charge pump design, we do not requirean additional body bias control circuit.

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3.2. Implementation of the Proposed Level Converter

We propose two designs that use charge pump outputs to drive a traditional level converterCCLC, as in Figure 2a, and the improved two-stage amplification-based level converter from [11], asin Figure 3, respectively. We call the former proposed level converter the charge pump boosted levelconverter (CPBLC) in the rest of the paper, and we call the latter proposed level converter the chargepump boosted ultra-low swing level converter (CPBULS). Following the same naming convention,we use ULS to represent TSCCLC in the following comparison to simplify the relationship betweendifferent structures.

Uniform Architecture

Figure 8 shows the architecture of the proposed topology, which combines two charge pumpsand a level converter design. The first stage provides the differential inputs doubled by the 2× chargepumps. The second stage is a cross-coupled differential inverter (e.g., the level converter designsin Figure 2) that restores the final output to full swing (zero to VDDH). The output of the charge pumpstage overpowers the equilibrium of the second stage and drives the PMOS to pull up the internalnode (e.g., A or B in Figure 2a and triggers the positive feedback within the conversion stage).

Figure 8. Architecture of the proposed level converter.

3.3. CPBLC and CPBULS

Deriving from the same proposed architecture, we use the boosting power of the subthresholdcharge pump to trigger the conversion. We will omit the schematic of CPBLC and CPBULS, sincetheir second stages have the same structure of CCLC as in Figure 2a and TSCCLC as in Figure 3.

Simulations

In Figure 9, it shows the functional waveform of CPBULS from the simulation of a VDDLof 120 mV. In fact, CPBLC works in a similar way. The signals labeled in Figure 9 correspondto the signals in Figure 8. As VIN goes high or goes low, one of the charge pump outputs, e.g.,CPOUT , increases and thus initiates the positive feedback in the conversion stage, resulting inthe amplification-based voltage conversion. From observation, when VIN just reaches its highestvalue (120 mV), the conversion cannot be successfully triggered. Instead, the boosting stage takesin VIN and pulls it up to 200 mV from 120 mV, as shown as CPOUT . When CPOUT is boostedto around 200 mV, the voltage conversion of the second stage successfully happens. This is asexplained in Section 2: the boosted CPOUT successfully satisfies the sufficient conversion constraintin Equation (12). In other words, the boosting stage lowers the constraint of a sufficient conversionfor the same amplification-based level converter design. Furthermore, in Figure 9, we can see thatCPOUT will slowly decrease to VDDL, as well, like the design in Figure 6. However, the difference is,in our design, this will not cause static current.

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Figure 9. Functional waveform of charge pump boosted ultra-low swing level converter (CPBULS).This figure was originally used in [6].

Figure 10 shows the minimum input swing results of 100 Monte Carlo simulations for CPBULS,CPBLC and ULS level converters. The charge pump technique decreases the minimum operatingvoltage of [11] (TSCCLC), further lowered down to an average of 128 mV, while the best case (amongthe 100 iterations) is 99.6 mV in CPBULS and an average of 171 mV in CPBLC.

100 110 120 130 140 150 160 1700

5

10

15

20

25

Min VDDL (mV)

Number

ofPoints

µ = 128mV

σ = 11mV

(a)

150 160 170 180 1900

2

4

6

8

10

12

14

Min VDDL (mV)

Number

ofPoints

µ = 198mVσ = 3.3mV

(b)

140 160 180 200 220 240 2600

2

4

6

8

10

12

14

Min VDDL (mV)

Number

ofPoints

µ = 197mV

σ = 21mV

(c)

Figure 10. Monte Carlo simulation results of the minimum input voltage of (a) CPBULS, (b) chargepump boosted level converter (CPBLC) and (c) ULS level converters (100 iterations).

Figure 11 shows the simulation results of the minimum input voltage of CPBULS (red) andCPBLC (blue) level converters under different temperatures. At −20 ◦C, CPBULS and CPBLC canwork at 145.4 mV and 192.8 mV respectively, while at 100 ◦C, they can work at 116.4 mV and 144.3 mV,respectively. Simulation shows that our charge pump-based level converter has lower temperaturedependence for the minimum operating voltage.

Figure 11. Simulation results of the minimum input voltage vs. temperature of CPBULS and CPBLClevel converters. This figure was originally used in [6].

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The proposed design was fabricated in a 130-nm CMOS process. Figure 12 shows the die photoof the test chip. The subthreshold charge pump takes 280 µm2, while CPBLC and CPBULS takearound 466 µm2 with an unoptimized layout design and necessary peripheral circuits.

Figure 12. Die photo of the fabricated chip under 130-nm technology. This figure was originally usedin [6].

4. Measurements

Figure 13 shows the measurements of the 2× charge pump from 15 chips, which starts workingfrom a 170-mV input in the worst case. We show the simulation result together with the measurementresults: the blue lines are the measurement results, while the red line is from simulation. After VIN ishigher than 200 mV, the boosting factor is stable at 2×.

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50

0.2

0.4

0.6

0.8

1

VIN (V)

VO

UT

(V

)

CPmeasure

CPsim

Figure 13. Simulation and measurement results of the input vs. output voltage of the charge pumpstage of the level converter. This figure was originally used in [6].

Figure 14 shows the measurement results of the minimum operational input swing for CPBULS,CPBLC and ULS level converters across the 15 chips. The CPBULS can achieve a mean minimuminput voltage of 157 mV, while the CPBLC achieves the same at 198 mV. The CPBULS can reach alowest input voltage of 145 mV. The limitation of this design is slower transition times that lead tohigher energy per conversion due to the extra leakage.

Figure 15 shows the energy-delay measurement of CPBLC and CPBULS across 15 fabricatedchips. The measurements were taken at three points: 200 mV, 300 mV and 500 mV. CPBLC andCPBULS can operate with a frequency of 35.6 kHz (28 us) and 50.1 kHz (19.96 us), respectively,at 200 mV for the best case, with a mean value of 12.8 kHz and 22.0 kHz, respectively. The bestoperation frequency is 66.9 kHz and 136.6 kHz at 300 mV, 109.7 kHz and 139.4 kHz at 500 mV,for CPBLC and CPBULS, respectively. As the operation voltage increases, the delay decreases,

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which is expected in an energy harvesting system where the worst case is when the operationvoltage is the lowest. In the subthreshold energy harvesting system, there is much voltage variation.The proposed work is designed for an unregulated power supply, which can still successfully workin the worst cases (also known as when the operation voltage goes very low). From the measurementresults of the 15 chips we fabricated, the best EDP value is 0.0015 pJ·ms for CPBLC and 0.0006 pJ·msfor CPBULS.

145 149 153 157 161 1650

1

2

3

4

5

Min VDDL (mV)

Number

ofChips

µ = 157mVσ = 6mV

(a)

190 192 194 196 198 200 202 2040

1

2

3

4

Min VDDL (mV)

Number

ofChips

µ = 198mVσ = 3.3mV

(b)

180 190 200 210 220 2300

0.5

1

1.5

2

2.5

3

Min VDDL (mV)

Number

ofChips

µ = 205mVσ = 15mV

(c)

Figure 14. Measurement results of the minimum input voltage of (a) CPBULS, (b) CPBLC and (c) ULSlevel converters.

0 0.05 0.1 0.15 0.2 0.25 0.3

Delay(ms)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

En

erg

y P

er

co

nve

rsio

n (

pJ)

EDP@200mV, 300mV, 500mV, CPBLC

(a)

0 0.02 0.04 0.06 0.08 0.1

Delay(ms)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

En

erg

y P

er

co

nve

rsio

n (

pJ)

EDP@200mV, 300mV, 500mV, CPBULS

(b)

Figure 15. Energy-delay for (a) CPBLC and (b) CPBULS from measurement across 15 chips.

Another source of variation, the process, can also affect the behavior of this design. As inFigure 7, in the subthreshold, the low slew rate results in that node X cannot be charged to 2× VDDLdue to the discharge caused by leakage. Thus, in the slow-fast corner, the discharge will furtheraffect the boosting of X; and vice versa, in the fast-slow corner, the discharge is weakened; thus, theboosting is enhanced. For the same reason, as in Figure 7, we enhanced the pull down network.

5. Conclusions

This proposed level converter design is based on a subthreshold charge pump design, as shownin Figure 7. Due to the charge and discharge time of M4, the capacitor, its performance is not as goodas conventional level converters at their operating voltages (300 to 400 mV). However, this design isa better choice for an ultra-low power energy harvesting system where performance is not the firstpriority, but the ability of using stored energy is instead, as discussed in Section 1. Thus, we try tomake more use of the energy collected in the capacitor in Figure 1. The challenge is, the lower thelevel converter can operate at, the more energy the system can use to obtain a longer lifetime.

Table 1 compares prior work, both simulations and chip measurements. This proposed chargepump-based level converter CPBULS up-converts reliably from 145 mV to 1.2 V, which is a wider

J. Low Power Electron. Appl. 2016, 6, 11 13 of 14

conversion range. The best energy per conversion is reported as 10 fJ in [10] from simulation resultswith a 90-nm technology. This work has a relatively lower maximum operating frequency with thelowest input swing, but achieves 1.2 pJ energy per conversion, which is 30% less than that in [8] fromchip measurement and a 2× conversion ability. This proposed work can further improve the energyutilization of an ultra-low power system, such as an energy harvesting system.

Table 1. Comparison between the proposed work and prior work.

[11] [10] [16] [8] This Work

Minimum VDDL 188 mV 200 mV 400 mV 300 mV 145 mVEnergy/bit - 10 fJ 327 fJ 1.7 pJ 1.2 pJ

Chip/simulation Chip Sim Sim Chip ChipMaximum frequency 17.3 MHz 10 MHz 1 MHz 8 MHz 8 kHz

Area (um2) - - 120.9 112,000 466Technology 130 nm 90 nm 180 nm 130 nm 130 nm

Acknowledgments: We thank Kevin Leach for his help improving the writing of the paper, providing figuresand giving his valuable suggestions.

Author Contributions: Yu Huang was responsible for authoring this paper, as well as the design and test of thecircuits described here. Aatmesh Shrivastava helped with the theoretical analysis and the design of the circuit.Aatmesh Shrivastava and Benton H. Calhoun helped to guide this research, review the proposed circuits and editthis paper. Laura E. Barnes reviewed this paper.

Conflicts of Interest: The authors declare no conflict of interest.

Abbreviations

The following abbreviations are used in this manuscript:

ULP Ultra low powerIoT Internet of thingsSoC System on chipCCLC Cross-coupled level converterCMLC Current mirror-based level converterWCMLC Wilson current mirror level converterPUN Pull up networkPDN Pull down networkTSCCLC/ULS Two-stage cross-coupled level converterCPBLC Charge pump boosted level converterCPBULS Charge pump boosted ultra-low swing level converter

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