96 Journ JAICSP Trans

7/25/2019 96 Journ JAICSP Trans

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ANALOG INTEGRATED

CIRCUITS ANDSIGNAL PROCESSING

An International Journal

Volume 9, No.2, March 1996

Translinear Circuits in Subthreshold MOS . . . . . . . . . . . . . . Andreas G.Andreou and KwabenaA. Boahen' 141


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Analog Integrated Circuits and Signal Processing, 9, 141-166 (1996)@ 1996 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.

Translinear Circuits in Subthreshold MOS

ANDREAS G. ANDREOU

Electrical and Computer Engineering, Johns Hopkins University, BaltimoreMD21218 USA

KWABENA A. BOAHEN

Computation and Neural Systems, California Instituteof Technology, Pasadena CA91125

USA

Abstract. In this paper we provide an overview of translinear circuit design using MOS transistors operating in

subthreshold region. We contrast the bipolar and MOS subthreshold characteristics and extend the translinear

principle to the subthreshold MOS ohmic region through a draidsource current decomposition. A fronthack-gatecurrent decomposition is adopted; this facilitates the analysis of translinear loops, including multiple input floating

gate MOS transistors. Circuit examples drawn from working systems designed and fabricated in standard digital

CMOS oriented process are used as vehicles to illustrate key design considerations, systematic analysis procedures,and limitations imposed by the structure and physics of MOS transistors. Finally, we present the design of an analog

VLSI translinear system with over 590,000transistors in subthreshold CMOS. This performs phototransduction,amplification, edge enhancement and local gain control at the pixel level. \

1. Introduction form of the translinear principle was recently proposed


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142 A. G.Andreou andK.A. Boahen

In this paper, we discussexperimentalcircuit designs

based on the translinear properties of subthresholdMOS transistors in the saturation and ohmic regions.

Our objective is to present a comprehensive overviewon this subject, beginning with the basic devices and

circuits, and following it through to the system level.

The discussion of subthreshold MOS models, and their

characteristics and limitations can be found in other ex-cellent references (for example [5],

[6] ) .

However, a

basic review of subthreshold MOS and bipolar oper-

ation, is provided since the large signal properties ofthe devices arekey to the subject matter. Most of the

circuit examples given, have been used in analog LSI

and VLSI systems that have been fabricated and tested

functional. The value of these circuits can only be

fully appreciated in the context of the systems that em-ploy them; references to the original journal articles

are given.The paper is divided into six sections. Section2con-

trasts the translinear properties of bipolar transistorswith those of MOS transistors in subthreshold. Basic

circuit techniques that employ MOS transistors in sub-threshold saturation and ohmic regimes are introduced

in section 3. In the same section, we discuss bothtranslinear loops (TL,) composed of generalized diodes

/

diode-like behavior, i.e., increasing the voltage on oneterminal is exactly equivalent to decreasing the voltage

on the other terminal by the same amount. In this

case, a loop of such devices consists of voltage dropsacross pairs of control terminals and we exploit the

linear transconductance-current relationship. Bipolar

transistors have both properties whereas MOSFETs do

not.The large-signal device model equations for both

the bipolar transistor and MOSFET in subthreshold

are discussed in Appendix A where the approxima-tions made during their derivations are clearly stated

and the symbols are defined. In the active-forward re-gion of operation, the function of a bipolar transistor

as a transconductanceamplijer is captured by the fol-

lowing equation:

V B V E

IC = Is e VI (1)

where V, = ( k T / q )and is^ is defined in Appendix A.The magnitude of the transconductance from the

base is identical to the magnitude of the transconduc-tance from the emitter:

a I C


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Translinear Circuits in Subthreshold MOS 143

0.5 1 1.5 2 2.5VGS, VBE [Volts]

Fig. I. Measured current ZDS and Zc versus controlling voltage

VGS

andVBE

respectively. The MOS transistor has dimensions of(16 x 16pm2) and is fabricated in a 1.2pm n-well CMOSprocessand is biased at a drain-source voltage, V~s=1.5Volts. The currentis measured at two different substrate voltage bias conditions. The

bipolar transistor is a vertical device with an emitter area of (16 x16pm2)

fabricated in a 2pm n-well CMOSprocess and biased withVc~z1.5

Volts. T=

301.5 K.

It should be pointed out that the voltage difference

that controls the current in a MOSFET to yield the

Equation4 can be re-written as a function of dimen-sionless current quantities i G and i g . Each of these

currents would correspond to the device current if the

surface potential @S could assume the voltage at thegate or bulk terminal. In essence these currents corre-spond to ideal diode junctions between the source and

surface potential weighted by the appropriate capaci-tive divider ratio. Therefore, the equation for the draincurrent can be written as:

In subsequent sections, we will see how the latterformulation facilitates the analysis of MOS translinear

circuits and an extension of it will be used to analyze

FGMOS translinear loops. Since the dimensioneless

current quantities are related to the surface potential

the will be called @-currentsorpsi-currents.

The transconductance from the gate is given by:

IK

I D S

gm

EZ

-

--

vt

( 6 )

a

V,, vS=c

and from the local substrate (backgate) terminal:


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G

P

C

b

E

Fig.2. (a) Symbol for an NMOS transistor. The current between thedrain and source is controlled by the difference between the surface

potential and the potential at the source terminal. The surfacepotential is set by the potential at the gate and bulk terminalsthrough the capacitive divider between C,, and c&pshown in (b).AnNPNbipolar transistor is shown in (C).The current between thecollector and emitter is controlled by the voltage difference between

in the elements connected in the Clockwise

(CW) direction is equal to the correspond-ing product for elements connected in the

Counter Clockwise (CCW) direction.

As an example let us consider the circuit of Figure 4consisting of four ideal diodes in the loop X-Z-Y-W-

X. Following the translinear principle, we can write:

Note that the translinear principle is derived by be-ginning with Kirchoffs voltage law or the principle of

conservation of energy, so that:

i = N / 2 i = N / 2

C

V D ( 2 i - 1 ) -C

V D ( 2 i ) =0 (1 1)

i=l i=l

Equation 10follows from Equation 11if the voltages

are summed around loops of translinear devices.

In a circuit graph composed of two terminal elements

such as ideal diodes (see Figure 4), there is a direct re-lationship between the voltage difference among each

pair of nodes transversedby the translineardevice and


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VBE WOllSl

Fig. 3.Normalized transconductance curves. The transconductanceis computed through numerical differentiationof the data in Figure 1,and subsequent smoothing. (Top) For the MOS transistor; (Bottom)for the bipolar transistor. The dramatic decreaseof the transconduc-tance in the MOS transistor at low gate-source voltages is attributedto the leakage current.

proposedandexperimentallydemonstratedrecentlyby

Fig. 4. A Translinear loop using ideal p-n junctions (diodes).

S


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146 A. G.Andreou andK. A. Boahen

In Out Ijunctions and obtain

I ut

Fig.6. The translinear loop of Figure4, implemented using compos-ite bipolar and subthresholdMOS transistors. The loop is employedin a current conveyor configuration where the bidrectional outputcurrent Zout equals to the bidirectional current l i n .

or

The above relationship can also be derived by sum-ming the voltages around the loop (conservation of en-

ergy)

V1 +V2 - V3 - V4 = o

Replacing the gate-source voltages forM l ,M2, M3, M4with their respective drain-source currents using Eq. (9)(assuming all devices are in saturation, have VSB = O,have negligible drain conductance, have identical K ,

have identical IOand geometry S) , we obtain:

or


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I II

Vbias III

II A

Fig. 8. A four transistor translinear circuit that performs a one-quadrant normalized multiplication and exploits the back-gate in anMOS transistor. Device pairs Ml, M3 and M2 , M4 share localsubstrate terminals (in this case n-wells). 11 ,

12

and 13 are the inputsand 14 is the output.

for thepsi-currents introduced in Equation 5:

M2

A

'2

F

M5

Fig.9. Circuit that converts a bidirectional current on a single wireinto two unidirectional currents on separate wires. This is a current-mode absolute value circuit. The sign of the bidirectional inputcurrent is assumed to be positive when it adds positive charge tonode C . The bidirectional current Z B D is the input, the unidirectionalcurrents and 12 are the outputs, and Z B sets the operating point ofthe circuit.

was assumed to be the same for all transistors. An-other implicit assumption here is that the gate voltage

is approximately the same for all transistors.

Our next example addresses the problem of con-


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Vdd and

Fig.10. A translinear circuit that computes the normalized differenceof two current signals. II and 2 are the inputs and the bidirectionalcurrent Zout is the output normalized to 11+ 12.

tained by connecting the two output wires together in

which case:

This circuit has been employed in a CMOS integra-

AI* =I B

-AI

Ii

n

similarly for AI* I3 - 4 , I B E 3+14.The differ-ential output current AI* is a scaled version of the dif-ferential input currentAI . The voltage between node

B and Vdd should be such that the current source I Bstays in saturation.

The mirror composed of transistors M5andM6con-

verts the unidirectional differential signal AI to thebidirectional signal Iout so that:

AIIout

= I B -

i n

3.1.2. Analysis of Circuits with MOS Transistors inthe Ohmic Regime In this subsection, we extend the

translinear principle to subthreshold MOS transistorsoperating in the ohmic region. In Appendix A, (see

Fig. 25), we show how the source-drain current of aMOS transistor can be decomposed into a source com-

ponent I Q ~and a drain component I Q ~ ,and that thesecomponents superimpose linearly to yield the actual

current ISD Ies- Q ~ .In the ohmic region these components are compa-


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Fig. II. A translinear circuit that employs subthresholdMOS tran-sistors in saturation and ohmic regime and computes the product oftwo input currents 11 and 12 normalized to 11+ 12

To demonstrate the application of the translinearprinciple to circuits that include MOS transistors in

the ohmic regime, consider the one-quadrant current-correlator circuit in Fig. 11. Transistor

M2

operates in

the ohmic region. Proper circuit operation requires that

the output voltage is high enough to keepM3 in satura-tion. This circuit was first introduced by Delbrck [27]

GND

Fig. 12. A current-mode circuit -translinear network- that imple-ments a

normalized

cubic non-linearity. 11 is the input,12

is theoutput and the voltage source VR normalizes the result.

and (20), the output current is given by:

Il 4

=-


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T

81

a a

GNDe

Fig. 13. A translinear circuit using FGMOS transistors to compute

the ratio of a cubic to square functions. 11 and 12 are the inputs and

13 is the output.

input current is I I , the output current is12 ,

and VR is

a constant voltage source, application of the translin-

ear principle around the loop (GND-A-B-C-D-GND)yields:

An expression for the output currentI3

can be ob-tained by applying the translinear principle around

three loops that include the floating gates and source of

transistorM 3 together with the floating gate nodes andsources of the other transistors. When the three loops

are traversed, the following equations forpsi-currents

are obtained:

i3a = i2a

i3a

=

l a

(25)

i 3 b = i l b

We have adopted a notation where for example, i3a

denotes thepsi-current in device 3 controlled by thevoltage on its gate a. Using Equation 24, the current atthe source of

M1 M 2 , M 3 ,

can be expressed as functions

ofpsi-currents so that:

where the devices are assumed to have the same S

and I n o ; the back-gate contribution to the current ineach device is eliminated as all transistors have the


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Fig. 14. A BiCMOS translinear network that exploits the MOSsubthreshold ohmic characteristics.

Using the adopted conventions for current decompo-sition in NMOS transistors (see Figure 25), I Q ~and

I Q d

together with Equation 28 we obtain the following ex-

This is a lumped parameter model where G1 and G2

correspond to resistances per unit length. The voltageson nodes P and Q referenced to ground, represent thestate of the network and can be read out using a differ-

ential amplifier with the negative input grounded.The equivalent circuit using idealized non-linear

conductances is shown in Figure 15(right). The dif-ference in currents through the diodes D1 and D2 are

linearly related to the current through the dimsor MOS

transistor.' This relationship can be derived from Equa-

tion 55 describing subthreshold conduction, and theideal diode characteristics where ID= I s exp[VD/ Vt].

An expression can be derived for the current IPQin

terms of the currentsI p

and IQ, the reference voltage

V, and the bias voltage V,, when diodes are replaced

by transistors:

The current In0 and S is the zero intercept currentand geometry factor respectively for the diffusor tran-sistor M h . I s is the reverse saturation current for the

diode that is assumed to be ideal. The currents in these

circuits are identical if


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Fig. 15. Building blocks for linear loaded networks.Using

segments that employ ideal (left) linear and (right) non-linear elements.

P Pwhere s h and

Sv

are geometry parametersfortransistors

M h

andM, , respectively.The one dimensional MOS transistor-only network

corresponding to the Helmholtz equation shown in Fig-

ure 17can model the averaging that occurs at the hori-zontal cells layer of the outer retina. This is equation is

the basis of the well known silicon retina architecture

proposed by Mahowald and Mead [34], [7].

Summing the currents at node j we get:


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Translinear Circuits in SubthresholdMOS 153

Fig.17. A one-dimensionalMOS translinear network to perform local aggregation-

spatial averaging-

. The back-gate terminals of all devicesare connected to the substrate.

have used the chargelcurrent-based formulation first

proposed in [151to explain its behaviour. This&ment-mode approach relies an intuitive understanding of the

device physics and yielded the insight which enabled

us to extend the translinear principle to subthresholdMOS transistors in the ohmic region as well as the de-composition of the current into dimensioneless com-

ponents corresponding to ideal junction. We now havea comprehensivecurrent-mode approach for ailalyz-

ing subthreshold MOS circuits. The essence of thisapproach is the representation of variables and param-

eters by charge, current, and diffusivity. Voltages and


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vices sharing common gate and comrnon substrate (see

Figure25 .)

However, to account for the near exact operation

of the multiplier in Figure 8,Vittozs argument must beextended to include loops that go through the back gate

of the MOS transistors as illustrated in Figure 18. Theglobal substrate restriction can thus be removed and

replaced by a local substrate connection, and the resultstill holds true. In a standard CMOSprocess, this willof course be possible only for one type of devices.

Now, we will re-examine the operation of the circuits

in Figure 10,Figure 8, and Figure 1l .Consider the largest loop (A-B-C-D-A) in Fig-

ure 10. Devices M1 and M2 have common gate andcommon bulk and so do devices M3 and M+ When

adjacent devices are paired in different ways we ob-serve thatM3 and M2 share the same source and bulkwhich is the case also for M1 and M4.

In the the largest loop (A-

B-

C-

D-

A) of translinearmultiplier circuit of Figure 8 in we can verify that tran-

sistorsM1 and M2 as well asM3 and M 4 share commongate and source. The alternative pairing, finds M 4 andM2 sharing same bulk and source which is also the case

forM3 and M l .

When devices in the loop are operating in the ohmic

regime such as in the circuit of Figure 11 we can

is accomplished in two separate steps. First the light

intensity is recorded through a standard imager such

as a CCD camera. The intensity field is subsequently

processed outside the camera to discard any absolute lu-minance information and form a representation whereonly relative illumination, i.e. contrast,is retained. Ad-

ditional processing such as edge extraction and or lowbit-rate encoding may follow. However, even thoughthe precision necessary for these tasks rarely exceeds8bits, the signal itself has a very large dynamic range,many orders of magnitude, which makes the problem

difficult. This issue becomes acute when the illumina-tion varies within a single frame something not uncom-

mon in natural scenes (see Figure 19). The detrimentaleffects of non-uniform illumination in the performance

of a face recognition system have been investigated ex-perimentally by Buhman, Lades and Eeckman [38].

We will now present one solution to the problem

of robust image acquisition and preprocessing undervariable illumination conditions: a neurornorphic ana-log VLSI silicon retina. This is a contrast-sensitiveedge-enhancing imager that includes a rudimentary,yet effective, local gain control mechanism at the pixel

level. The architecture is inspired by the processing

performed in the outer plexiform layer of the verte-

b t ti [ [ Th lti i t d


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:

120 150 180 210

Fig.19. (Bottom) Mark captured by a conventional camera. (Top) Intensity profile at image line 110 (white line). The light souIce is

positioned to the right side of the image and it introduces a large gradient in illumination within a single frame. This is clearly shown in theintensity histogram. The dynamic range of the scene exceeds the dynamic range of the camera. Aperture control on the camera provides arudimentary global gain control mechanism. Information in this imag is lost at this very first step because there is no gain control (adaptation)at the pixel level.


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ElectricalSynapses

Photo-receptors

HorizontalCells

Fig. 21. One-dimensional model of neurons and synapses in theouter-plexiform layer. Based on the red-cone system in the turtleretina.

cal synapses. These allow ionic currents to flow from

one cell to another, and are characterized by a certain

conductance per unit area.

In the biological system, contrast sensitivity -the

normalized output that is proportional to a local mea-

sure of contrast- is obtained by shunting inhibitiori.

The horizontal cells compute the local average inten-sity and modulate a conductance in the cone membrane

proportionately. Since the current supplied by the cone

outer-segment is divided by this conductance to pro-duce the membrane voltage, the cones response, ,will

be proportional to the ratio between its photoinpt and

the local average, i. e. to contrast. This is a very simpli-

I X I

Fig. 22. Floorplan and system organization. It comprises of two

functional components, the core, and the support circuitry. Focalplane processing is performed in the core area.


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Fig.24. (Left) Photomicrograph of the chip. The surface is covered by second metal except where there are openings for the phototransistors(the dark square areas). Note the hexagonal connectivityof the pixels. (Right) Layout df the basic cell.

sion

in[151).

Refering to Figure 23, the output currentI c ( x m , y,) at each pixel, can be given (approximately)in terms of the input photocurrent I

(x y,) and a lo-

cal average of this photocurrent in a pixel neighborhood( M ,N ) . This region may extend beyond the nearest

neighbor. The fixed current I , supplied by transistor

M3 normalizes the result and P is a parameter.

with the internode distance normalized to unity. Solv-

ing for Zh (x, y), we find

This is thebiharmonic equation used in computer vi-sion to find an optimally smooth interpolating function

I h (x, y) for the noisy, spatially sampled dataI (x i , y j ) ;

it yields the function with minimum energy in its sec-


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S +

:

4 D

'Qs B' 'QdII

SD

Fig.25. Large signal model for anNMOS transistor (left). Adopted conventions for current decomposition in PMOSandNMOS devices (right).

4.4. Discussion

The silicon retina, presented in this paper is essentially

an analog floating-pointprocessor. As a first step, the

system computes the range (the voltages on the H nodescorrespond to the value of the exponent in floating-

point data representation). This is the operating point

of the system and is a function of the spatial coordinates

and this is how local automatic gain control is achieved.

At an operating point, sophisticated spatial filtering is

performed to smooth the sampled data and enhance the

d H i t d th bl f i i d

1,7 I I I I I

1

L

........................................................................I................... ................

1

1

5 '1

1

1

I I I I I

O 0.5 1 1.5 2 2.5 3


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amount because the transconductances are different

(compare Eqs. (6) and (8)). Whereas changing the

source voltage changes the the barrier by an equal

amount, only a certain fraction ( K ) of changes in thegate voltage affects the surface potential and hence the

barrier height. This behaviour is depicted in Figure 1and manifests itself as a slope for the current character-

istics that has lower value compared to that of a bipolar

transistor. An even lower value (1-K)for the slope isseen from the back gate terminal.

The experimental data from Figure 1 suggest that K

can be pushed closer to unity by biasing the device witha large surface potential (i.e. large VSBand VGB .The

dependence ofK

on the substrate voltage is measured

and plotted in Figure 26. As the substrate is reversed

bias, the depletion capacitance C&,p, in Equation 58becomes smaller and hence the gate has larger influence

on the channel conductance. Under these conditions,

the subthreshold MOS device becomes closer to anideal translinear element whose transfer characteristics

come closer to those of bipolars.

Another way to circumvent the potential divider

problem is to move the local substrate voltage together

with the source voltage-which is exactly equivalent

to increasing VGBby the same amount and does not

change In practice this may be achieved simply

1 0 7

1 8

10-9

1 1 O

I II

i

I I I I

-0.05 O 0.05 0.1 0.15 0.2 0.25

VSB

(Volts)

Fig. 27. Measured drain current IDS as a function of the sourcevoltage V S Bfora (16x 16pm)NMOS transistor fabricated in a 2pmn-well CMOS process. The solid line isanexponential function fit to

the data. The experiments were performed at a temperature such thatthe thermal voltage

V,

= 0.0259 Volts and hence 1/ V, = 38.5V-.


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160

A. G.Andreou andK.A. Boahen

30

25

'

Above Threshold

1 1ou

--Iu

, . I

I

2 0

15 Subthreshold1n

10--1oop

- - I

OP

5

O VGS [V]

O 5 10 15 20 25 30 0.2 0.4 0.6 0.8 1 1.2 1.4

Fig.29. (Left) Density plots of currents in a32 x 32 array of4pm x 4pm NMOS transistors. Each transistor is represented by a square pixel.Current level is coded by the shade of gray, where the minimum and maximum values are represented by black and white, respectively. Thecurrent at a nominal current level of lOOnA is obtained by setting VGSto be the same for all transistors in the array. The devices are biasedin saturation. (Right) Measured drain current

ZD

versus gate-source voltageVGS

for32 small geometry transistors (4 x 4p.m fabricated in a

2pm n-well CMOSprocess; drain-source voltage of V~s=1 . 5Volts. The fuzziness in the current, (mismatch between levices), is constant insubthreshold (on a

log(Z)

scale) and decreases asthe deviceent qs the transition and above threshold regime.\

5.2. Output Conductance Limitations mum [16], i.e., in the subthreshold and transition re-

gions. Small device geometries and hightransconduc-

The non-zero output conductance, or what is often tance per unit current makes the drain current stronglycalled the Early effect also degrades the performance dependent on spatial variations of process-dependent

of the circuits. All well known circuit techniques that parameters, particularly l o . Characterization of thereduce the output conductance, such as cascoding andregulated cascoding are beneficial to translinear cir-

cuits. A second effect contributes to the drain conduc-

fabrication process and the qhtchingproperties of the

basic devices is thus of paramount importance becauseit provides the necessary information for designing low


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Fig. 30. Dependence of normalized standard deviation of I D S ontransistor size; the lines are best fits to the data. All devices havesquare geometries with area A = L 2 . Notice that the normalizedstandard deviationof IDS saturates at large transistor geometries.

Figure 30 shows the dependence of the normalized

standard deviation of the drain current,O ( I ) / (I ) , on

transistor size. Each data point represents measure-ments from approximately 1000 transistors. The nor-malized standard deviation of the current is inversely

proportional to the square root of the device area, A,

and is given by:

Fig.31. Power spectral density for a PMOS transistor in saturation,where W = 1148 pm andL =4 pum. The model is given by solidlines, the data are marked by x's. The three curves correspond to

nominal current values of (a) 1nA, (b) 10nA, and (C)100nA for an

equivalent square device. Some amount of excess noise is evident atlow current levels.

Assuming shot and flicker noise are independent, a

complete noise model for a transistor operating in the

subthreshold region is


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The maximum value of drain current I D Sm ax with a sabbatical leave at Caltech. We thank Carver Mead

the MOS transistor still in subthreshold region is given for his continuing support and encouragement. Chip

by 151: fabrication was provided by MOSIS.r

Appendix A: Device Models

From the above equations a maximum transition fre-quency in subthreshold T m a x can be approximated to: A 1

B@ozar

Transistor

The Ebers-Moll model [46], [47] for an npn bipolar(44) transistor is:

IE = - IF

+ C Y R I R

where is the effective carrier mobility andL iy$he 45)

device channel length. The transition frequency of a IC = ~ F I F- R

device is essentially the bandwidth (as determined bythe internal gain and parasitic capacitances of the tran- , I F = I E s ( e 7V B E - 1)sistor). For six to ten micron length devices (typical

in analog VLSI today), functional systems in the hun- IR = I c s ( e 7 - 1)

dreds of kHz range are possible while for submicrondevices, the limit extends to the MHz range.

QVBC

FIES

= ~ R I C S (47)

6. Conclusions where IC and I E are the collector and emitter currents

In this paper we have provided a comprehensive

overview of the application of the translinear princi-

respectively andV B E is the base to emitter voltage,



24/27


When the collector to base voltage equals zero or the

collector is reverse biased with respect to the base, the

above equation simplifies to the familiar:

whereA E

is a design parameter, the area of the emitter

junction.JES

and I s are the saturation current density

and current for the emitter respectively. In this case,

I R


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164 A. G.Andreou andK.A.Boahen

tor has been called a dif i sor [151 in analogy with thevariable conductance electrical junctions in biological

systems.

An expression for the current in anNMOS transistoroperating in subthreshold can thus be written [6], [7]as:

ID

IDS

= I n 0Sexp(~n

VG

B / Vt1

x

[exp(-VSB/h) - xp(-VDB/Vt)l (55)

and for a PMOS

I D

ISD

= IpO Sexp(-Kp VGB/Vt)

x [exp(VSB/Vt) exp(VDB/Vt)] (56)

The terminal voltages VGB,VSB,VDBare referencedto the substrate. The constant

IO

depends on mobility

P) and other silicon physical properties. S is a geom-etry factor, the width W to lengthL ratio the device.

For devices that are biased withVDS

2 4 V,, (satu-ration) the drain current is reduced to:

divider ratio closer to unity. A larger surface poten-tial also reduces C&p. The parameter K takes values

between 0.6 and 0.9.

l. Thediffusor is a term adopted in [151to describe the exploitationof diffusion transport in MOS transistors to spread signals in amanner analogous to gap junctions between neural cells.

References

1.

2.

3.

4.

5.

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AndreasG.Andreou received the M.S.E. andPh.D.

in electrical engineering and computer science fromJohns Hopkins University, Baltimore, in 1983 and

1986, respectively. From 1987 to 1989 he was a post-doctoral fellow and associate research scientist at Johns

Hopkins where he became Assistant Professor in 1989and Associate Professor in 1993. His research interests

are in the areas of device physics, integrated circuitsand neural computation.

Dr. Andreou is a member of Tau Beta Pi and a mem-

ber of I.E.E.E.

Kwabena A. Boahen is aPh.D.

student at Caltech

in the Computation and Neural Systems program aftercompleting a B.S.N.S.E. degreein electrical and com-

puter engineering at Johns Hopkins University, Bal-

timore, MD. His research at Caltech involves analogVLSI models of biological computation, with an em-phasis on retinal computation and chip-to-chip com-

munication.Mr. Boahen is a member of Tau Beta Pi and a student

member of the I.E.E.E.

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