500 W fully digital AC-DC power supply (D-SMPS) evaluation ... · Figure 1: STEVAL-ISA147V3 evaluation board . This application note focuses on the design of STEVAL-ISA147V3, a 500

October 2016 DocID029850 Rev 1 1/46

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AN4930 Application note

500 W fully digital AC-DC power supply (D-SMPS) evaluation board

Introduction AC-DC converters designed for a wide variety of applications, from computer adapters to server and telecom systems, require high efficiency over the entire load range of operation and across the universal mains input voltage range. Given the demand for more efficient, smaller adapters, their design is becoming more challenging and new conversion approaches, rather than the standard designs based on analog ICs, have been investigated. In particular, while the standard approach is based on the use of a boost type PFC and a regulation stage, both of which controlled using analog PWM regulators, the new, fully digital approach relies on the use of microcontrollers to control both the PFC and the DC-DC stage. This approach is increasingly being used for high density, high efficiency power electronics systems.

Figure 1: STEVAL-ISA147V3 evaluation board

This application note focuses on the design of STEVAL-ISA147V3, a 500 W AC-DC switch mode power supply with full digital control based on the STM32 family of microcontrollers. The system consists of two power stages: an input semi-bridgeless power factor corrector (SBPFC) controlled by an STM32F051K8 and a regulation stage implemented with an LLC half-bridge with synchronous rectification (SR), controlled by an STM32F334C8 microcontroller. The operating principles, main features and design choices are discussed. Details regarding the main components used for the implementation of both the power and control stages are also provided.

Contents AN4930

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Contents 1 System overview ............................................................................. 5

2 Bridgeless PFC stage ...................................................................... 7

2.1 Operating principle ............................................................................ 7

2.2 Semi-bridgeless PFC design ........................................................... 10

2.3 PFC control algorithm ..................................................................... 13

2.4 PFC firmware overview ................................................................... 15

3 LLC DC-DC converter design ....................................................... 20

3.1 LLC converter firmware overview and control algorithm ................. 26

4 Experimental characterization ...................................................... 31

5 Schematic diagrams ...................................................................... 37

6 Conclusions ................................................................................... 43

7 References ..................................................................................... 44

8 Revision history ............................................................................ 45

AN4930 List of tables

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List of tables Table 1: 500 W AC-DC converter specifications ........................................................................................ 6 Table 2: Specifications of the 500 W Bridgeless PFC .............................................................................. 11 Table 3: Function names and tasks of the PFC firmware ......................................................................... 17 Table 4: Microcontroller resources for PFC digital control implementation .............................................. 19 Table 5: Main specifications of the LLC converter .................................................................................... 21 Table 6: LLC converter parameters .......................................................................................................... 25 Table 7: LLC firmware tasks ..................................................................................................................... 29 Table 8: Efficiency measurements at 120 VAC ........................................................................................ 31 Table 9: Efficiency measurements at 230 VAC ........................................................................................ 31 Table 10: DSMPS power factor and current THD% at 120 VAC .............................................................. 32 Table 11: DSMPS power factor and current THD% at 230 VAC .............................................................. 32 Table 12: Document revision history ........................................................................................................ 45

List of figures AN4930

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List of figures Figure 1: STEVAL-ISA147V3 evaluation board .......................................................................................... 1 Figure 2: 500 W digital power supply: block diagram ................................................................................. 5 Figure 3: Basic scheme of a bridgeless PFC converter. ............................................................................ 7 Figure 4: Semi-bridgeless PFC with addition of diodes D3 and D4 ........................................................... 8 Figure 5: Current path during positive half-cycle when M1 is ON .............................................................. 8 Figure 6: Current path during positive half-cycle when M1 is OFF ............................................................ 9 Figure 7: Current path during negative half-cycle when M2 is ON. ............................................................ 9 Figure 8: Current path during negative half-cycle when M2 is OFF ......................................................... 10 Figure 9: PFC control scheme block diagram .......................................................................................... 13 Figure 10: variation of the Kg parameter with the input PFC voltage ....................................................... 15 Figure 11: PFC firmware state machine overview .................................................................................... 16 Figure 12: Timer 1 utilization for PFC PWM generation and ADC conversion trigger ............................. 18 Figure 13: ADC utilization and acquisition sequence ............................................................................... 18 Figure 14: Basic schematic of the LLC DC-DC converter ........................................................................ 20 Figure 15: Resonant tank gain at full load, half load, no load .................................................................. 24 Figure 16: Block diagram of the LCC converter control ............................................................................ 26 Figure 17: STM32F334x ADC1 and ADC2 utilization ............................................................................... 27 Figure 18: ADC1 and ADC2 injected acquisition sequence and trigger events ....................................... 28 Figure 19: HRTIM timing configuration ..................................................................................................... 28 Figure 20: LLC firmware structure overview ............................................................................................. 29 Figure 21: STM32F334x internal comparator configuration for overcurrent protection ............................ 30 Figure 22: PFC inductor current at 120 V input, full load .......................................................................... 32 Figure 23: PFC inductor current at 230 V input, full load .......................................................................... 32 Figure 24: PFC circuit efficiency ............................................................................................................... 33 Figure 25: PFC input current power factor................................................................................................ 33 Figure 26: PFC inductor L2 (blue) and L1 (green) current and MOSFET Q1 drain voltage (purple) at 120 V, 60 Hz input, full load ............................................................................................................................. 33 Figure 27: PFC inductor L1 (green) L2 (blue) and current and MOSFET Q2 drain voltage (purple) at 120 V, 60 Hz input, full load ............................................................................................................................. 33 Figure 28: PFC inductor L2 (blue) and L1 (green) current and MOSFET Q1 drain voltage (purple) at 230 V, 50 Hz input, full load ............................................................................................................................. 34 Figure 29: PFC inductor L1 (green) L2 (blue) and current and MOSFET Q2 drain voltage (purple) at 230 V, 50 Hz input, full load ............................................................................................................................. 34 Figure 30: LLC converter, MOSFET Q12 Gate signal (yellow), drain current (blue), drain voltage (purple) at full load (42 A output) ............................................................................................................................ 34 Figure 31: LLC converter, MOSFET Q12 Gate signal (yellow), drain current (blue), drain voltage (purple) at no load .................................................................................................................................................. 34 Figure 32: LLC switching frequency vs. output current ............................................................................ 35 Figure 33: LLC converter efficiency .......................................................................................................... 35 Figure 34: Load transition from 10% to 90% max load (max load=42 A) with 120 V, 60 Hz AC input ..... 35 Figure 35: Load transition from 90% to 10% max load (max load=42 A) with 120 V, 60 Hz AC input ..... 35 Figure 36: Repetitive dynamic load variation 10% to 90% max load ....................................................... 36 Figure 37: Startup at full load (42 A), 230 V, 50 Hz input voltage; PFC bus voltage (yellow), 12 V output (purple); output current (green and blue) .................................................................................................. 36 Figure 38: Input current waveform at full load, 120 VAC .......................................................................... 36 Figure 39: Input current waveform at full load, 230 VAC .......................................................................... 36 Figure 40: STEVAL-ISA147V3 circuit schematic (1 of 6) ......................................................................... 37 Figure 41: STEVAL-ISA147V3 circuit schematic (2 of 6) ......................................................................... 38 Figure 42: STEVAL-ISA147V3 circuit schematic (3 of 6) ......................................................................... 39 Figure 43: STEVAL-ISA147V3 circuit schematic (4 of 6) ......................................................................... 40 Figure 44: STEVAL-ISA147V3 circuit schematic (5 of 6) ......................................................................... 41 Figure 45: STEVAL-ISA147V3 circuit schematic (6 of 6) ......................................................................... 42

AN4930 System overview

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1 System overview The block diagram of the 500 W digital AC-DC converter is shown in the following figure. A two-stage architecture is generally implemented in this type of application.

Figure 2: 500 W digital power supply: block diagram

The first block, from left to right, is the EMI filter. In a standard AC-DC topology, the EMI filter is connected to the input of a diode bridge rectifier, which is then connected to the input of a PFC stage. However, this 500 W AC-DC implementation uses the so-called bridgeless PFC topology which has the advantage of lower conduction losses and higher efficiency by eliminating the need for the diode rectifier stage. This choice also has the advantage of reducing component count with respect to a standard PFC.

The input stage is typically controlled using an outer voltage loop for bus voltage regulation and an inner control loop to shape the current according to a sinusoidal waveform. The outer loop adjusts the current reference in order to maintain a regulated bus voltage independently from the load or input voltage variations. The output isolation and regulation stage is implemented using a half-bridge LLC topology operated with constant duty cycle and variable frequency control.

The DC-DC stage performs voltage step-down using an HF transformer with a primary-to-secondary turns ratio chosen to maintain good efficiency and regulation in the entire operating range. The transformer is supplied with a square wave voltage generated by the primary side active switches. On the secondary side this voltage waveform is rectified and then smoothed by the output filter. While on the primary side switching losses are reduced thanks to zero voltage switching (ZVS), on the secondary side synchronous rectification (SR) is used to ensure low conduction losses. The overall effect of these design choices is high system efficiency, in line with the stringent requirements of the power supply industry.

System overview AN4930

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The system is controlled by two microcontrollers from the STM32 product family. On the primary side, an STM32F051K8 controls the bridgeless PFC by sampling the current of the two MOSFETs, the input AC voltage and the output bus voltage. Two control signals, PWM1 and PWM2, are then generated to drive two power switches. On the secondary side, an STM32F334C8 microcontroller samples the output voltage and adjusts the frequency of the LLC bridge control signals to ensure stable operation in the overall load range. In addition, two channels of the ADC are used to sample the rising and falling edges of the drain-to-source voltage of the SR MOSFETs. The two microcontrollers exchange information about the status of the input and output power stage via bidirectional serial communication.

Both the power stage and control stage are supplied by an offline flyback circuit which provides a suitable regulated voltage to the microcontrollers, the gate drive ICs and signal conditioning circuits.

The table below summarizes the 500 W digital power supply main specifications. Table 1: 500 W AC-DC converter specifications

Parameter Value

Input AC voltage 95 VAC up to 264 VAC

Input AC frequency 45 Hz up to 65 Hz

Output voltage 12 V DC

PFC output voltage 430 V DC

Output power 500 W

PFC switching frequency 60 kHz

DC-DC switching frequency 70 kHz up to 130 kHz

HF transformer isolation 4 kV

Peak efficiency 93.2%

Cooling Forced air cooling

Input short-circuit protection 10 A fuse

Output short-circuit protection Managed by STM32F334C8

Input under/overvoltage Managed by STM32F051K8

Input under/overfrequency Managed by STM32F051K8

Bus DC under/overvoltage Managed by STM32F051K8

Output under/overvoltage Managed by STM32F334C8

Overtemperature protection Managed by STM32F051K8 (primary) and STM32F334C8 (secondary)

The converter accepts universal input voltage and produces a 12 V regulated output. The continuous power rating of the unit is 500 W. Natural convection is used up to 300 W. Above this power level a cooling fan is activated to provide forced air cooling. The ambient operating temperature range is 0 ºC to 50 ºC.

The intermediate high-voltage DC bus is regulated at 430 V by the PFC which draws sinusoidal input current from the AC input maintaining high power factor and low current total harmonic distortion (THDI%). The LLC circuit converts this high DC voltage to low DC voltage proving isolation (4 kV) by means of an HF transformer, and high efficiency thanks to ZVS. Input and output current and voltage protection are also provided together with overtemperature protection.

AN4930 Bridgeless PFC stage

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2 Bridgeless PFC stage

2.1 Operating principle The bridgeless PFC is a high efficiency topology characterized by the absence of the diode bridge rectifier and by the use of only two semiconductors in the current conduction path during any operating interval. The basic scheme of the bridgeless PFC boost converter is shown in Figure 3: "Basic scheme of a bridgeless PFC converter.". The boost inductor is connected directly to the input AC source and split between line and neutral connection. Each inductor is connected to the drain of a power MOSFET and to the anode of a fast switching diode. The cathodes of the two diodes are connected to the output filter capacitor which is then parallel connected to the load.

The operation of this circuit is very similar to that of a standard PFC. More in detail, during the positive half-cycle of the input voltage, the boost converter composed of L1, M1, D1 and C1 is active, while during the negative half-cycle of the input voltage the boost converter composed of L2, M2, D2, and C2 is active.

Although this circuit has a reduced component count and higher efficiency compared to traditional PFC topologies, it has some drawbacks which limit its use in such a configuration. The main one is that the AC source is not referenced to the PFC ground. As a consequence, some difficulties in input voltage and inductor current sensing are introduced. Common mode EMI filtering can also be an issue related to this circuit.

A variant of the bridgeless PFC, known as semi-bridgeless PFC, is characterized by the addition of two diodes, D3 and D4, is shown in Figure 4: "Semi-bridgeless PFC with addition of diodes D3 and D4". The purpose of these diodes is to keep the negative phase connected to the PFC ground, thus resolving the EMI filtering issue mentioned above for the bridgeless topology.

Figure 3: Basic scheme of a bridgeless PFC converter.

Bridgeless PFC stage AN4930

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Figure 4: Semi-bridgeless PFC with addition of diodes D3 and D4

The operating principle is briefly described as follows:

Positive half-cycle Figure 5: Current path during positive half-cycle when M1 is ON

• The input voltage diode D3 is off and D4 conducts the current returning to the source. MOSFET M1 is switched ON and OFF while MOSFET M2 is idle.

• When MOSFET M1 is ON the current flows as highlighted in Figure 5: "Current path during positive half-cycle when M1 is ON".

• When MOSFET M1 is OFF the current flows as highlighted in Figure 6: "Current path during positive half-cycle when M1 is OFF".

• The return path of current is offered by the parallel of diode D4 and the body diode of M2.


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Figure 6: Current path during positive half-cycle when M1 is OFF

Negative half-cycle Figure 7: Current path during negative half-cycle when M2 is ON.

• Diode D4 is OFF and diode D3 conducts the current returning to the source. In this case M2 is switched ON and OFF while M1 is idle.

• When M2 is ON current flows as shown in Figure 7: "Current path during negative half-cycle when M2 is ON.".

• When M2 is OFF, the current flows as shown in Figure 8: "Current path during negative half-cycle when M2 is OFF"

• The return path of the current is offered by the parallel of diode D3 and the body diode of M1.


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Figure 8: Current path during negative half-cycle when M2 is OFF

Note that in the previous analysis it has been supposed that during the positive and negative half-cycles one of the two MOSFETs is switching and the other is idle. There are actually two additional control strategies besides the one mentioned above.

In the first, during the positive half-cycle of the input voltage M1 is switched ON and OFF while M2 is kept ON. During the negative half-cycle of the voltage, M2 is switched ON and OFF while M1 is kept ON. This control strategy allows the return current to flow across the channel of the MOSFET rather than across the body diode and, therefore, some improvement in efficiency is possible.

In the second, both MOSFETs are controlled synchronously, with the same PWM signal applied to each gate. Again, the benefit is lower power dissipation when current flows through the MOSFET during the return phase. In addition, only one driver can be used for both MOSFETS.

Due to these advantages, the PFC topology chosen for the 500 W digital power supply implementation described in this application note is the semi-bridgeless PFC with synchronous control.

2.2 Semi-bridgeless PFC design The practical implementation of the proposed 500 W bridgeless boost PFC rectifier is detailed in this section. The converter is designed to operate in DCM. In low and medium power applications, discontinuous and critical conduction mode are often used to obtain numerous benefits such as reduced switching losses, low diode reverse recovery current and small inductor size.


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The PFC was designed starting from the specifications shown in the following table: Table 2: Specifications of the 500 W Bridgeless PFC

Parameter Value

Input AC voltage 90 VAC up to 264 VAC

Input AC frequency 45 Hz up to 65 Hz

Output voltage 12 V DC

PFC output voltage 430 V DC

Output power 500 W

PFC switching frequency 60 kHz

Efficiency >95%

The design steps are reported as follows:

• Maximum input RMS current value

Considering the minimum input voltage and the minimum desired converter efficiency, the maximum RMS value of the input current can be calculated.

Equation 1

𝐼𝐼𝑖𝑖𝑖𝑖_𝑅𝑅𝑅𝑅𝑅𝑅_𝑚𝑚𝑚𝑚𝑚𝑚 =𝑃𝑃𝑜𝑜𝑜𝑜𝑜𝑜

𝜂𝜂 ⋅ 𝑉𝑉𝑖𝑖𝑖𝑖_𝑅𝑅𝑅𝑅𝑅𝑅_𝑚𝑚𝑖𝑖𝑖𝑖= 5.84 𝐴𝐴

• Maximum input peak current value

Equation 2

𝐼𝐼𝑖𝑖𝑖𝑖_𝑝𝑝𝑝𝑝_𝑚𝑚𝑚𝑚𝑚𝑚 = √2 ∙ 𝐼𝐼𝑖𝑖𝑖𝑖_𝑅𝑅𝑅𝑅𝑅𝑅_𝑚𝑚𝑚𝑚𝑚𝑚 = 8.24 𝐴𝐴

• Boost inductor value

The inductance value of the two input chokes has to be carefully selected in order to ensure DCM operation across the universal input voltage range and load range. This is guaranteed if the inductor is selected according to:

Equation 3

𝐿𝐿 <𝑀𝑀 − 14 ∙ 𝑀𝑀3 ∙ 𝑅𝑅 ∙ 𝑇𝑇 = 95 𝜇𝜇𝜇𝜇

Where M=Vout/Vin is the converter voltage gain, R=Vout²/Pout is the load resistance and T is the switching period. Note that in equation 3 the minimum value of peak input voltage has been considered for the calculation of the value of the input inductors.

Two 100 µH, 10 A RMS inductor chokes, characterized by a 33 mΩ DC resistance have been selected for this application. The peak-current rating of the inductor must be well above the expected peak current of the converter to avoid core saturation. A gapped ferrite with core material characterized by low core losses at the design switching frequency of 60 kHz has been used.

• Inductor peak current

The inductor peak current can be calculated as:

Equation 4

𝐼𝐼𝐿𝐿𝑝𝑝𝐿𝐿𝑚𝑚𝑝𝑝 =𝑉𝑉𝑉𝑉𝑉𝑉_𝑝𝑝𝑝𝑝𝑚𝑚𝑖𝑖𝑖𝑖

𝐿𝐿∙ 𝑡𝑡𝑜𝑜𝑖𝑖_𝑚𝑚𝑚𝑚𝑚𝑚 = 18.9 𝐴𝐴


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Equation 5

𝐷𝐷𝑚𝑚𝑚𝑚𝑚𝑚 =𝑡𝑡𝑜𝑜𝑖𝑖_𝑚𝑚𝑚𝑚𝑚𝑚

𝑇𝑇𝑠𝑠= 0.9

Where it is assumed that the duty cycle is limited to a maximum of 0.9

• Power MOSFET selection

The choice of power semiconductors is fundamental to meet the efficiency requirements of the application. In a boost PFC, when the switch is on the current is equal to the inductor current. The peak current calculated in equation 4 is also the peak current of the switch. When the switch is off, the drain-to-source voltage is the output voltage. Therefore, the MOSFET is selected with a rated voltage greater than the output voltage and rated current greater than the maximum inductor current. Since the boost PFC operated in DCM is mainly affected by conduction losses, it is very important to use a power MOSFET with low drain-to-source resistance in order to ensure high efficiency. The output voltage of the device value is chosen according to:

Equation 6

𝑉𝑉𝑉𝑉𝑉𝑉𝑚𝑚𝑜𝑜𝑠𝑠 > 1.3 ∙ 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 > 559 𝑉𝑉

To meet the design requirements, the STP42N60M2-EP-channel power MOSFET has been used for M1 and M2. This device is characterized by a minimum breakdown voltage of 650 V and a maximum on resistance of 87 mΩ at 25 °C. The total gate charge is 55 nC.

• Rectifier diodes selection

The average diode current can be calculated as:

Equation 7

𝐼𝐼𝐷𝐷 =𝑃𝑃𝑜𝑜𝑜𝑜𝑜𝑜𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜

= 1.16 𝐴𝐴

Two STPSC1006D 600 V, 10 A diodes are used as rectifier diodes. The forward voltage drop at 1.16 A is about 0.75 V at TJ=150 °C.

• Output capacitor selection

The output capacitor bank value is selected to limit the output voltage ripple to 1% of the nominal output voltage. Equation 8 has been chosen to define the value of the output capacitor bank:

Equation 8

𝐶𝐶𝑜𝑜𝑜𝑜𝑜𝑜 =𝑃𝑃𝑜𝑜𝑜𝑜𝑜𝑜

2𝜔𝜔∆𝑉𝑉0𝑉𝑉0= 430 𝜇𝜇𝜇𝜇

Where ω is the mains angular frequency and ΔV0 is the output voltage ripple. Four 450 V, 100 μF electrolytic capacitors from Vishay have been parallel connected on the PFC output. In addition, a 600 V, 560 nF ceramic capacitor with low ESR and ESL is connected in parallel to the each electrolytic capacitor.

• Input filter capacitors

The need for a high power factor introduces a limit on the maximum capacitance that can be placed across the line. The maximum capacitance is a function of how much phase shift that can be tolerated. This phase shift angle can be calculated using:

Equation 9

𝜃𝜃 = 𝑡𝑡𝑡𝑡𝑉𝑉−1 �𝜔𝜔 ∙ 𝑉𝑉𝑉𝑉𝑉𝑉𝑚𝑚𝑚𝑚𝑚𝑚 ∙ 𝐶𝐶𝑖𝑖𝑖𝑖

𝐼𝐼𝑖𝑖𝑖𝑖�


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Choosing Cin=3 uF the total displacement is 7°.

• Current sensing

The current flowing across each power switch is sensed by means of CTs. These are placed between the inductor and the MOSFET. Due to this placement, only the rising part of the inductor current is available to the control algorithm. The current signal is always sampled at the mid-point of the gate control PWM. Then, the current samples could be digitally corrected in order to calculate the average inductor current. In fact, contrary to the CCM case, when the PFC is in DCM the current sensed at the mid-point of the MOSFET triangular current waveform is no longer equal to the inductor average current.

The CT must withstand the peak current calculated in equation 4. The selected current sense transformer is the 53040C from Murata. This is characterized by a magnetizing turns ratio of 40.

2.3 PFC control algorithm This section contains an overview of the PFC digital average current-mode control method in discontinuous conduction mode (DCM). This control method allows good input current shaping in terms of harmonic distortion (low THD) and synchronization with input voltage (PF close to one). The proposed control technique estimates the average value of the inductor current in each switching cycle. The average inductor current can be precisely estimated by the digital controller modifying the sampling instant within the switching period and calculating a correction factor. Sampling the inductor current more than once in a switching cycle, with a high-performance A/D converter, also helps to achieve a precise average inductor current estimation.

The control is implemented by means of a conventional current sensing circuit and a 32-bit microcontroller, the STM32F051K8 from the STM32 family, which features a fast 12-bit A/D converter. As in traditional average current mode control implementations, this algorithm uses two control loops: an outer voltage loop, performed at 100 Hz providing the regulation of the bus voltage output at the reference value (430 V) and an inner current loop, performed at 20 kHz, to ensure that the input current follows a sinusoidal reference in phase with the input voltage. While the voltage control is achieved with a single linear regulator, the current control is based on a PI controller plus a feed-forward controller.

Figure 9: PFC control scheme block diagram


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A block diagram of the control scheme is shown in Figure 9: "PFC control scheme block diagram". The average inductor current is forced to follow the reference current, which is proportional to a rectified sinusoidal voltage synchronized to the input voltage and reconstructed by a lookup table, so that unity power factor is achieved. The lookup table provides the sinusoidal values in a [0°, 90°] range with 1.15 fixed-point format (1 bit for the integer part and 15 bits for the decimal part), with the amplitude given by the output of the voltage PI regulator.

The STM32 microcontroller calculates the duty cycle in every three switching cycles based on the error between the feedback current and the reference current values. The two switches are then controlled with these duty cycle values to achieve unity power factor and sinusoidal input current waveform. The whole digital average current mode control includes:

1. bus voltage and MOSFETs current sampling 2. voltage error calculation 3. voltage PI regulation 4. reference current calculation 5. current error calculation 6. current PI regulation 7. duty cycle feed-forward generation 8. final duty cycle computation.

The final calculated duty cycle value is therefore composed of two terms: an open loop, feed-forward term, which depends on the instantaneous input and output voltage values, and a closed loop term which depends on the applied load. The input voltage value of the feed-forward term is obtained by means of the same lookup table used to calculate input voltage amplitude and phase. This choice is effective for noise reduction and for compensation of sampling delays.

Considering only half the period of the input sinusoid, the expression of the duty cycle for the boost converter in CCM is:

Equation 10

𝑉𝑉(𝑡𝑡) = 1 −𝑉𝑉𝑖𝑖𝑖𝑖|𝑉𝑉𝑉𝑉𝑉𝑉𝜔𝜔𝑡𝑡|

𝑉𝑉0

where Vo is the output bus voltage, and Vin sin ωt is the mains voltage. However, this converter is designed to work in DCM and therefore the correct expression of the duty cycle is:

Equation 11

𝑉𝑉(𝑡𝑡) = 𝐷𝐷 ∙ �1 −𝑉𝑉𝑖𝑖𝑖𝑖|𝑉𝑉𝑉𝑉𝑉𝑉𝜔𝜔𝑡𝑡|

𝑉𝑉0

where D is the constant duty cycle in absence of modulation. Since the implementation of this formula is quite complex, the feed-forward duty cycle term has been calculated using the following expression:

Equation 12

𝑉𝑉(𝑡𝑡) = 𝐾𝐾𝑓𝑓𝑓𝑓 ∙ �1 −𝑚𝑚 ∙𝑉𝑉𝑖𝑖𝑖𝑖|𝑉𝑉𝑉𝑉𝑉𝑉𝜔𝜔𝑡𝑡|

𝑉𝑉0�

Where kff is a gain depending on the load and the input voltage and m is a constant modulating index.


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The gain kff increases with load and decreases with input voltage. Since the output of the PI voltage regulator depends on the load, the expression chosen for feed-forward duty cycle gain is the following:

Equation 13

𝐾𝐾𝑓𝑓𝑓𝑓 = 𝐾𝐾𝑔𝑔 ∙𝑉𝑉𝑃𝑃𝑃𝑃𝑜𝑜𝑜𝑜𝑜𝑜𝑉𝑉𝑖𝑖𝑖𝑖

where Vin is the amplitude of mains voltage, VPIout is the output of the voltage PI regulator and kg is a gain that varies with the input voltage amplitude according to the diagram shown in the following figure.

Figure 10: variation of the Kg parameter with the input PFC voltage

2.4 PFC firmware overview The execution of the PFC firmware is based on the implementation of a state machine made up of six states. The diagram in Figure 11: "PFC firmware state machine overview" provides an overview of the firmware architecture. As soon as the microcontroller is supplied, all the peripherals are configured and the firmware is in PFC IDLE state. Here the system waits for the AC mains insertion and verifies that no faults are present. If no faults are detected, the new state is PFC INIT. In this state the integral terms of PI regulators are reset and the PM8834 (PFC MOSFET driver) is enabled. The PFC output reference voltage is initialized to the last sampled value. After this, the new state is PFC START, where the output voltage ramp function is executed. When the ramp is completed and the output voltage is equal to 430 V DC, the LLC L6491 driver is enabled and a serial command is sent to the secondary microcontroller to confirm that the PFC startup is completed. Then, the feed-forward duty cycle control is enabled and the next state is PFC ON. If in any of the above states a fault condition is verified the system is forced into PFC STOP state.


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Figure 11: PFC firmware state machine overview

The possible faults are:

• Input voltage under/overfrequency (F< 45 Hz; F>65 Hz) • Input under/over voltage (Vin< 95 V RMS; Vin>264 V RMS) • Bus DC undervoltage (320 V) • Bus overvoltage (Vbus>470 V)

In any of these cases both the PFC and LLC PWM modulation are disabled. The MOSFET driver enabling signal is low and the system is in PFC WAIT state for 5 seconds before the system enters the PFC IDLE state.

If during PFC operation, the bus voltage is greater than 450 V but lower than 470 V, the PFC operates in BURST MODE. In this case, the PFC is forced into the STOP state and only the PFC modulation is disabled while the LLC converters continue to operate. The WAIT state is bypassed and the system is forced into IDLE state. The PWM modulation is re-enabled when the PFC bus voltage is below 430 V.

As described above, the control firmware performs several tasks, with different timings and priorities to ensure both output voltage regulation and input current regulation. The main tasks and functions are summarized in Table 3: "Function names and tasks of the PFC firmware", together with the execution time and priority level.


DocID029850 Rev 1 17/46

Table 3: Function names and tasks of the PFC firmware

Function Task Execution frequency Priority

ADC1_COMP_IRQHandler()

Current control loop Sinusoidal reference calc.

Input voltage sign detection Average of last 3 current

samples

20 kHz 60 kHz 60 kHz 60 kHz

High

TIM14_IRQHandler() Voltage control loop

Update control parameters 100 Hz Medium

TIM6_DAC_IRQHandler() Computing of Vac frequency and amplitude 2 kHz Medium

main()

Fault checks State machine

Serial communication LED

Low

After the initialization of the main peripherals such as system clock, ADC, DMA, timers, UART and I/O ports, which are executed in the main loop, the fault check function and serial communication tasks are performed. These tasks have lower priority level compared to those executed in specific interrupts.

As soon as the 500 W power supply is connected to the mains supply, the PFC is in idle state and a fault check routine is executed to ensure that no fault conditions are present. During this phase, the input voltage amplitude and frequency are calculated in order to verify that the mains parameters are within the converter specified operating window. In this case, the PM8834 gate driver, used to drive the two PFC MOSFETs, is enabled and the main PFC control algorithm is performed. A soft-start routine is first executed to linearly increase the DC bus voltage up to 400 V. When the soft-start is completed, the primary STM32F051K8 microcontroller sends the information of the correct PFC status to the secondary STM32F334x microcontroller, via serial communication. After having sent this information, the primary microcontroller starts the control loop routine, updating the control regulator parameters and enabling a second voltage ramp-up to increase the bus voltage to 430 V.

The algorithm for the computation of the input voltage amplitude and frequency is performed when the update event of timer 6 (TIM6) occurs (every 500 µs). The voltage control loop is executed every 10 ms when the update event of timer 14 (TIM14) occurs. Also, the calculation of new feed-forward duty cycle control parameters is triggered by the same event.

The current control loop is the highest priority task and is performed when the interrupt of the ADC end of conversions is triggered. All the acquisitions are synchronized with timer 1 (TIM1) which generates the output PWM signals (CH1 and CH2 of TIM1) as shown in Figure 12: "Timer 1 utilization for PFC PWM generation and ADC conversion trigger". A single sampling in single period technique is adopted.


18/46 DocID029850 Rev 1

Figure 12: Timer 1 utilization for PFC PWM generation and ADC conversion trigger

Figure 13: ADC utilization and acquisition sequence

The switch current is sensed at the midpoint of the PWM ON time which corresponds to the average inductor current in CCM. A sample correction algorithm can be implemented to take into account DCM operation. This is generally done, when necessary, to improve the input current THD. The ADC samples the MOSFET current first, either across MOS1 or MOS2, depending on the sign of input voltage sine waveform. Then, the input voltage is sampled and immediately after the output bus voltage is sampled. The acquired samples are then transferred into a buffer by DMA, keeping CPU resources free for other operations. The acquisition sequence (which depends on the sign of the input voltage) and ADC channels utilization is shown in Figure 13: "ADC utilization and acquisition sequence".

If a fault condition occurs, the PWMs are stopped, the PFC gate driver is disabled and a serial message is sent to the secondary side microcontroller in order to stop the LLC control algorithm.


DocID029850 Rev 1 19/46

The following table summarizes the resources required for the implementation of the digital control of the 500 W semi-bridgeless PFC.

Table 4: Microcontroller resources for PFC digital control implementation Signal Type MCU resource Resolution

Input voltage Analog ADC1 CH8 12 bit (1MSPS)

Output voltage Analog ADC1 CH9 12 bit (1MSPS)

MOS1 current Analog ADC1 CH1 12 bit (1MSPS)

MOS2 current Analog ADC1 CH0 12 bit (1MSPS)

ADC trigger Digital TIM1 CH4

Gate drive 1 Digital TIM1 CH1 (PWM1) Dres=0.125% at 60kHz

Gate drive 2 Digital TIM2 CH2 (PWM2) Dres=0.125% at 60kHz

RS232-RX Digital UART1 (PB10)

RS232-TX Digital UART1 (PB6)

Temp. sense Analog ADC1 (CH6)

LED Digital GPI/O (PB2)

PM8831 enable/disable Digital GPI/O (PA12)

L6491 enable/disable Digital GPI/O (PF1)

LLC DC-DC converter design AN4930

20/46 DocID029850 Rev 1

3 LLC DC-DC converter design The purpose of the DC-DC stage is to step the PFC output voltage down to 12 V. The topology used for this conversion stage, the LLC half-bridge, is shown in Figure 14: "Basic schematic of the LLC DC-DC converter". The power stage of the LLC converter is formed by the input and output capacitors C2 and C3, MOSFETs M3, M4, transformer T1 and resonant capacitor Cr. The resonant inductor Lr and the magnetizing inductor Lm depicted in Figure 14: "Basic schematic of the LLC DC-DC converter" are integrated in the high frequency transformer. The output rectification stage is implemented with two MOSFETs, M5 and M6, used to exploit the advantages of synchronous rectification. The main advantages of the LLC topology are:

• ZVS at turn-on for the primary side switches • ZCS at turn off for the secondary side switches • Very good load regulation

The main drawback is the high sensitivity to input voltage variations which requires some design trade-offs to optimize the circuit in a wide input voltage range. The specifications used for this design are reported in Table 5: "Main specifications of the LLC converter".

Figure 14: Basic schematic of the LLC DC-DC converter

AN4930 LLC DC-DC converter design

DocID029850 Rev 1 21/46

Table 5: Main specifications of the LLC converter Parameter Value

Input voltage 420 V

Minimum input voltage 400 V

Maximum input voltage 440 V

Nominal output voltage 12 V DC

Efficiency >96%

Output power 500 W

Switching frequency 80 kHz at full load, 420 V DC Input

Maximum switching frequency 90 kHz

Stray capacitance 350 pF

Dead time 350 ns

The voltage gain of the LLC converter resonant tank can be expressed as:

Equation 14

𝑀𝑀(𝑓𝑓𝑖𝑖, 𝜆𝜆,𝑄𝑄) =1

��1 + 𝜆𝜆 − 𝜆𝜆𝑓𝑓𝑖𝑖2�2

+ 𝑄𝑄2 �𝑓𝑓𝑖𝑖 −1𝑓𝑓𝑖𝑖�2

where:

𝜆𝜆 = 𝐿𝐿𝑟𝑟𝐿𝐿𝑚𝑚

is the ratio between the resonant tank inductance and the transformer magnetizing inductance;

𝑓𝑓𝑖𝑖 = 𝑓𝑓𝑠𝑠𝑠𝑠𝑓𝑓𝑟𝑟

is the normalized frequency ratio between the switching frequency and the resonant frequency;

𝑄𝑄 = 1𝑅𝑅𝑎𝑎𝑎𝑎

�𝐿𝐿𝑟𝑟𝐶𝐶𝑟𝑟

is the quality factor;

𝑅𝑅𝑚𝑚𝑎𝑎 = 8𝑖𝑖2𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜2

𝜋𝜋2𝑃𝑃𝑜𝑜𝑜𝑜𝑜𝑜 is the equivalent load resistance.

Under no-load conditions (Q=0) equation 14 can be written as:

Equation 15

𝑀𝑀𝑂𝑂𝐿𝐿(𝑓𝑓𝑖𝑖, 𝜆𝜆) =1

��1 + 𝜆𝜆 − 𝜆𝜆𝑓𝑓𝑖𝑖2��

In this operating condition a second resonant frequency can be defined:

Equation 16

𝑓𝑓0 =1

2𝜋𝜋�(𝐿𝐿𝑚𝑚 + 𝐿𝐿𝑟𝑟)𝐶𝐶𝑟𝑟= 𝑓𝑓𝑟𝑟 ∙ �

𝜆𝜆1 + 𝜆𝜆


22/46 DocID029850 Rev 1

Or in normalized form

Equation 17

𝑓𝑓𝑖𝑖,0 =𝑓𝑓0𝑓𝑓𝑟𝑟

= � 𝜆𝜆1 + 𝜆𝜆

In fact, in no-load conditions (the rectifier is not conducting) the total primary inductance (magnetizing plus leakage inductance) resonates with the capacitor. At this frequency the no-load gain characteristic tends to infinity.

For an infinite value of the normalized frequency the no-load gain MOL tends to M∞:

Equation 18

𝑀𝑀∞ =1

1 + 𝜆𝜆

The design steps are summarized in the following part of this document:

• Transformer turns ratio:

This is calculated assuming that the required gain at nominal input voltage is unitary:

Equation 19

𝑀𝑀𝑖𝑖𝑜𝑜𝑚𝑚 = 2𝑉𝑉𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜

𝑉𝑉𝑖𝑖𝑖𝑖_𝑖𝑖𝑜𝑜𝑚𝑚= 1 → 𝑉𝑉 =

𝑉𝑉𝑖𝑖𝑖𝑖_𝑖𝑖𝑜𝑜𝑚𝑚

2𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜=

4202 ∙ 12

= 17.5

The transformer turns ratio has been chosen equal to 18.

• Calculation of minimum and maximum voltage gain (assuming 5% margin):

Equation 20

𝑀𝑀𝑚𝑚𝑖𝑖𝑖𝑖 = 2𝑉𝑉𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜

𝑉𝑉𝑖𝑖𝑖𝑖_𝑚𝑚𝑚𝑚𝑚𝑚∙ 0.9 = 2 ∙ 18 ∙

12440

∙ 0.95 = 0.93

𝑀𝑀𝑚𝑚𝑚𝑚𝑚𝑚 = 2𝑉𝑉𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜𝑉𝑉𝑖𝑖𝑖𝑖_𝑚𝑚𝑖𝑖𝑖𝑖

∙ 1.1 = 2 ∙ 18 ∙12

400∙ 1.05 = 1.13

• Maximum input current

Equation 21

𝐼𝐼𝑖𝑖𝑖𝑖_𝑚𝑚𝑚𝑚𝑚𝑚 =𝑃𝑃𝑜𝑜𝑜𝑜𝑜𝑜

0.96 ∙ 𝑉𝑉𝑖𝑖𝑖𝑖_𝑚𝑚𝑖𝑖𝑖𝑖= 1.3 𝐴𝐴

• Equivalent load resistance

Equation 22

𝑅𝑅𝑚𝑚𝑎𝑎 =8 ∙ 𝑉𝑉2 ∙ 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜2

𝜋𝜋2 ∙ 𝑃𝑃𝑜𝑜𝑜𝑜𝑜𝑜= 75.71 Ω

• Calculation of maximum normalized operating frequency:

Equation 23

𝑓𝑓𝑖𝑖,𝑚𝑚𝑚𝑚𝑚𝑚 =𝑓𝑓𝑚𝑚𝑚𝑚𝑚𝑚𝑓𝑓𝑟𝑟

= 1.125


DocID029850 Rev 1 23/46

• Inductance ratio:

Equation 24

𝜆𝜆 =𝐿𝐿𝑟𝑟𝐿𝐿𝑚𝑚

=1 −𝑀𝑀𝑚𝑚𝑖𝑖𝑖𝑖

𝑀𝑀𝑚𝑚𝑖𝑖𝑖𝑖∙

𝑓𝑓𝑖𝑖,𝑚𝑚𝑚𝑚𝑚𝑚2

𝑓𝑓𝑖𝑖,𝑚𝑚𝑚𝑚𝑚𝑚2 − 1

= 0.34

• Calculation of the maximum value of Q to operate in ZVS at full load and minimum input voltage

Equation 25

𝑄𝑄𝑍𝑍𝑉𝑉𝑅𝑅2 =𝜆𝜆

𝑀𝑀𝑚𝑚𝑚𝑚𝑚𝑚∙ �

1𝜆𝜆

+𝑀𝑀𝑚𝑚𝑚𝑚𝑚𝑚

2

𝑀𝑀𝑚𝑚𝑚𝑚𝑚𝑚2 − 1

= 0.82 → 𝑐𝑐ℎ𝑜𝑜𝑜𝑜𝑉𝑉𝑜𝑜𝑄𝑄𝑍𝑍𝑉𝑉𝑅𝑅2 = 0.8

• Calculation of the maximum Q value to work in the ZVS with no-load condition and maximum input voltage:

Equation 26

𝑄𝑄𝑍𝑍𝑉𝑉𝑅𝑅2 =2𝜋𝜋∙

𝜆𝜆 ∙ 𝑓𝑓𝑖𝑖,𝑚𝑚𝑚𝑚𝑚𝑚

(𝜆𝜆 + 1) ∙ 𝑓𝑓𝑖𝑖,𝑚𝑚𝑚𝑚𝑚𝑚2 ∙

𝑡𝑡𝑑𝑑𝑅𝑅𝑚𝑚𝑎𝑎 ∙ 𝐶𝐶𝑍𝑍𝑉𝑉𝑅𝑅

= 3.2

𝑄𝑄𝑍𝑍𝑉𝑉𝑅𝑅 ≤ 𝑚𝑚𝑉𝑉𝑉𝑉(𝑄𝑄𝑍𝑍𝑉𝑉𝑅𝑅1,𝑄𝑄𝑍𝑍𝑉𝑉𝑅𝑅2)

The value of QZVS is chosen equal to QZVS1.

• Calculation of resonant tank components:

Equation 27

𝑍𝑍0 = 𝑄𝑄𝑍𝑍𝑉𝑉𝑅𝑅 ∙ 𝑅𝑅𝑚𝑚𝑎𝑎 = 62.4 Ω

𝐶𝐶𝑟𝑟 =1

2 ∙ 𝜋𝜋 ∙ 𝑓𝑓𝑟𝑟 ∙ 𝑍𝑍0= 31.8 𝑉𝑉𝜇𝜇

𝐿𝐿𝑟𝑟 =𝑍𝑍0

2 ∙ 𝜋𝜋 ∙ 𝑓𝑓𝑟𝑟= 124.2 𝜇𝜇𝜇𝜇

𝐿𝐿𝑚𝑚 =𝐿𝐿𝑟𝑟𝜆𝜆

= 361 𝜇𝜇𝜇𝜇

• Resonant Tank

The selected values differ from the calculations as a result of the efficiency optimization process done at an input voltage of 430 V DC (selected output PFC voltage). The resonant tank values are:

Cr=30 nF

Lr=140 μH

Lm=500 μH


24/46 DocID029850 Rev 1

The transformer has been designed to integrate both the series inductance Lr and the magnetizing inductance Lm. The resonant capacitance is realized by parallel connection of two 15 nF, 1 kV polypropylene capacitors. With the values reported above, the resulting resonant tank gain is depicted in the following picture.

Figure 15: Resonant tank gain at full load, half load, no load

The frequency at full load and 430 V DC input is 77.7 kHz. The minimum operating frequency at full load and minimum input voltage is 68.3 kHz. The maximum operating frequency is obtained with no load and maximum input voltage and is equal to 96.3 kHz.

• Half-bridge MOSFETs selection:

The power MOSFETs used on the primary side of the LLC converter have 600 V breakdown voltage and drain current of 11.3 A at 100 °C case temperature and 0.188 Ω maximum drain-to-source resistance.

The part number of this device is STP25N60M2-EP, characterized by using the MDmesh™ M2 EP technology which ensures very low on-resistance and optimal switching performance making them ideal for this application.

The breakdown voltage is selected considering the following equation:

Equation 28

𝑉𝑉𝑏𝑏𝑟𝑟 ≥ 1.2𝑉𝑉𝑖𝑖𝑖𝑖_𝑚𝑚𝑚𝑚𝑚𝑚 = 540 𝑉𝑉

where 20% derating is considered.


DocID029850 Rev 1 25/46

• SR MOSFETs selection:

The power MOSFETs used on the secondary side for synchronous rectification are characterized by 60 V breakdown voltage and 185 A drain current at 100 °C PCB temperature. They feature extremely low drain-to-source resistance, ideal to keep secondary side conduction losses low thanks to the 7th generation of STripFET™ DeepGATE™ technology. The part number is STL220N6F7 which is packaged in a Power Flat 5X6. Two of these devices are parallel-connected on each side of the rectifier circuit in order to minimize conduction losses.

The LLC converter parameters resulting from the design are summarized in the following table:

Table 6: LLC converter parameters Parameter Value

Magnetizing inductance 500 µH

Resonant inductance 140 µH

Transformer turns ratio 18

Resonant capacitor 30 nF

Resonant frequency 77.7 kHz

Maximum switching frequency 96.3 kHz

Minimum switching frequency 68.3 kHz

Input voltage operating range 400 V to 440 V

Output voltage 12 V

Primary side MOSFETs STP25N60M2-EP

SR MOSFETs STL220N6F7


26/46 DocID029850 Rev 1

3.1 LLC converter firmware overview and control algorithm The LLC firmware is implemented on the secondary side MCU which is the STM32F334x, a 32-bit microcontroller from the STM32 family. The control strategy generates the gate signals for both primary and secondary side MOSFETs in order to ensure precise output voltage regulation at 12 V DC.

The secondary side MOSFETs are used to reduce the conduction losses produced by standard output rectifier diodes. The SR MOSFETs are properly controlled by the MCU implementing a synchronous rectification control strategy which improves the efficiency and compensates for delays caused by hardware components and parasitic elements.

The block diagram of the control scheme is shown below. Figure 16: Block diagram of the LCC converter control

A simple voltage control loop, based on the use of a PI regulator whose input is the error between the reference voltage and LLC converter output voltage, is adopted.

The STM32F334x high resolution timer HRTIM generates the driving signal pattern to control the primary and secondary MOSFETs. The HRTIM is specifically designed to drive power conversion systems. It is characterized by a modular architecture and can generate up to ten digital signals with either independent or coupled waveforms.

The HRTIM has timing measure capabilities and links to built-in ADC and DAC converters. It features light load management mode and is able to handle various fault schemes for safe shutdown purposes. The HRTIM can be partitioned into several sub modules:

• The master timer • The timing units (timer A to timer E) • The output stage • The burst mode controller • An external event and fault signal conditioning logic • The system interface


DocID029850 Rev 1 27/46

The HRTIM is configured as follows to drive the LLC stage with synchronous rectification:

• The master timer is used for synchronization of Timer A, C and D • Timer C is used for primary half-bridge modulation • Timer A and Timer D are used for secondary synchronous rectification • Timer C is configured in half mode and drives two complimentary outputs CHC1 and

CHC2 with 50% duty cycle and a suitable dead time.

Timer A output CHA1 and Timer D output CHD1 are used to generate the two synchronous rectification MOSFET modulation signals. The ON and OFF time of each driving signal generated by Timer A and Timer D is dynamically adjusted and depends on the drain-to-source voltage of the synchronous rectification MOSFETs. These voltages are acquired by two 5 MHz ADC converters, namely ADC1 and ADC2. The utilization of the two A/D converters is shown in the following figure.

Figure 17: STM32F334x ADC1 and ADC2 utilization

The hardware is configured to acquire some other measurements such as heatsink temperature, auxiliary power supply output voltage, LLC transformer primary current and its average value.

ADC1 CH1 acquisition is triggered by the update event of the master timer, while CH2 and CH3 acquisitions are triggered by either timer A or timer C compare events. Similarly, ADC2 CH2 and CH3 are triggered by either timer C or timer D compare events. The injected acquisition sequence and trigger events are shown in Figure 18: "ADC1 and ADC2 injected acquisition sequence and trigger events" while the HRTIM timing configuration is shown in Figure 19: "HRTIM timing configuration".


28/46 DocID029850 Rev 1

Figure 18: ADC1 and ADC2 injected acquisition sequence and trigger events

Figure 19: HRTIM timing configuration

The voltage control loop consists of a standard PI regulator and is executed at the update event of the master timer. The regulator output is the new value of the primary MOSFET driving signal period in terms of number of clock cycles (new value of HRTIM_MPER register). In this way, the frequency can vary from 70.3 kHz up to 130 kHz, while the duty cycle is fixed at 50%. Together with the period, the new rising and falling edges of the SR signals are calculated. The calculation includes a blanking time to take into account the opto-isolator delay and the delay due to the sampling and acquisition of SR MOSFETs drain-to-source voltage.

The SR control algorithm tries to maintain the two drain-to-source voltage ADC samples (each drain-to-source voltage is sensed twice) under/above a reference value to detect the correct turn-on and turn-off of SR MOSFETs. If the first and second samples are not under/above the preset reference value, the on-time is made longer or shorter.


DocID029850 Rev 1 29/46

The LLC converter firmware structure and its main tasks are highlighted in Figure 20: "LLC firmware structure overview" and,Table 7: "LLC firmware tasks" respectively.

Figure 20: LLC firmware structure overview

Table 7: LLC firmware tasks

Function Task Execution frequency Priority

HRTIM_MASTER_IRQHandler()

Voltage control loop Synchronous rectification

Burst mode

HRTIM master frequency Medium

HRTIM_TimerC_IRQHandler() Output short-circuit protection Comparator trigger High

USART1_IRQHandler() Acquisition of PFC status On acquisition Low

main()

State machine LED

Serial communication Temperature check

Low

The STM32F334xx devices embed 3 comparators that can be used either as standalone devices (all terminals are available on I/Os) or combined with the timers. They can be used for a variety of functions such as wakeup from low-power mode triggered by an analog signal, analog signal conditioning and cycle-by-cycle current control loop when combined with the DAC and a PWM output from a timer.

In this design an internal comparator is used to implement the output overcurrent protection. The configuration is shown in Figure 21: "STM32F334x internal comparator configuration for overcurrent protection" where the inverting pin of the microcontroller internal comparator COMP2 is connected to CH1 of DAC1 and the non-inverting pin is connected to the output of the current sense circuit used to measure the LLC converter primary current.


30/46 DocID029850 Rev 1

Figure 21: STM32F334x internal comparator configuration for overcurrent protection

When the sensed current is higher than the preset threshold, a fault event is generated to set the Timer C output channels in idle state. In addition, the HRTIM Timer C interrupt is generated to set the state machine in LCC_STOP state. After such an event, the state is updated to LLC_WAIT and, after this, the new state is LLC_OFF. If no faults are detected the LLC converter can be started again after the PFC bus voltage ramp-up.

Burst mode operation is implemented for light load management. The main purpose is to increase the efficiency of the converter by reducing the number of transitions on the outputs and the associated switching losses. The STM32F334C8 burst mode controller allows having the outputs alternatively in IDLE and RUN state, by hardware, so that some switching periods are skipped with a programmable periodicity and duty cycle.

The burst mode operation is enabled when the output of the voltage control PI regulator is lower than a predefined threshold (switching period) corresponding to a switching frequency of 115 kHz. Similarly, it is disabled when the PI regulator output is greater than a threshold corresponding to 110 kHz. In this way, the output voltage is regulated at 12 V ± 100 mV during no-load and light load operation.

AN4930 Experimental characterization

DocID029850 Rev 1 31/46

4 Experimental characterization This section includes the validation results of the 500 W digital power supply design. It includes the efficiency and power quality test results at different input voltage values and the main waveforms of the two converters.

The power supply efficiency measured at different mains voltages, namely 120 VAC and 230 VAC, is shown in Table 8: "Efficiency measurements at 120 VAC" and Table 9: "Efficiency measurements at 230 VAC".

The efficiency was measured in the following conditions:

1. The board was operated at half load for 30 minutes. 2. The efficiency results were taken in the following output load points: 6 A, 12 A, 18 A,

24 A, 28 A, 34 A, 42 A. 3. The input and output voltages were measured directly at the input and output

connectors of the board. 4. All the measurements were taken using the Voltech PM6000 Universal Power

Analyzer 5. The power measurements do not take into account the power consumption of the fan

which will be activated above 300 W. 6. The board was tested with open frame at an ambient temperature of 25 °C.

Table 8: Efficiency measurements at 120 VAC VIN (V) IIN (A) PIN (W) VOUT (V) IOUT (A) POUT (W) Efficiency (%)

120 0.71 81.84 12.07 6 72.76 88.91

120 1.33 156.67 12.03 12 144.58 92.29

120 1.96 233.08 12.01 18 216.49 92.88

120 2.60 310.67 12.02 24 288.74 92.94

120 3.04 363.90 12.03 28 337.48 92.74

120 3.71 443.76 11.99 34 409.37 92.25

120 4.61 551.78 12.01 42 505.69 91.65

Table 9: Efficiency measurements at 230 VAC VIN (V) IIN (A) PIN (W) VOUT (V) IOUT (A) POUT (W) Efficiency (%)

230 0.45 80.22 12.1 6 72.62 90.53

230 0.73 155.04 12.04 12 144.47 93.18

230 1.04 231.23 12.01 18 216.56 93.65

230 1.37 307.69 12.04 24 288.63 93.80

230 1.59 359.98 12.03 28 336.62 93.51

230 1.94 440.10 11.99 34 410.26 93.22

230 2.40 545.60 12.01 42 505.5 92.65

The peak efficiency is obtained at 230 VAC input is equal to 93.2%. For 120 VAC input the peak efficiency is reduced to 92% due to higher input to output voltage ratio.

Experimental characterization AN4930

32/46 DocID029850 Rev 1

Table 10: "DSMPS power factor and current THD% at 120 VAC"and Table 11: "DSMPS power factor and current THD% at 230 VAC" report the measurement of current THD% and power factor both at 120 V and 230 VAC input voltage. It can be noted that the total harmonic distortion is still low even for high input voltage values. The power factor is close to unity for both low and high input voltage values.

Table 10: DSMPS power factor and current THD% at 120 VAC Output load at 120 V AC PF THD%

6 A 0.965 5.4

12 A 0.984 5.4

18 A 0.992 4.2

24 A 0.994 3.5

28 A 0.996 3.2

34 A 0.996 3.2

42 A 0.997 4.3

Table 11: DSMPS power factor and current THD% at 230 VAC Output load at 230 V AC PF THD%

6 A 0.78 13.6

12 A 0.925 11.4

18 A 0.964 9.7

24 A 0.977 8.9

28 A 0.983 7.9

34 A 0.986 7.6

42 A 0.989 7.4

Figure 22: PFC inductor current at 120 V input, full load

Figure 23: PFC inductor current at 230 V input, full load

The PFC inductor currents are shown together with the input voltage in Figure 22: "PFC inductor current at 120 V input, full load" and Figure 23: "PFC inductor current at 230 V input, full load". It is possible to highlight that only one branch of the bridgeless PFC circuit is switching during each half period of the input voltage.


DocID029850 Rev 1 33/46

The PFC efficiency in the whole operating range is highlighted in Figure 24: "PFC circuit efficiency" and is as high as 98%. The power factor for 120 V and 230 V AC input is depicted in Figure 25: "PFC input current power factor" for an output load varying form 70 W up to 500 W. In this operating range the power factor is always higher than 0.9.

Figure 24: PFC circuit efficiency

Figure 25: PFC input current power factor

Figure 26: PFC inductor L2 (blue) and L1 (green) current and MOSFET Q1 drain voltage

(purple) at 120 V, 60 Hz input, full load

Figure 27: PFC inductor L1 (green) L2 (blue) and current and MOSFET Q2 drain voltage

(purple) at 120 V, 60 Hz input, full load

Figure 26: "PFC inductor L2 (blue) and L1 (green) current and MOSFET Q1 drain voltage (purple) at 120 V, 60 Hz input, full load" and Figure 27: "PFC inductor L1 (green) L2 (blue) and current and MOSFET Q2 drain voltage (purple) at 120 V, 60 Hz input, full load" show the inductor currents and PFC MOSFETs drain-to-source voltage at full load for 120 V operation. Figure 28: "PFC inductor L2 (blue) and L1 (green) current and MOSFET Q1 drain voltage (purple) at 230 V, 50 Hz input, full load"and Figure 29: "PFC inductor L1 (green) L2 (blue) and current and MOSFET Q2 drain voltage (purple) at 230 V, 50 Hz input, full load"show the same waveforms for 230 V operation. In both cases the PFC is operating in DCM.

The LLC converter main switching waveforms are shown in Figure 30: "LLC converter, MOSFET Q12 Gate signal (yellow), drain current (blue), drain voltage (purple) at full load (42 A output)" and Figure 31: "LLC converter, MOSFET Q12 Gate signal (yellow), drain current (blue), drain voltage (purple) at no load" for full load and no-load operation, respectively. The MOSFET current is negative before the device is turned on thus providing zero voltage switching.


34/46 DocID029850 Rev 1

The switching frequency at full load and nominal input voltage is 77 kHz while during no-load operation the burst mode is enabled and the switching frequency can vary in the 115-130 kHz range. The operating switching frequency for different load currents is reported in Figure 32: "LLC switching frequency vs. output current", while Figure 33: "LLC converter efficiency" shows the LLC converter efficiency in whole operating range at nominal input voltage.

Figure 28: PFC inductor L2 (blue) and L1 (green) current and MOSFET Q1 drain

voltage (purple) at 230 V, 50 Hz input, full load

Figure 29: PFC inductor L1 (green) L2 (blue) and current and MOSFET Q2 drain voltage (purple) at

230 V, 50 Hz input, full load

Figure 30: LLC converter, MOSFET Q12 Gate signal (yellow), drain current (blue), drain voltage (purple) at full load (42 A output)

Figure 31: LLC converter, MOSFET Q12 Gate signal (yellow), drain current (blue), drain

voltage (purple) at no load


DocID029850 Rev 1 35/46

Figure 32: LLC switching frequency vs. output current

Figure 33: LLC converter efficiency

The impact on the power supply regulated 12 V output voltage when the load is increased from 10% to 90% of the nominal value is shown in Figure 34: "Load transition from 10% to 90% max load (max load=42 A) with 120 V, 60 Hz AC input", Figure 35: "Load transition from 90% to 10% max load (max load=42 A) with 120 V, 60 Hz AC input" and Figure 36: "Repetitive dynamic load variation 10% to 90% max load". In every case the output voltage is tightly regulated and the steady state operation is restored in less than 5 ms.

Figure 34: Load transition from 10% to 90% max load (max load=42 A) with 120 V, 60 Hz

AC input

Figure 35: Load transition from 90% to 10% max load (max load=42 A) with 120 V, 60 Hz

AC input


36/46 DocID029850 Rev 1

Figure 36: Repetitive dynamic load variation 10% to 90% max load

Figure 37: Startup at full load (42 A), 230 V, 50 Hz input voltage; PFC bus voltage (yellow), 12 V output (purple); output current (green

and blue)

The typical converter waveforms at startup are shown in Figure 37: "Startup at full load (42 A), 230 V, 50 Hz input voltage; PFC bus voltage (yellow), 12 V output (purple); output current (green and blue)". The bus DC voltage is initially regulated at 400 V. As soon as the output current has reached the steady state value, the bus DC voltage is increased to 430 V.

Figure 38: Input current waveform at full load, 120 VAC

Figure 39: Input current waveform at full load, 230 VAC

Finally, Figure 38: "Input current waveform at full load, 120 VAC" and Figure 39: "Input current waveform at full load, 230 VAC" show the input current waveforms at 120 V and 230 VAC input at full load.

AN4930 Schematic diagrams

DocID029850 Rev 1 37/46

5 Schematic diagrams

Figure 40: STEVAL-ISA147V3 circuit schematic (1 of 6)

F1

FU

SE

Q1

Q2

ST

P42

N60

M2-

EP

G_PF

C1

- OUT

PFC

+ O

UTPF

C

PFC

VAC

PFCCS1

+3.3

Prim

ary

GN

D1

GN

D1

GN

D1+3

.3Vpr

i+3

.3Pr

imar

y

GN

Dpr

i

PFC

CS2

R39

1K

R41

1K

R32

10K

R40

2000

R43

5K1

R21

6. 8

R15

22

GN

D1

GN

D1

GN

D1

13

24

T5MUR

ATA

5302

0C

13

24T4

MUR

ATA

5302

0C

C22

1nF

C15

4n7 Y

2116

6486

C18

4n7 Y

2116

6486

31

24 L6 1636

294

123JP

1

Head

er3

31

D7 STPS

C100

6D

31

D8ST

PSC1

006D

L1

500u

H10

AL2 50

0uH

10A

G_PF

C2R1

622

C20

100n

F

R22

6.8

D1

1

BA

R43

AS

notc

onne

cted

C83

100n

F

GN

D1

R38 10

K+3

.3Pr

imar

y

C65

8n2

1 2

D9 1N40

07

C35

100uF450V1166652

GN

D1

GN

D1

GN

D1

EART

H

1 3

4 2

L3 1636

294

C14n7 Y

2116

6486

C46

4n7 Y

2116

6486

EART

HEA

RTH

EART

H

R18

nc

GN

D1

R50

nc

GN

D1

GN

D1

R3 470K9241108

C53

560nF1890496

C64

560nF1890496

C16

560nF1890496

C12

560nF1890496

C17

560nF1890496

C19

560nF1890496

D14

STPS

1L30

9907

491

C21

1uF

X217

8189

4

C24

1uFX21781894

C26 1uFX21781894

12

D10

1N40

07

12

D13

1N40

07

12

D12

1N40

07C1

4

100uF450V1166652

C36

100uF450V1166652

C34

100uF450V1166652

C25

560nF1890496

C23

560nF1890496

R49

0

R51

0

OUT

4

V- 2

IN+

1IN

-3

V+5

U6

TSV6

11

R4

470K

9241

108 R6 470K9241108

R27

470K

9241

108

R31

470K

9241

108

R36

470K

9241

108

R26

470K

9241

108

R30

470K

9241

108

R34

470K

9241

108

C76

3.3nF G

ND1

C71

3.3nF

GN

D1

D19

STPS

1L30

9907

491

C96

4n7 Y

2116

6486

C97

4n7 Y

2116

6486

EART

H2

EART

H2

EART

H2

GSPG0903151420SG

ST

P42

N60

M2-

EP

Schematic diagrams AN4930

38/46 DocID029850 Rev 1


12

4 5 6

3

U9

ACP

L-P 4

8420

7025

4

6

15 13 1012

3

T7

TR

AN

SFO

RM

ER

LP45

25-H

12

4 5 6

3

U10

ACP

L -P4

8420

7025

4

12V

GD

_1 GD

_2

GD

R_2

GD

R_1

USA

RT

1R

XPr

imar

y

US A

RT

1T

XP r

ima r

y

3.3 V

pri

USA

RT

1T

XSe

cond

ary

USA

RT

1R

XSe

cond

ary

GN

D2

GN

D2

GN

D2

GN

D2

GN

D2

+3.3

Vpr

i

GN

Dpr

i

3.3V

pri

GN

D2

GN

Dse

c

3.3V

sec

+Vcc +V

cc

Bri

dge

HS_

P

Bri

dge

LS_

P

Bri

dge

HS_

P_M

CU

Bri

dge

LS_

P_M

CU

Bri

dge

curr

ent

OU

T

+ O

UT

PFC

- OU

TPF

C

VD

rain

1

1234G

ND

5

Vo

6 7

Vcc

8

U11

PS98

21/K

B35

7N

T

1 2 3 4G

ND

5

Vo

67

Vcc

8

U12

PS98

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B35

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T

GN

D2

R77

300

R80

300

R79

300

R82

0

R83

39/2

00fo

r35

7N

T

R81

0 R84 39

/200

for

357

NT

R86

0

R74

20

R85

0

C4515nF1854929

C48

100n

F

C39

1500uF16V1551414

D23

1N4148W1469425MMSD914

D20

1N4148W1469425MMSD914

C80

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4kV

GN

D2

C47

100n

F C49

100n

F

C50

100n

F

C43

220pF1216461

C44

10u

F21

1270

5

Cap

LLC

Q3

STP2

5N60

M2-

EP

Q4

N.C

.

3.3V

sec

+3.3

Vse

cond

ary

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C8415nF1854929

T2

GN

D2

D33

1N41

48W

1469

425

D36

1N41

48W

1469

425

R33

39

GN

D2

R37

1KC

8922

pF

R29

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C87

3uF

GN

D2

curr

ent_

AV

G

curr

ent_

cycl

e

D37

BA

T75

4

3.3V

sec

C40

1500uF16V1551414

C41

1500uF16V1551414

C42

1500uF16V1551414

C90

10uF X7R2112722

C88

10nF

Q8

Q6

STL

220

N6F

7

Q7

Q10

Q11

Q12

R42

39

R44

47R35

47

C91

10uF X7R2112722

C92

10uF X7R2112722

C93

10uF X7R2112722

12

34

56

78

910

1112

1314

P6

Hea

der

7X2H

1551

388

1 2 3

P7 FAN

GN

D2

R52

20R

5620

D28

BA

T75

4

3.3V

sec

Q9

PMB

F170

1081

473

GN

D2R94

100

R97

300

Dis

char

ge

R10

00

R10

4

0

R10

1nc

/820

for

357

NT

R10

3

nc/8

20fo

r35

7N

T

Q14

Q13

N.C.

Q15

STN

4NF0

3LR

111 33

0

GN

D2

FAN

switc

h

Q17

Q16

N.C

.

V D

rain

2V

Dra

in2

VD

rain

2

R11

5

0(n

c)G

ND

2

GSPG0903161500SGSTL220N6F7

N.C.

N.C

.ST

L22

0N

6F7

STL220N6F7

STP2

5N60

M2-

EP

N.C

.

MA

GN

ETIC

A 2

4.34

0.00

2


DocID029850 Rev 1 39/46


ENB

28

ENB

11

PWM

12

GN

D3

PWM

24

OU

T17

VC

C6

OU

T25

IC1

PM88

34

VC

C3

GN

D4

HIN

2

LIN

1

BO

OT

8

HV

G7

OU

T6

LVG

5

U7L6

387E

(not

mou

nted)

Brid

geH

S_P

Brid

geLS

_P

GD

_1

OU

T

GD

_2

GD

R_1

PFC

PWM

1

PFC

PWM

2

LLC

Driv

er se

ctio

n - P

rimar

y

Rect

ifica

tion

- Sec

onda

ry

LOW

SID

E M

OSF

ET D

RIVE

R

PFC

Driv

er se

ctio

n

SR2

GN

Dse

c

GN

D2

+Vcc

END

RPF

C

GN

Dpr

i

+Vcc

R55

82

R61

330

R53

360

R57

360

C31

100p

F(n

ot m

ount

ed)

C30

100n

F

D15

BA

T754

D16

BA

T754

ENB

28

ENB

11

PWM

12

GN

D3

PWM

24

OU

T17

VC

C6

OU

T25

IC2

PM88

34

GD

R_2

LOW

SID

E M

OSF

ET D

RIVE

R

SR1

GN

D2

12V

ENSY

NC

REC

T

R60

330

R11

80

R11

70

G_P

FC1

G_P

FC2

C32

100p

F(n

ot m

ount

ed)

C28

4u7

(not

mou

nted

)C

29

100n

F(n

ot m

ount

ed)

C33

100n

F

D17

BA

T754

6VV

iper

D18

BA

T754

C73

1uF

C72

1uF

(not

mou

nted

)

C86

1uF

HIN

3

VC

C4

SD/O

D2

LIN

1

LVG

8PG

ND

7SG

ND

6D

T5

CP-

9C

P+10

OU

T12

HV

G13

BO

OT

14U

8

L649

1D

Brid

geH

S_P

Brid

geLS

_P

OU

T

+Vcc

C85

100p

FC

8210

0pF

C77

4u7

C79

100n

FC

781u

F

R23

0+V

ccC

81nc

R20

10K

R25

1K

SDL6

491D

R54

3.3

R58

3.3

R59

82

R62

10K

R63

10K

GN

D2

R64

10K

Q5

PMB

F170

1081

473R

65nc

R67

330

R68

nc

R66

300

+Vcc

+3.3

Vpr

i

+3.3

Prim

ary

+3.3

Prim

ary

GSPG0903161445SG


40/46 DocID029850 Rev 1


PF0/O

SC_i

n2

PF1/O

SC_o

ut3

NRS

T4

VD

Da5

PA2

8PA

17

PA0

6

PA3 9PA4 10PA5 11PA6 12PA7 13PB0 14PB1 15PB2/BOOT1 16

VDD

17PA

818

PA9

19PA

1020

PA11

21PA

1222

PA1 3

2 3PA

1424

PA1525 PB326 PB427 PB528 PB629 PB730 BOOT031 PB832

VDD

1

U13

STM

32F0

51K

x

PFC

CS1

Brid

gecu

rrent

PFCVAC

USA

RT1

RXPr

imar

y

USA

RT1

TXPr

imar

y+3

.3V

pri

+3.3

Prim

ary

+3.3

Prim

ary

+3.3

Prim

ary+3

.3Pr

imar

y

+3.3

Prim

ary

END

RPF

C

GN

Dpr

i

+3.3

Prim

ary

+3.3

Prim

ary

test

1T9 Te

stpo

int

1 2 3 4

P4 Hea

der4

test 1T8 Test

poin

t

+O

UTPF

C

PFC

CS2

R93

620

R96

3K9

R91

180K

C51

100n

F

R87

10K

D24

LED

1058

385

C56

1uF

C55

100n

F

C57

100n

F

C58

10nF

L4

D25

BAT7

54

PFC

PWM

1

PFC

PWM

2

R92

180K

R95

180K

+3.3

Prim

ary

D38

BAT7

54

C94

47pF

C95

47pF

I2C1_SCL

I2C1_SDA

1 2 3 4

P3 Hea

der4

SDL6

491D

R45

470

P2 DAC

out

C67

100n

F

GN

D1

+3.3

Prim

ary

VO

2+V

S1

3

GNDU

5LM

19CI

Z

C27

100n

F

R17

470

R28

470

C52

10nF

C68

22nF

GN

D1

D21

BAT7

54

D22

BAT7

54

R108

330

R109

330

+3.3

Prim

ary

+3.3

Prim

ary

GSPG0903161515SG


DocID029850 Rev 1 41/46


GN

D2

GN

D2

GN

D2

GN

D2

GN

D2

GN

D2

10K

R99

GN

D2

GN

Dse

c

GN

D2

+3. 3

Vse

c ond

ary

VC

C

VC

C

VC

C

VC

C

VC

C

VC

C

GN

D2

US A

RT

1R

XSe

cond

ary

USA

RT

1T

XSe

cond

ary

12V

EN

SYN

CR

EC

T

VC

C

GN

D2

6V Viper

P5

1 2 3 4

Hea

der4

1T12

T13

Test point

test 1

L5

GN

D2

GN

D2

VC

C

Vbbaa

ttPCC

1133PCC

1144//OO

SSCC3322

iinnPCC

1155//OO

SSCC3322

oouutt

PDD00//

OOSSCC

iinnPDD

11//OO

SSCCoouu

ttN

RRSSTT

VSSSS

aV

DD

aP A

0PA

1PA

2

1 2 3 4 5 6 7 8 9 10 11 12

PA3PA4PA5PA6PA7PB0PB1PB2PB10PB11

VSS_2VDD_2

131415161718192021222324

VD

D_3

VSS

_3PA

13PA

12PA

11PA

10PA

9PA

8PB

15PB

14PB

13PB

12

36 35 34 33 32 31 30 29 28 27 26 25

VDD_1VSS_1PB9PB8BOOT0PB7PB6PB5PB4PB3PA15PA14

484746454443424140393837

U14

STM

32F

334

VC

C

GN

D2

GN

D2

GN

D2

VC

C

VC

C

GN

D2

GN

D2

R98

200

R10

70

R11

40

R11

236

0

R10

636

0D

30

R11

02k R

113

2k

R10

51K

0.1%

12

Y2

8Mhz

HC

49/U

S

D26

LED

1058

385

C62

20p

F

D27

BA

T75

4

D32

BA

T75

4

R10

2

4K3

0.1%

C61

20p

F

C63

1uF

C3

100n

F

C66

1nF

C69

100n

F

C75

47p

F

C70

47p

F

C60

100n

F

C59

100n

F

C74

100n

F

D29

BAR

43S

D35

B AR

43S

BA

T75

4

D34 B

AT

754 VD

rain

1

VC

C

VC

C

SRle

g 1

R69

0R

460

R47

0

GN

D2

C37

100n

F

GN

D2

C38

100n

F

GN

D2R

2447

0

R19

470

Tem

pSR

out

P8

1 2 3 4

Hea

der4

GN

D2

C54

10nF

Temp SR outcurrent_cycle

R70

0

R48

R710

R72 0

SRle

g2

R73

0

R76

0R

780

R88

0R

890

R90

0

R75

0

SR1

Brid

geH

S_P_

MC

UB

ridge

LS_P

_MC

U

SR2

cu rrent_AVG

Discharge

VD

rain

2

VC

C 1

123

P9I2

C

GN

D2

FAN

switc

h

U15

LM19

CIZ

+VS

VO

GN

D

2

3

C98

n c(4

7to

100

nF)

GN

D2

tom

ain

GN

D2

0

test

Test point

GSPG0903161540SG


42/46 DocID029850 Rev 1


BR CO

NT

DR

AIN

SOU

RC

E

CO

NT R

OLVD

D

F B 42

8 1

35

7

U2

VIP

ER

27H

N

1 2

4 3

OP

T O1

PC

817

D

6V V

iper

-OUT

PFC

+3.3

Vpr

i

GN

Dpr

i

+Vcc

GN

Dse

c

GN

D2

GN

D2GN

D2

GN

D2

R2 3.3

R11

33K

R12

nc

R13

47K

R14

4.3K

R10

160K

R9 16K

R8 1.8K

R7 180K

R1 1R5 2.

4K

D3ST

TH1L

06D2

1.5K

E250

97

2145

86

TR1

Vipe

r tra

nsfo

WE

MID

COM

A 5K3NC 1

4

NC2

VREF

U3TS43

1ILT

D1 STPS

2L40

1 2

P1 Head

er2

C10

ncC1

122

nF

GND 1Vin3

Vout

2

U4LD1117

GND 1Vin3

Vout

2 Vout

4

U1 LD11

17D4

1N41

48W

1469

425

C6 100u

F16

V17

8061

5

C8 100u

F25

V17

8061

5

C13

100u

F16

V17

8061

5

+ O

UTPF

C

C9 120n

F

C7 82nF

D6 BAR4

6D5 BA

R46

+3.3

Vse

cond

ary

C2

470uF16VYXF

C4 22uF

35V

1899

657

C5 1uF

GSPG0903161400SG

AN4930 Conclusions

DocID029850 Rev 1 43/46

6 Conclusions This application note describes the design of a 500 W fully digital switch mode power supply. The system is based on a two-stage architecture consisting of a semi-bridgeless PFC circuit and an LLC half-bridge DC-DC stage. The control architecture is designed around two 32-bit MCUs from the STM32 family of microcontrollers. The control algorithm for both the PFC and the LLC converters is highlighted throughout the document. The experimental evaluation shows that high efficiency (93.2%), near unity power factor, and low THD% can be achieved under wide input voltage and load current conditions thanks to the performance of the ST products used and to the implementation of suitable control strategies on high-performance 32-bit microcontrollers.

References AN4930

44/46 DocID029850 Rev 1

7 References • AN2450: LLC resonant half-bridge converter design guideline • High frequency transformer for 500 W LLC converter: Magnetica 1892.0039 • Inductor chokes for 500 W bridgeless PFC: Yujing Technologies 11999-126H400210

QP-3930H

AN4930 Revision history

DocID029850 Rev 1 45/46

8 Revision history Table 12: Document revision history

Date Revision Changes

12-Oct-2016 1 Initial release.

AN4930

46/46 DocID029850 Rev 1

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Documents

500 W fully digital AC-DC power supply (D-SMPS) evaluation ... · Figure 1: STEVAL-ISA147V3 evaluation board . This application note focuses on the design of STEVAL-ISA147V3, a 500