7-17-16-15-1

ECE 3EJ4Electronic Devices & Circuits II

Lecture Set 7 – Mixed Signal Lecture Set 7 – Mixed Signal CircuitsCircuits

Prof. M. Jamal DeenProf. M. Jamal Deen

Professor and Senior Canada Research ChairDept. of Electrical and Computer Engineering

McMaster University Hamilton, ON L8S 4K1, Canada

7-27-26-25-2

Analog and Digital Analog and Digital (Mixed) Signals(Mixed) Signals

(Only Class Notes and Cited References Available)(Only Class Notes and Cited References Available)

Control Input

T

P

L

H

7-3

Applications of Data ConvertersApplications of Data Converters•Precision sensor signal conditioning and data acquisition• Industrial Process Control

►Liquid/Gas Chromatography►Portable Applications

•Sensors►Weigh Scale►Pressure Transducers►Pressure►Intelligent Sensors►Temperature

http://www.analog.com/library/analogDialogue/archives/39-06/Chapter%208%20Data%20Converter%20ApplicationsF.pdfhttp://www.national.com/vcm/national3/en_US/global/files/national_automotive_solutions.pdfhttp://www.national.com/appinfo/adc/files/ABCs_of_ADCs.pdf

•Instrumentation►Gas Monitoring►Portable Instrumentation► Blood Analysis►Medical Instrumentation►Portable Instruments►Smart Transmitters

• Car Instrumentation►Safety►Environmental

Sustainability►Connectivity

7-4

Digital and AnalogDigital and Analog•Digital - greater accuracy and

reliability►Versatility and cost

►Comprehensive theory, algorithms

►Availability of CAD tools

►Manufacturing - optimized, low-cost device processes

•Digital circuits – used in►Computers, data processing

►Electronic calculators and instrumentation

►Control devices

►Communication equipment, telephone networks, cell phones

►Entertainment – CD, MP3 Players, TV, radio, camera

►Medical equipment

• Analog - advantages► Most physical phenomena of

interest are analog

► Required for most real situations

• Transducers are simple

• Potentially high precision

• Analog - disadvantages► Analog components - drift,

distortion, noise, offsets, etc.

► Errors in analog signals - accumulate during processing, transmission, and storage

► Relatively simple signal processing practical for most applications

7-5

Digital CircuitsDigital Circuits

• Advantages

►Signal strength easily restored

►Not much degradation of signal

accuracy during processing,

transmission and storage

►Components are cheap, reliable

and consume low-power

►Digital signal processing can be

highly sophisticated using

special-purpose hardware or

software - programmable digital

signal processors or computers

• Disdvantages► Limited signal precision - number

of bits used to encode each sample

► Analog-to-digital converters and digital-to-analog converters are required to interface a digital system with real-world analog signals

7-67-66-65-6

Introduction – Digital-to-Introduction – Digital-to-Analog Converters Analog Converters

(DACs)(DACs)

7-7

Digital-to-Analog ConverterDigital-to-Analog Converter• For n-bit binary input word (b1, b2, …, bn),

output of DAC expressed as

► VFS - full scale voltage

► VOS - offset voltage

• Smallest voltage change that can occur at DAC output takes place when LSB in digital word changes from 0 to a 1

• This minimum voltage change is resolution of converter

• Conversion rate - clock speed of input signal and settling time of DAC

Digital-to-Analog

Converter

+-

Vref

+Vo

-

b1,b2,b3, …bn

O 2 O1 2

1

( 2 2 ... 2 )

{1,0}

nFS n S

iFor b

V V b b b V

Resolution 2 nLSB FSV V

• DAC Characteristics► Resolution

► Linearity

► Speed

► Settling Time

► Reference Voltages

► Errors

2 1

2

n

FS REF nV V

7-8

Practical IssuesPractical Issues

DAC Errors• Gain Error

• Offset Error

• Settling time

tsettling

½ LSB+-

Analog Output Voltage

Time

7-9

Practical IssuesPractical IssuesDAC with linearity errors DAC with non-monotonic output

Inflection in the transfer functionFor one output value, two binary input are possible.

DAC Errors• Non-Linearities

• Monotonicity

7-10

DAC Realization - 1DAC Realization - 1• Weighted-R DAC circuit

• Disadvantages► Maintain accurate R ratios over wide range

► Switch “on” resistance very low

► Current drawn from voltage reference varies with binary input pattern.

► Varying I causes change in V drop in Thevenin equivalent Rsource of voltage reference data-dependent errors

REFn

no Vbbbv )2...22( 22

11

nn IIII 1

321 2...42

1 1 2 2

1 21 1 2

1 21 2

...

2 2 2 ... 2

2 2 ... 2

n n

nn

nREFn

I b I b I b I

I b b b

Vb b b

R

1 2REFI V R

1 21 22 2 ... 2 n

o n REFv IR b b b V

+

VREF

Vo

R

R

2 R 2 R …..

I

R b1 b2 bn

2R

• Inverted R-2R ladder► Wide range of R values avoided

► Currents’ in ladder and VREF are independent of digital input power dissipation does not change

7-11

Binary Weighted Resistor DACBinary Weighted Resistor DAC• Inverting summing Op-Amp

• Set input R values at multiple

powers of 2

• KCL and Op-Amp properties

V(-) = V(+) = 0 V

• Start, V1 to V3 - give each Vinput

exactly ½ effect on output as

voltage before

31 2

2 4outVV V

V RR R R

I1

I2

I3

I1 +I2+I3

7-12

Example – Weighted-R DACExample – Weighted-R DAC

3 2 1 08 4 28REF

outV

V b b b b

4n

8(0) 4(0) 2(1) 1(1)8

3

8

REFout

REF

VV

V

1 2 1 01 2 1 01

2 2 ... 2 22

n nREFout s n nn

VV V b b b b

4

4

2 10.9375

2FS REF REFV V V

Binary Weighted Resistor DAC

VREF

Vout

R

2R

4R

8RLSB

MSB0

0

1

1

R

2 1

2

n

FS REF nV V

7-13

R-2R Ladder DAC AnalysisR-2R Ladder DAC Analysis

3 02 1O 2 4 8 16

FREF

D DR D DV V

R

Take the case of VLSB connected to VREF

2REFV

4REFV

8REFV

16REFV

16fREFRV

R

16REFV

REFV

7-14

Example R-2R Ladder NetworkExample R-2R Ladder Network• Determine the voltage output by the following R-2R ladder network given the switch states shown

in table

SW0   SW1   SW2   SW3   Vout  

Ground   Ground   Ground   Vref   8 volts  

Ground   Ground   Vref   Ground   4 volts  

Ground       Vref   Ground   Ground   2 volts  

Vref   Ground   Ground   Ground   1 volt  

Ground   Ground   Ground   Ground   0 volts  

011010010101010100101101010101011111100101000010101010111110011010101010101010101010111010101011110011000100101010101010001111

Digital Input0 bit

nth bit

n bit DAC

Low-passFilter

Piece-wise Continuous Output

Analog Continuous Output

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Analog-to-Digital Analog-to-Digital Converters (ADCs)Converters (ADCs)

7-16

ADC CharacteristicsADC Characteristics• Full scale voltage - determined using VREF

2 1

2

n

FS REF nV V

Resolution 2nREFV V

VREF (V) Resolution 1LSB (mV)

1 8 3.9062

1 12 0.24414

2 8 7.8125

2 10 1.9531

2 12 0.48828

2.048 10 2

2.048 12 0.5

4 8 15.625

4 10 3.9062

4 12 0.97656

Suppose binary number with N bits - represent analog value ranging from 0 to A

There are 2N possible numbersResolution = A / 2N

7-17

Analog-to-Digital ConversionAnalog-to-Digital Conversion

• Basic concept► Step 1 sampling: get discrete signal from analog

signal (Nyquist’s critical frequency)

► Step 2 quantizing: assign an integer value to each sampling point (quantization error introduced)

► Step 3 coding: convert any integer value to binary system

11 | 2 |

2

n i FSx FS ii ni

Vv V bb selected

Analog-to- Digital

Converter

+-vx

+ VREF -

b1, b2, b3, … bn

Code sequences for a 3-bit successive approximation ADC

100

110111

110

111

101

100

011

010

001

000

101

011

001

010

T 2T 3T 4T

Final Code

Time

Successive approximation converter

An

alo

g

Inp

ut

vx

VREFv0=1 if

vx < VREF

7-18

Analog-to-Digital ConversionAnalog-to-Digital Conversion• Parallel (flash) ADC - make //, not serial

comparisons simultaneously

n-bit DAC

Successive Approximation

LogicADC Output Code10 11 00 01 10

Vx

Clock

fc

R

R

R

R

R

R

R/2

VREF

Vx

b1b2b3

+

-

+

-

+

-

+

-

+

-

+

-

+

-

Co

mb

inat

ion

al

Lo

gic

3R/2

N = # of bits in output word (2N-1) comparators neededModern electronics - possible, expensive

1 0.5 2

nFS

T c

Signal must not change by LSB V

during conversion time T n f

0

0 0

1

1 2

22

sin 2

FSFS n

FST FS n

cn

c

VdT Max V

V ff

n

no V

f

td

r

t

SAR ADCSAR ADC

7-19

• End-of-convert (EOC), data-ready (DRDY), or busy signal (actually, not-BUSY indicates end of conversion)

• DAC set either ¼ or ¾ scale depending on value of bit 1, and comparator makes decision for bit 2 of conversion.

• Result is stored in register, and process continues until all bit values determined

• When all bits have been set, tested, and reset or not as appropriate, contents of SAR correspond to value of the analog input, and conversion complete.

• Comparator SHA output > or < the DAC output, and result (bit 1, MSB of conversion) stored in SAR

7-20

3-Bit Flash ADC• Making all comparisons between

digital states and analog signal - fast conversion cycle

• Resistive voltage divider - provide digital reference states needed

• Eight reference values (including zero) for the 3-bit converter

• Voltage reference states - offset - midway between reference step values

• Analog signal - compared with each reference state

• Separate comparator required for each comparison

• Digital logic - combines several comparator outputs - appropriate binary code

Combinational Logic

Dig

ital

Wo

rd10

111

0001

0

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AliasingAliasing

• ADC's sample time - fast enough to capture essential changes in analog waveform

• Data acquisition terminology - highest-frequency waveform that ADC can theoretically capture is so-called Nyquist frequency - equal one-half of ADC's sample frequency

• If ADC circuit has sample frequency of 5000 Hz, highest-frequency waveform it can successfully resolve is Nyquist frequency of 2500 Hz

• If analog input signal frequency > Nyquist frequency for ADC, converter will output incorrect digitized signal - lower frequency

• Phenomenon is known as aliasing

• See illustration - aliasing

• Practically – do not expect ADC to resolve frequency > 1/5 to 1/10 of sample frequency

7-22

Anti-aliasing FilterAnti-aliasing Filter• ADC - usually equipped with

analog low-pass filters to pre-condition signal prior to digitization

• Prevents signals with frequencies greater than sampling rate from being seen by ADC – prevent detrimental effect - aliasing

• Analog pre-filters - known as anti-aliasing filters

• Determine which of following Sallen-Key active filters is the correct type for an anti-aliasing filter

7-23

Resolution• Temperature range of 0 K to 300 K to be linearly converted to a

voltage signal of 0 to 2.5 V, then digitized with an 8-bit A/D converter, what is the voltage step size and temperature resolution?

2.5 V / 28 = 9.8 mV, or ~ 10 mV per step

300 K / 28 = 1.2 K per step

• If a 10-bit A/D converter is used instead, what is the new step size and temperature resolution

2.5 V / 210 = 2.44 mV, or ~ 2.4 mV per step

300 K / 210 = 0.29 K per step

Is the noise present in the system well below 2.4 mV?

7-24

Noise•Quantization noise - results from quantization process- process of assigning

an output code to a range of input values

•Each conversion has average uncertainty of one-half of the step size, ½(A/2N)

•Quantization error places an upper limit on signal-to-noise ratio

Maximum (ideal) SNR ≈ 6.02 N + 1.76 dB (N = # bits)

e.g. 8 bit 49.92 db, 10 bit 61.96 db

•Signal level of 1VRMS and a noise level of 100μVRMS SNR of 104 = 80dB

•Noise level - integrated over half clock frequency

7-25

Dynamic Range• Dynamic range - ratio of the largest to the smallest possible signals

that can be resolved

• Dynamic Range = 20 * Log(2n - 1)

Resolution (Bits) Dynamic Range (dB)

6 36.0

8 48.1

10 60.2

12 72.2

14 84.3

16 96.3

18 108.4

20 120.4

7-26

Practice Problems

• The op-amp in the figure shown has an offset voltage of +5mV and the feedback resistor has a value of 1.05R. What are the offset and gain errors of this ADC?

• How many resistors are required to realize a 10-bit weighted-resistor DAC? What is the ratio of the largest to the smallest resistor?

• Tabulate the output voltages for the eight binary input words for the 3-bit DAC shown at the right. Find the linearity errors is VREF = 5 V, RREF = 250 and R = 1.2188 k?

• Suppose each switch in the DAC has an on-resistance of 200 and. What value of R is required for zero gain error? Find the linearity errors if VREF = 5 V, RREF = 250

7-27

Practice Problems• A four-bit weighted current source array with

IFS = 2 mA is connected to the summing

junction of the op-amp shown. (a) Make a table of the output voltages versus input code if R = 5k, RO = 1 kandVREF = 1 V. (b)

What is the equivalent offset current if the op-amp has an offset voltage of + 5mV?

• A 3-bit inverted R-2R ladder R = 2.5 k and VBB =

-2.5V is connected to the input of the op-amp in

the figure shown at the right. Draw a schematic

of the complete DA converter. Make a table of

the output voltages versus input codes if R1 = 5k

• A 14-bit ADC with VFS = 5.12 V has an output code of 10101010110010. What is the possible range

of input voltages?

• A 20-bit ADC has VFS = 2 V. (a) What is the value of the LSB? (b) What is the ADC output code for

an input voltage of 1.630000 V? (c) What is the ADC output code for an input voltage of

0.997003V?

7-28

Practice Problems

• A 12-bit successive approximation ADC with VFS = 2 V is designed using the

circuit shown. What is the maximum permissible offset voltage of the comparator if the offset error is to be less than 0.1 LSB. (b) repeat this question for a 20-bit ADC.

• A 16-bit successive approximation ADC is designed to operate at 50,000 conversions per second. What is the clock frequency? How rapidly must the unknown and reference voltage switches change state if the switch timing delay is to be equivalent to less than 0.1 LSB time?