223410 Linear Integrated Circuit Analysis and Designte.kmutnb.ac.th/~msn/223410intro.pdf · zForward substrate biasing (V BS>0) reduces the threshold voltage V T Îlow voltage

1

Asst. Prof. Dr. Montree Siripruchyanun

223410 Linear Integrated Circuit Analysis and Design

Introduction

Asst. Prof. Dr. MONTREE SIRIPRUCHYANUNDept. of Teacher Training in Electrical Engineering

King Mongkut’s Institute of Technology North Bangkok

Evolution of the Transceiver

1929

www.maxim-ic.com/an1768

Bulky, expensive and required high supply voltages.

2


Evolution of the Transceiver

IEEE J. Solid-State Circuits, Vol. 32, 12, pp. 2071-2088, 1997

Bluetooth Wireless Technology

3


4


Introduction

19061906 19471947

Introduction

Intel Pentium II, 1997Clock: 233MHz

Number of transistors: 7.5 MGate Length: 0.35

First integrated circuit (germanium), 1958Jack S. Kilby, Texas Instruments

Contained five components, three types:transistors resistors and capacitors

19581958 19971997

5


Trends in transistor count

(From: http://www.intel.com)

Number of transistors doubles every 2.3 years(acceleration over the last 4 years: 1.5 years)

42 M transistors

2.25 K transistors

Increase: ~20K

Trends in clock frequency

2 GHz

Intel LabsSub-ps switching transistorμP clock > 20 GHzGate length: 20nmGate oxide: 3 atomic layersIn production: 2007 !

6


Trends in feature size

0.13 μm inproduction

Intel LabsSub-ps switching transistorμP clock > 20 GHzGate length: 20nmGate oxide: 3 atomic layersIn production: 2007 !

2002 and beyond ?Semiconductor Industry Association (SIA) Road Map, 1998

Update1999 2002 2014

Technology (nm) 180 130 35Minimum mask count 22/24 24 29/30Wafer diameter (mm) 300 300 450Memory-samples (bits) 1G 4G 1TTransistors/cm2 (μP) 6.2M 18M 390MWiring levels (maximum) 6-7 7 10Clock, local (MHz) 1250 2100 10000Chip size: DRAM (mm2) 400 560 2240Chip size: μP (mm2) 340 430 901Power supply (V) 1.5-1.8 1.2-1.5 0.37-0.42Maximum Power (W) 90 130 183Number of pins (μP) 700 957 3350

IEEE Spectrum, July 1999

Special report: “The 100-million transistor IC”

These scaling trends will allow the electronics market to growth at 15% / year

7


1982Year

1987 1996 2001

100

90

80

70

60

50

40

30

20

10

BiCMOS

CMOSNMOS

PMOS

BIPOLAR ANALOG

TTL and OTHER

ECL4%

19%

22%

2%

41%

12%4%

86%

8%

MOS

BIPOLAR

39%

24%

20%

12%

4%

70%

10%

16%

PER

CEN

T

1% GaAs and others

http://smithsonianchips.si.edu/ice/cd/STATUS97/SEC04.PDF

Technology Trends

Technology Trends

Trend of supply voltage and 1/f noise from 2003 ITRS Roadmap

0.0

0.4

0.8

1.2

1.6

2002 2004 2006 2008 2010

V DD

(V)

0.00

0.04

0.08

0.12

0.16100

1/f n

oise

(mV2 /H

z)

90 80 70 65 57 50Gate Length (nm)

8


Technology Trends

Trend of supply voltage and 1/f noise from 2003 ITRS Roadmap

100

1000

2002 2004 2006 2008 2010

Freq

uenc

y (G

Hz)

0.00.20.40.60.81.0

NF m

in(d

B)

100 90 80 70 65 57 50Gate Length (nm)

Peak fmaxPeak fT

500

Trends - Commercial Wireless

Si CMOS displacement of other technologies continuesBoundary between GaAs & InP shifting to lower frequenciesCost is a key factor in determining boundaries

ITRS 2003 Roadmap, RF and AMS Technologies for Wireless Communications

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Trends in RFIC Integration

Using standard, mature CMOS processes to design RFIC building blocksWith CMOS, DSP blocks can be integrated with RF front-end on the same chip – good IP integration

kabuki.eecs.berkeley.edu/~jrudell/ IEEE Spectrum, March 2002

Trends – New Operation ModeVBS improves the MOSFET performance

Forward substrate biasing (VBS>0) reduces the threshold voltage VT low voltage applications

Forward substrate biasing (VBS>0) speeds - up the MOSFET RF applications

Reverse substrate biasing (VBS<0) reduces the drain current ID low power applications

S

D

BGVDS

VGS VBS

NMOS, 10x0.2μm

VDS=25mV

0.0 0.3 0.6 0.9 1.2Gate Voltage (V)

Dra

in C

urre

nt (A

) 0.5V

-0.5V

0V

10 -12

10-10

10-8

10-6

10-4

10


Design Techniques: Sub-ThresholdOperate transistor in weak inversion

VDS (V)

Measured

0.15

10-9

10-10

10-11

10-12

10-13

10-14

Calculation

0.20

0.10

0.04V

VGS=-0.01V

0 0.05 0.1 0.15I D

(A)

Very low VDS required to operate transistor

low-voltage applications

Drain current ID also very low

low-power applications

Proc. ISCAS, pp. I697-I700 and I701-I704, Bangkok, Thailand (May 25-28, 2003)

The Wireless Transceiver

Analog Baseband

Digital Baseband

(DSP + MCU)

PowerManagement

Small Signal RF

PowerRF

bwrc.eecs.berkeley.edu

Channelselect

Duplexer

PA

LNA Band-passfilter

Band-passfilter

LO

ADC

DAC Low

freq

uen c

ysi

gnal

proc

essi

ng

Proc. IEEE EDSSC, Hong Kong, 14-16 December 2003

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Gilbert Mixer with gm CellTechnique

IBIAS

RF-RF+

LO-

LO+ LO+

IF-(to buffer)

IF+(to buffer)

RL RL

VDDBuffer

199dB/0.18μmFoM/Technology1.9GHz/-2dBRF Input/Conversion Gain17dB/8dBmSSB Noise Figure/IIP31.2V/3.95mWSupply voltage/Power


Body-Input Mixer

202dB/0.18μmFoM/Technology1.9GHz/3dBRF Input/Conversion Gain10dB/-11dBmSSB Noise Figure/IIP30.8V/0.4mWSupply voltage/Power


VBIAS

IF-IF+

RF+RF+

RL

RL

VDD

RF-LO+ LO-

Buffer

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Folded Mixer

Buffer

LO-

RF+ RF-

Vbias

LO+ LO+

IF-IF+

RL

RL

VDD

202dB/0.18μmFoM/Technology

10dB/-2dBNoise Figure/IIP3

2.4GHz/-4dBRF Input/Conv. Gain

1V/1mWSupply voltage/Power


Passive ComponentsReduce number of off-chip passives

Increase amount of integrationReduce number of off-chip passivesSmall product: Cell phoneCost effective

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Modeling Issues of Integrated PassivesInductor

Quality factor

PN Diode and MOS VaractorTuning rangeQuality factor over tuning range

ViasMay become a concern as frequencies of RFIC reach the 10s of GHz range IMEC 2003, Microsystems

P- Substrate

N WellN+ N+

N+

Package Trends

IEEE Spectrum, July 2003

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Package Integration

RF Design, Nov. 2002

Mixed Signal Integration IssuesIssues

Substrate noise isolation between noisy digital and low noise analog circuitsCross-talk between sensitive analog circuits

Possible SolutionsCareful attention to layoutMultiple voltage sourcesGuard rings around noisy digital circuitryDouble well and triple well (deep Nwell isolation)

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Research Issues – RFICs & SystemsNoise – low frequency and SNRMatching of input stages – fluctuation/dispersion effects

Technology - tox, Nsub, xj VT, gm, gDS, fT, fMAX…Design - LG, WG RG, gm, gDS, fT, fMAX…

Low-voltage designVoltage distribution across elements between VDD and VSS

Modeling in subthreshold

Novel circuits requiredModeling of passives and improved passivesIsolation techniques between digital and analogDesign techniques – microwave and mm-wave

History of Electronics1904 Vacuum tube by Fleming1906 Solid state Diode by Pickard1907 Radio Circuits 1920 Super Heterodyne Receiver by Armstrong1925 Field Effect Device by Lilienfield1933 FM by Armstrong1940 Radar 1947 Silicon Transistor by Bardeen, Bratain and Shockley1950 Color Television 1952 Unipolar Filed Effect Transistor by Shockley

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History of Electronics (Continued)

1956 Silicon Controlled Rectifier by Bell Laboratories1958 Commercial Thyristor by General Electric 1958 Integrated Circuits by Texas and Fairchild1968 Op-Amp by Fairchild Semiconductor1971 4004 Microprocessor by Intel1972 8 bit Microprocessor by Intel1995 Gigabit Memory Chip by Intel

Transistor RevolutionTransistor –Bardeen (Bell Labs) in 1947Bipolar transistor – Schockley in 1949First bipolar digital logic gate – Harris in 1956First monolithic IC – Jack Kilby in 1959First commercial IC logic gates –Fairchild 1960TTL – 1962 into the 1990’sECL – 1974 into the 1980’s

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MOSFET TechnologyMOSFET transistor - Lilienfeld (Canada) in 1925 and Heil (England) in 1935CMOS – 1960’s, but plagued with manufacturing problemsPMOS in 1960’s (calculators)NMOS in 1970’s (4004, 8080) – for speedCMOS in 1980’s – preferred MOSFET technology because of power benefitsBiCMOS, Gallium-Arsenide, Silicon-GermaniumSOI, Copper-Low K, …

Applications of CMOS

ComputerTelecommunicationControlMilitaryIndustrialEtc.

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Introduction to Transistors

Classification of Transistors

NPN PNP

Bipolar Junction Transistor(BJT)

Junction FET(JFET)

Depletion MOSFET(D-MOSFET)

Enhancement MOSFET(E-MOSFET)

MOS

Metal Oxide Semiconductor FET(MOSFET)

Field Effect Transistor(FET)

Insulated Gate Bipolar Transistor(IGBT)

Transistors

Intel 4004 Microprocessor

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Intel Pentium (IV) Microprocessor

Moore’s Law in Microprocessors

40048008

80808085 8086

286386

486Pentium® proc

P6

0.001

0.01

0.1

1

10

100

1000

1970 1980 1990 2000 2010Year

Tran

sist

ors

(MT)

2X growth in 1.96 years!

Transistors on lead microprocessors double every 2 yearsTransistors on lead microprocessors double every 2 years

Courtesy, Intel

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64

256

1,000

4,000

16,000

64,000

256,000

1,000,000

4,000,000

16,000,000

64,000,000

10

100

1000

10000

100000

1000000

10000000

100000000

1980 1983 1986 1989 1992 1995 1998 2001 2004 2007 2010

Year

Kbi

t cap

acity

/chi

p

Evolution in DRAM Chip Capacity

1.6-2.4 μm

1.0-1.2 μm

0.7-0.8 μm

0.5-0.6 μm

0.35-0.4 μm

0.18-0.25 μm

0.13 μm

0.1 μm

0.07 μm

human memoryhuman DNA

encyclopedia2 hrs CD audio30 sec HDTV

book

page

4X growth every 3 years!

Die Size Growth

40048008

80808085

8086286

386486 Pentium ® proc

P6

1

10

100

1970 1980 1990 2000 2010Year

Die

siz

e (m

m)

~7% growth per year~2X growth in 10 years

Die size grows by 14% to satisfy Moore’s LawDie size grows by 14% to satisfy Moore’s Law

Courtesy, Intel

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Clock FrequencyLead microprocessors frequency doubles every 2 yearsLead microprocessors frequency doubles every 2 years

P6Pentium ® proc

48638628680868085

8080800840040.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Freq

uenc

y (M

hz)

2X every 2 years

Courtesy, Intel

Technology Directions: SIA Roadmap

2.42.22.02.42.01.4Battery power (W)18317417016013090High-perf power (W)0.60.60.91.21.51.8Power supply (V)109-1098-97-86-7Wiring levels

2200180014001100800600Clock rate (MHz)14721408128010241024768Signal pins/chip354308269235170-214170Chip size (mm2)7012841154714-267Mtrans/cm2

355070100130180Feature size (nm)

201420112008200520021999Year

For Cost-Performance MPU (L1 on-chip SRAM cache; 32KB/1999 doubling every two years)

http://www.itrs.net/ntrs/publntrs.nsf

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Design Abstraction Levels

SYSTEM

GATE

CIRCUIT

VoutVin

CIRCUIT

VoutVin

MODULE

+

DEVICE

n+S D

n+

G

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24


What is the next wave?

Source: Richard Newton

25


Design flow

Concluding RemarksNovel circuits will be needed - deep submicron

Higher frequencies, reduced power, improved linearityLower noise, matching issues, …

High quality passives at very high frequenciesModeling, design, technology

Packaging technology and modeling - integrationSeveral promising new applications are arising

Imaging systems and transceiver circuits discussedIntelligent transceiver architectures e.g. radio with a “brain”RFICs in new technologies – RFID tags in polymers/organics

Several research issues identifiedFuture applications of RFICs - limited by our imagination and economics--- Nanotechnology

Documents

223410 Linear Integrated Circuit Analysis and Designte.kmutnb.ac.th/~msn/223410intro.pdf · zForward substrate biasing (V BS>0) reduces the threshold voltage V T Îlow voltage