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CmOs Solutions for Mid-board Integrated transceivers with breakthrough Connectivity & ultra low cost (COSMICC)
CONSORTIUM
In order to reach these ambitious objectives the consortium consists of 11 partners from industry and academia in 5 European countries :
The consortium has a balanced partnership including :
Research Center : CEA LETI
Industry : ST-MICROELECTRONICS (FRANCE AND ITALY), VARIO-OPTICS, SEAGATE, FINISAR
Academic & Institutional : UNIVERSITÉ PARIS SUD, UNIVERSITA DI PAVIA, UNIVERSITY OF SOUTHAMPTON OPTICAL RESEARCH CENTER, UNIVERSITY OF SAINT ANDREWS
Other : AYMING
ACKNOWLEDGEMENT CONTACT
The work leading to this invention has received funding from the European Union Horizon H2020 Programme (H2020-ICT27-2015) under grant agreement n°688516.
The project has started on December 1st, 2015 and will end on November 30th, 2018.
Photonics Public Private Partnership 21.
Project Coordinator :
CEA – Dr Ségolène [email protected]+33 4 38 78 03 66
CEA – Dr Sylvie [email protected]+33 4 38 78 04 51
Quality Manager and Management support :
AYMING – Ms Julie [email protected]
AYMING – Mr Etienne [email protected]
www.H2020-COSMICC.eu
A European Project supported through the H2020 Framework Programme
OBJECTIVES
The COSMICC consortium gathers key industrial and research partners with world-leading positions in the fields of Silicon Photonics, CMOS electronics, Packaging, Optical transceivers and Data center player around a strong vision: mass commercialization of Silicon photonics based transceivers is possible starting in 2019 by enhancing the existing photonic integration platform of ST-Microelectronics.
COSMICC will develop optical transceivers that will be packaged on-board (Figure1). Combining CMOS electronics and Si-photonics with innovative-high-throughput fiber-attachment techniques, the developed solutions are scalable to meet the future data-transmission requirements in data-centers and Super computing systems. With performances improved by an order of magnitude as compared with current VCSELs transceivers, COSMICC developed technology will answer tremendous market needs with a target cost per bit that the traditional WDM transceivers cannot meet. The early setting up of a new value chain will enable exploitation of the developed technologies.
Electronic Integrated Circuits (EIC)
DESIGN FOUNDRIES DEVICES - MODULES SYSTEMS END-USERS
Photonics Electronics3D Integration
Polymer waveguide Subcontracting
Assembly
Storage Systems
Data centersHigh PerformancesComputing systemsSilicon Photonics
Integrated circuits
OR OSAT
FLEX SUBSRATEMT-FERRULE
FLEX SUBSRATE MT-FERRULE
ROADMAPCONCEPT & APPROACH
In a first high reward step-modification of the fabrication platform, COSMICC consortium will achieve mid-board optical transceivers in the [2Tbit/s -2pJ/bit- 0.2€ per Gbit/s]-class with ~200Gbit/s per fiber: the introduction of one process brick (SiN layer) in the photonic process will enable low-cost packaging techniques (up to 2x12 fiber channels) and practical coarse WDM implementation (4 wavelengths with no temperature-control requirements).
The built demonstrators will be tested in lab and field environments. In compliancy with the enhanced-fabrication platform, lasers will be developed by heterogeneous integration of III-V material, targeting improved temperature behaviour, and doubled-bit-rate payback.
A second step-modification of the fabrication platform will consist in evaluating a disruptive process that enables SiGe layers with tunable Si-composition for achieving micrometer-scale devices.
FIGURE 1: Schematics of COSMICC on-board optical transceiver at 2.4 Tb/s (50 Gbps/wavelength, 4 CWDM wavelengths per fiber, 12 fibers for Tx, 12 fibers for Rx).
Push performances with current fab capabilities
STEP 1 : SIN-ENHANCED SI-PHOTONIC FABRICATION LINE
Time to market
Market penetration of COSMICCSi-Photonic-based transceivers>100 Gb/s, <2km transceivers
Standalone modules4 �bers
PCB-integration12 �bers
Laser integration
2017 2018 2019 2020 2021
DEMO 1
DEMO 2PIC V2
DEMO 2Adv PIC A
DEMO 2Adv PIC B
TODAY25 Gb/s per �ber
100 Gb/s total20€/Gb/s35pJ/bit
3mm-MOD
2 WDM x 50 Gb/s per �ber400 Gb/s total
2,5€/Gb/s8pJ/bit + CDR
3mm-MOD
4 WDM x 50Gb/s per �ber800 Gb/s total
1,5€/Gb/s3pJ/bit + CDR(500µm-MOD)
4 WDM x 50Gb/s per �ber2,4 Tb/s total
0,2€/Gb/s<3pJ/bit / NO CDR
(500µm-MOD)
8 WDM x 50Gb/s per �ber4,8 Tb/s total
0,1$/Gb/s2pJ/bit / NO CDR
(500µm-MOD)
DEMO 1
Current process available at STCr2, TRL7 at T0
• Surface �ber coupler in Si: 30nm coupling BW, 4 dB loss• Modulator : MZM PN junction (3mm long)• Mux/Dmux in Si (70 pm/°C -> needs temperature control)• External laser -> needs assembly with a lens + isolator
Photonicsfabrication
processcharacteristics
Photonic devices
Electronicfabrication
process anddesign
Packaging
TransceiverPerformance
BI55 (BiCMOS) from ST-Cr2Distributed drivers
Demo 100G/�ber Tx and Rx2lx 50G = 100G/�ber8pJ/bit + CDR1 �ber set (total = 100Gb/s Tx and Rx)EIC = 10mm², PIC = 50mm²
Scalability of demo (4 �ber sets)400G Tx and Rx
3D photonic/electronic integrationSurface coupling
DEMO 2
WITH PIC V1 WITH PIC V2 WITH ADV - PIC_A WITH ADV - PIC_B
Step 1- process enhancement : Addition of an SiN Layer in the MEOL (TRL2 at T0, TRL4/5 at
COSMICC completion)
• In-plane coupler (Si/SiN/polymer): 80nm coupling BW, <1 dB loss• Modulator: 500µm long (slow wave in Si, or capacitive modulator)• Mux/Dmux in SiN (7pm/°C) -> no temperature control• External laser source
BI55 (BiCMOS) from ST-Cr2Lumped driver
3D photonic/electronic integrationin-plane coupling
Demo 200G/�ber Tx and Rx4lx 50G = 200G/�ber3pJ/bit + CDR1 �ber set (total = 200Gb/s Tx and Rx)EIC = 20mm², PIC = 70mm²
Scalability of demo (4 �ber sets)800 G Tx and Rx
Step 1- process enhancement : Addition of an SiN Layer in the MEOL (TRL2 at T0, TRL4/5 at
COSMICC completion)
• In-plane coupler (Si/SiN/polymer): 80nm coupling BW, <1 dB loss• Modulator: 500µm long (slow wave in Si, or capacitive modulator)• Mux/Dmux in SiN (7pm/°C) -> no temperature control• External laser source
BI55 (BiCMOS) from ST-Cr2Lumped driver
3D photonic/electronic integrationIn plane coupling - Through polymer
Demo 200G/�ber Tx and Rx4lx 50G = 200G/�ber< 3pJ/bit 1 tyle for 1 �ber set (total = 200Gb/s Tx and Rx)Tyle: EIC = 20mm², PIC = 80mm²
Scalability of demo (12 tyles)2400 G Tx and Rx
Demo 200G/�ber Tx and Rx8lx 50G = 400G/�ber3pJ/bit + CDR1 tyle for 1 �ber set (total = 200Gb/s Tx and Rx)EIC = 20mm², PIC = 70mm²
Scalability of demo (12 tyles)2400 G Tx and Rx
Wire bonding, possibly 3D photonic/electronic integration
In plane coupling - Through polymer
BI55 (BiCMOS) from ST-Cr2Lumped driver
• In-plane coupler (Si/SiN/polymer): 80nm coupling BW, <1 dB loss• Modulator: 500µm long (slow wave in Si, or capacitive modulator)• Mux/Dmux in SiN (7pm/°C) -> no temperature control• Integrated laser source with reduced wavelength shift against temperature
III-V integration with SiN Layer in the FEOL (TRL2 at T0, TRL3/4 at
COSMICC completion)
