AN255610GEPON SY88009L and XGS-PON/NG-PON2 SY88029L

OLT Burst Mode Limiting Amplifiers

Author: Abdennour MezerregMicrochip Technology Inc.

INTRODUCTION

This document explains how to use the SY88009L and SY88029L burst mode limiting amplifiers in their respective appli-cations 10GEPON and XGS-PON.

The SY88009L is a dual rate 1.25G/10G dual output PECL(1.25G)/CML(10G) burst mode limiting post amplifier designed for use in 10GEPON OLT receivers, while the SY88029L is a dual rate (2.5G/10G or 1.25G/10G) single CML output burst mode limiting post amplifier designed for use in XGPON/XGS-PON, NG-PON2, and 10GEPON OLT receiv-ers.

The SY88009L (resp. SY88029L) contains a high-sensitivity input stage followed by 1.25G/10G (resp. 1.25G/2.5G/10G) auto-rate detector/noise discriminator block with user-programmable wide-range LOS/SD assert/de-assert threshold levels, which enables optimized system reach. A logic level control pin is provided to enable user selection of a TTL LOS or SD status indication signal. The LOS/SD output can be fed back to the JAM input for output stability when there is no data present at the input. LOS/SDLVL sets the threshold for the input signal detection.

Both amplifiers offer a LOS/SD assert/de-assert time in the 75 ns to 150 ns range under AUTORESET mode while SY88029L offers <5 ns after RESET is applied which make the SY88029L meet largely the timing of the XGS-PON and NG-PON2 applications.

AUTO-RATE DETECTOR

The noise discriminator feature is intended for PON OLT applications with high-gain burst-mode TIAs with high respon-sivity APD receiver where noise can trigger a false LOS de-assert or SD assert while no input data is present. The noise discriminator will filter input data through a series of specialized circuits that will only trigger LOS/SD on the preamble of a valid PON data signal, 1.25 Gbps/10 Gbps for SY88009L and 1.25 Gbps/2.5 Gbps/10 Gbps for SY88029L. In the case of SY88009L, the noise discriminator/auto-rate detector will turn ON the appropriate output (PECL for 1.25G or CML for 10G) and turns off the other output.

RESET VS. AUTORESET OPERATION IN BURST MODE APPLICATIONS

AUTORESET and RESET have a dual function to de-assert SD (assert LOS) after the loss of a burst and initialize the noise discriminator (ND) to be ready for a new burst detection. SY88009L operates with AUTORESET mode ON always while for SY88029L the user can chose between AUTORESET or manual RESET. In AUTORESET mode, the SD de-asserts (LOS asserts) automatically within 150 ns (worst case under all combined worst conditions) after the last tran-sition of the input data burst. If the AUTORESET function is disabled (SY88029L only), SD must be de-asserted (LOS asserted) manually by applying a RESET pulse at RESET pin.

AC- OR DC-COUPLING AND BURST MODE RECEIVER CHALLENGES

The receiver should be able to support data signals with long strings of consecutive identical digits (CID) and power shift from strong bursts to weak bursts (and vice versa) to avoid the loss of data packets. These two situations will not be an issue if the receiver link from the TIA to the limiting amplifier is DC-coupled and doesn’t contain any coupling capacitors. Unfortunately, DC-coupling the limiting amplifier to the TIA requires the output of the TIA and the input of the LA to have compatible common mode voltages, and it is unlikely to find a TIA-LA on the market that satisfies that condition. There-fore, to have more choice in parts selection, the module designer will more likely use AC-coupling between the TIA and LA.

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AC-coupling the TIA to the LA comes with some issues the designer should address by using appropriate architecture and component values. The two issues that face the use of AC-coupling are the presence of long strings of consecutive identical digits (CID) and receiver threshold settlement time during large power shifts between strong and weak bursts (and vice versa).

CID

CID is defined as consecutive identical digits, may vary from one protocol to another, and can be either consecutive ‘1’ or consecutive ‘0’. It is up to the module designer to ensure that the module will correctly handle the number of CIDs for a particular application. Figure 1 shows the effects of a long string of CIDs with large and small coupling capacitors.

1

SS SS

PreambleSS SS

Small AC coupling cap

Large AC coupling cap

Large droop

Small droop

Data Payload

64 bits CID

FIGURE 1: Effect of CID.

A small value coupling capacitor will create a higher low-cut-off frequency (the cap and the termination creates a high-pass filter) that may cause errors with low frequency data, especially in the presence of long strings of CID due to droop-ing (see Figure 1). Additionally, this condition makes the middle of the data eye wander with low frequency data com-ponents. Therefore, the value of the cap should be large enough to set the low frequency cut-off well below the lowest frequency component (created by CID) and minimize DC level wander with low frequency components.

RECEIVER THRESHOLD SETTLING TIME IN BURST MODE APPLICATIONS

Figure 2 shows the effect of large and small coupling caps on the receiver settling time during a strong burst-to-weak burst transition. When the data at the input of the receiver switches from a strong burst to a weak burst, the DC compo-nents of the data signal decays exponentially with time. If a large value is selected for the coupling cap, the data’s DC level may not settle to the baseline of the new burst within allowed deviation during the preamble time and will lead to errors in data detection. In other words, the time constant created by the coupling cap should be small enough to make the receiver threshold settlement transparent to strong burst-weak burst transitions.

SS

SS

ONU#1

ONU#2

Guard TimeSS

SS

Preamble

Small AC coupling capLarge AC coupling cap

e-t/

FIGURE 2: Effect of Coupling Cap on Receiver Settling Time.

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10GEPON OLT RECEIVER

SY88009L

In the case of 10GEPON OLT receivers, the guard time between bursts is >400 ns and a single coupling capacitor/input termination combination can work for both 1.25G and 10G bursts. The SY88009L with its internal 50Ω termination and a 1 nF to 10 nF coupling capacitor can be enough to provide good results for both 1.25G and 10G data bursts. As men-tioned above, the SY88009L LOS/SD response time with AUTORESET is within 75 ns to 150 ns, which largely meets the timing for the 10GEPON application. Figure 3 shows a possible configuration for the SY88009L.

VCC

10 nF

10 nF SY88009LLO

S/S

D_L

VL

PO

L_C

TRL

LOS

/SD

_SEL

PE_CTRL

LOS

/SD

PEL

VL

CP

A_C

TRL

CP

A

SW

_CTR

L1

SW

_CTR

L2

GND

DIN+

GND

ND_CTRL

DIN-

JAM

DN

C

RA

TE_S

EL

VCC

1G_DOUT-

VCC

10G_DOUT+

10G_DOUT-

1G_DOUT+

InputBu er

50

50

VREF

VCC

C8 C9

VCCTIA

200 200

0.01μF 0.1μF

0.01μF 0.1μF

FIGURE 3: 10GEPON Single-Chip OLT LA Solution with SY88009L.

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SY88029L

SY88029L can be programmed to be used in 10GEPON OLT receiver with a single CML output for both 10G and 1.25G data bursts. That mode of operation is selected by setting pin 19 (1G_SEL) to a high level to select 1.25G operation instead of 2.5G operation and installing 50Ω resistor between DIN and VREF as shown in Figure 4.

VCC

10 nF

10 nF SY88029L

LOS

/SD

_LVL

PO

L_C

TRL

LOS

/SD

_SEL

VREF

LOS

/SD

SW

_CTR

L1

AU

TOR

ESE

T

MA

NR

ES

ET

CP

A_C

TRL

CP

A

GND

DIN+

GND

ND_CTRL

DIN-JA

MR

C_C

TRL

1G_S

EL

VCC

SW_CTRL2

VCC

DOUT+

DOUT-

PE

InputBu er

2020

10 10

VREF

VCC

C8 C9

VCCC8 C9

TIA

50

50

0.01μF 0.1μF

0.01μF 0.1μF

FIGURE 4: 10GEPON Single-Chip OLT LA Solution with SY88029L.

XGS-PON/NG-PON2 OLT RECEIVER

For XGS-PON and NG-PON2 applications the target spec for the guard time between bursts is 25.6 ns to 51.2 ns and the use of one combination coupling capacitor/input termination won’t be enough to satisfy the receiver settling time, to avoid data packets loss, and high enough RC time constant that prevents data errors that can be caused by signal droop during long strings of CID.

CID AND RECEIVER THRESHOLD SETTLING TIME SOLUTION

To improve the receiver threshold settlement time, which requires a short time constant, and the CID problem, which requires a long time constant, the circuit can be designed with two low-frequency cut-off frequencies: one low enough to be used for CID and one high enough to improve the receiver’s settlement time between bursts. The SY88029L shown in Figure 5 and Figure 6 incorporates a switch at its input that allows the user to switch between short and long RC time constant.

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VCC

82 pF

82 pF SY88029L

RESETLO

S/S

D_L

VL

PO

L_C

TRL

LOS

/SD

_SEL

VREF

LOS

/SD

SW

_CTR

L1

AU

TOR

ESE

T

MA

NR

ES

ET

CP

A_C

TRL

CP

A

GND

DIN+

GND

ND_CTRL

DIN-

JAM

RC

_CTR

L

1G_S

EL

VCC

SW_CTRL2

VCC

DOUT+

DOUT-

PE

InputBu er

2020

10 10

VREF

VCC

C8 C9

VCCC8 C9

TIA

1010

0.01μF 0.1μF

0.01μF 0.1μF

FIGURE 5: Solution Based on Two Time Constants, RESET Applied to RC_CTRL.

VCC

82 pF

82 pF SY88029L

RESET

LOS

/SD

_LVL

PO

L_C

TRL

LOS

/SD

_SEL

VREF

LOS

/SD

SW

_CTR

L1

AU

TOR

ESE

T

MA

NR

ES

ET

CP

A_C

TRL

CP

A

GND

DIN+

GND

ND_CTRL

DIN-

JAM

RC

_CTR

L

1G_S

EL

VCC

SW_CTRL2

VCC

DOUT+

DOUT-

PE

InputBu er

2020

10 10

VREF

VCC

C8 C9

VCCC8 C9

TIA

1010

VCC

R<5

0.01μF 0.1μF

0.01μF 0.1μF

FIGURE 6: Solution Based on Two Time Constants, LOS Applied to RC_CTRL.

Please note that for the configuration used in Figure 6, LOS must be selected (LOS/SD_SEL pin High).

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The output of the TIA is coupled to the input of the LA with a small cap (82 pF). The termination at the input of the limiting amplifier is switched between a low value (10Ω) during guard time between the consecutive bursts and part of the pre-amble of the second burst, and then switched to a higher value (internal 20 kΩ in parallel with any resistor installed out-side between DIN± and VREF as shown in Figure 5 and Figure 6). The lower value allows for a fast threshold acquisition while the higher value allows for a smaller threshold droop during CID.

The selection between the two termination resistors, which determines the two low-frequency cut-offs, is done through RC_CTRL pin. When a high signal is applied to RC_CTRL pin, the switch will close and the terminations become 10Ω (which represents the switch ON series resistor). When it’s low, the switch opens and the termination becomes the inter-nal 20 kΩ in parallel with the resistor installed outside the part between DIN and VREF.

The RESET signal should start during the guard time and end either during the guard time or after a few bits of the sec-ond burst preamble, as shown in Figure 8 and Figure 11. This allows for a fast ONU#2 threshold’s acquisition (short time constant selected when RESET applied) and minimizes the threshold droop during CID when RESET is LOW (longer RC time constant selected). If RESET ends during the guard time, it will take longer to the receiver to settle to the base-line of the new bursts since the long RC time constant is selected when the second burst starts. If RESET ends during the second burst preamble, there is no signal detection during the overlap time between RESET and preamble.

A best solution to control RC_CTRL is to use LOS signal as shown in Figure 6. RESET is applied right after the end of the first burst and ends during the guard time to allow the detection to start from the first bit of the next burst. During the guard time, LOS is High, which selects the fast RC time constant (10Ω termination selected). This allows for a fast receiver settling to the new burst baseline. When the signal is detected, LOS switches to Low and the long RC time constant is then selected to optimize the receiver for long CID strings.

TEST PATTERN AND SENSITIVITY

If the LOS/SD pin is not connected to the JAM pin (meaning the squelch function is not used) and the noise discriminator is disabled, any pattern can be used to test the sensitivity because test signals flow through the RF path without any control. The sensitivity is determined only by the amplifier’s ability. If the squelch function is used (LOS/SD connected to JAM), then test results depend on the test pattern, the noise discriminator, and the LOS/SDLVL.

ND Disabled, Squelch Function Used

If the noise discriminator (ND) is disabled, the sensitivity test can be done with any pattern because, in this case, the test signal flows through the RF path without any signal validity test from the ND. The sensitivity is determined by the amplifier’s ability and the detection threshold is set by the DC voltage applied at the LOS/SDLVL pin or by the resistors installed from LOS/SDLVL pin to VCC, whichever is used. For SY88009L, RATE_SEL may be used to select between 1.25 Gbps and 10 Gbps data rates.

ND enabled, Squelch Function Used or Not Used

If the noise discriminator is enabled, the test pattern should start with a sequence of “1010…” (preamble) to allow the ND block detect/validate the data at the beginning and avoid additional delays. The sensitivity is still set by LOS/SD LVL. If a PRBS pattern is used without any preamble, the ND will take an unknown time to detect/validate data depending on where it can detect a “1010…” sequence in the PRBS data signal. In this case, the sensitivity test is affected by the long delay the ND takes to detect the data and releases the LOS/SD signal to assert/de-assert.

EFFECT OF RESET SIGNAL ON SD/LOS TIMING (SY88029L ONLY)

Noise Discriminator (ND) Disabled

If the noise discriminator (ND) is disabled and the RESET signal is applied during the guard time between the two ONUs data and ends before the preamble of the ONU#2, as shown in Figure 7, there will be no impact on LOS/SD assert or de-assert time. However, the threshold acquisition time will not be fast because the DC level will first settle to VREF and then to the ONU#2 data threshold during the preamble.

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SS

ONU#2

Guard TimePreamble

ONU#1

RESET

SD

tSDA

FIGURE 7: RESET Ends before Preamble with ND Disabled.

To improve the threshold acquisition and receiver settlement time between two bursts, the RESET can be applied during the guard time and ends during the preamble of ONU#2, as shown in Figure 8. Keeping the RESET during a few bits of the preamble allows for a fast acquisition of the ONU#2 data threshold using the shorter time constant.

SS

ONU#2

Guard TimePreamble

ONU#1

RESET

SD

tSDA

FIGURE 8: RESET Ends During Preamble with ND Disabled.

This improvement comes at the price of a delay in the SD assert (LOS de-assert) because the data is not detected during the bits of the preamble overlapped by the RESET signal. To minimize that delay, the overlap between RESET and the preamble should be kept to the minimum that eliminates or minimizes the droop in the data DC component.

If the RESET is applied after the first burst ends and another RESET is applied during the preamble or DATA, as shown in Figure 9, SD (or LOS) will generate a glitch before stabilizing. SD asserts high during the first bits of the preamble, then de-asserts low following the RESET to assert high again during the preamble or during the data bits following the end of RESET.

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SS

ONU#2

Guard TimePreamble

ONU#1

tSDA tSDA

RESET

SD

FIGURE 9: RESET Applied During Preamble or Data with ND Disabled.

Noise Discriminator Enabled

If the noise discriminator is enabled and the RESET is applied during the guard time and ends before the preamble of ONU#2, as shown in Figure 10, the SD assert time will be the combination of the noise discriminator data detection time and the delay between data detection and SD asserting high.

SS

ONU#2

Guard TimePreamble

ONU#1

RESET

SDtND tSD

tSDA

FIGURE 10: RESET Ends Before Preamble with ND Enabled.

If the noise discriminator is enabled, and the RESET is applied during the guard time and ends during the preamble of ONU#2 (Figure 11), the SD assert time will be the combination of the delay from the start of the preamble to the first bit “1” following the end of RESET, the noise discriminator data detection time, and the delay between data detection and SD assert.

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Be aware that if the RESET is applied during guard time and extends into the preamble, the SD assert delay will vary depending on where the end of the RESET signal occurs. In other words, the SD assert time won’t be repetitive. There-fore, this way of applying RESET is not recommended if the shortest and stable SD assert time is required.

SS

ONU#2

Guard TimePreamble

ONU#1

RESET

SDtND tSD

tSDA

FIGURE 11: RESET Ends during Preamble and ND Enabled.

If the RESET is applied after the first burst ends and another RESET is applied during the preamble or DATA, as shown in Figure 12, and ND is enabled, SD (or LOS) will generate a glitch before stabilizing. SD asserts high during the first bits of the preamble, then de-asserts low with RESET to assert high again during the preamble. If RESET ends during data, SD asserts high only if the ND detects the sequence of “1010…” in the data bits following the end of RESET.

SS

ONU#2

Guard TimePreamble

ONU#1

RESET

SDtND tSD tND tSD

FIGURE 12: RESET Applied during Preamble or Data with ND Enabled.

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NOTES:

DS00002556A-page 10 2017 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

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Germany - MunichTel: 49-89-627-144-0 Fax: 49-89-627-144-44

Germany - RosenheimTel: 49-8031-354-560

Israel - Ra’anana Tel: 972-9-744-7705

Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781

Italy - PadovaTel: 39-049-7625286

Netherlands - DrunenTel: 31-416-690399 Fax: 31-416-690340

Norway - TrondheimTel: 47-7289-7561

Poland - WarsawTel: 48-22-3325737

Romania - BucharestTel: 40-21-407-87-50

Spain - MadridTel: 34-91-708-08-90Fax: 34-91-708-08-91

Sweden - GothenbergTel: 46-31-704-60-40

Sweden - StockholmTel: 46-8-5090-4654

UK - WokinghamTel: 44-118-921-5800Fax: 44-118-921-5820

Worldwide Sales and Service

11/07/16