22
© Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

© Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

Embed Size (px)

Citation preview

Page 1: © Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

© Banff and Buchan College 2007

DH2T 34 Computer Architecture 1

LO2 Lesson One

Memory

Page 2: © Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

Random Access Memory. Whenever a program is about to be run, the binary code is first loaded into the RAM. The RAM chips are split into a number of cells, or

“addresses”, each with a unique number. These cells are made of transistors and capacitors.

RAM can be both read from and written to.The common name for RAM is main memory.

Page 3: © Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

The RAM capacitors can only hold their values for a very small period of time before they discharge.

To retain the values, the capacitors must be constantly refreshed with electrical current.

We therefore refer to this type of RAM as dynamic memory.

DRAM is cheap to produce and has a very fast access time – typically 60 – 70 nanoseconds.

RAM is volatile – it loses all the stored information if the power is cut off.

Page 4: © Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

You will sometimes see DRAM marketed as –

Synchronous RAM (SDRAM) – this is RAM synchronised to the System Bus – it can run at

100MHz or more.

Rambus RAM (RDRAM) – this is a type of RAM specially developed for the Pentium 4. It is also

very fast but very specialised.

Double Data Rate RAM (DDRAM) – this RAM effectively doubles transfer rates by using both phases of the clock cycle. Also known as DDR

SDRAM.

Page 5: © Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

Read Only Memory (ROM)The role of the ROM chip is to start the

computer, perform the Power On Self Test (POST) and load the operating system.

For this reason it is sometimes called the Basic Input Output System (BIOS) chip.

Page 6: © Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

Unlike RAM, the ROM chip is non-volatile; it retains all it’s programming even when the

power is switched off.

Page 7: © Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

ROM chips have their programs burnt onto them at the point of manufacture. They cannot be

subsequently reprogrammed.

They are comparatively expensive to produce and their access times are very slow compared

to RAM.

Page 8: © Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

Unlike a ROM, however, a PROM is

manufactured blank. It has its program burned onto it at a later point using a PROM burner.

Another type of ROM, often found mounted on peripherals, is

Programmable Read Only Memory (PROM).

Page 9: © Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

The PROM can only be programmed once – it cannot then be wiped clean and re-used.

Like a ROM, it’s access time is slow.

The setup costs to write the program for a PROM are high, but once the algorithm has been designed, the costs to produce burned

PROMS are extremely cheap. They are burned in huge lots and used for many

different types of firmware.

Page 10: © Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

There are also types of PROM available which can be reprogrammed under

certain conditions.

These are Eraseable Programmable Read Only

Memory (EPROM) and Electrically Erasable Read Only Memory (EEPROM).

Page 11: © Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

EPROMS are wiped by using UV light, then reprogrammed in a PROM burner.

EEPROMS are wiped using electrical current. They can be reprogrammed

using special software or a PROM burner.

Page 12: © Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

EPROMS and EEPROMS are often used in firmware which will be subject to later

upgrading – for example on graphics cards. They are also widely used for Quality

Control purposes in motherboard manufacturing.

Like ROM, these are also non-volatile and retain their contents when switched off.

They are expensive to produce and their access times are slow.

Page 13: © Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

Another form of read/write memory is Static Random Access Memory (SRAM).

Do not confuse this with SDRAM!

Modern computers ship with SRAM installed. Very early computers had little or

no SRAM.

Page 14: © Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

Unlike DRAM, SRAM is composed of bi-polar electric cells. These behave like

very small batteries and do not need to be constantly refreshed with current.

SRAM, however, is still volatile – if the power is cut all the contents are lost.

Page 15: © Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

SRAM is much faster than DRAM (about 10 ns) and more stable, but requires more power and is a lot more expensive to

produce.

For this reason it is only ever used as a memory cache.

Page 16: © Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

The Cache is memory which sits between the main RAM and the CPU. It works on the Principle

of Locality of Reference – data frequently accessed is kept close by, to save time.

Page 17: © Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

Cache Memory can be located in the Processor itself, on the Motherboard, or

both.

Pentium 4s usually ship with 256kB or 512kB of on-chip (Level 1) cache.

Elite Group motherboards usually ship with 128kB on-board (Level 2) cache.

Page 18: © Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

Two Different Types of Cache

Write-through. Every write operation to the cache is accompanied by a write of the same data to main memory.

Write-back. In this scheme, the central processor updates the cache during a write, but actual updating of the memory is deferred until the line that has been changed is discarded from the cache. At that point, the changed data are written back to main memory.

Page 19: © Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

The Cache is connected to the CPU by a special data bus called the Front Side Bus. This is an

extremely fast data pipeline which often runs at half the speed of the processor – a 1 GHz

processor may have a FSB running at 500 MHz or even more.

Front-side bus from CPU to

L2 cache

Page 20: © Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

© Banff and Buchan College 2007

Data Throughput

0

1000

2000

3000

4000

5000

6000

72 p

in S

IMM

pc 6

6

pc 1

00

pc 1

33

pc 8

00

pc 1

600

pc 2

100

pc 2

700

pc 4

200

RIM

M 3

200

RIM

M 4

200

RIM

M 4

800

Memory Devices

Th

rou

gh

pu

t (M

B/s

)

Page 21: © Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

© Banff and Buchan College 2007

Page 22: © Banff and Buchan College 2007 DH2T 34 Computer Architecture 1 LO2 Lesson One Memory

Summary

Dynamic RAM is another name for main memory. It is capacitor-based and volatile. It relatively cheap to produce.

Static RAM is used as the cache. It is made from bi-polar electric cells and is comparatively expensive. It is also

volatile.

Read-Only Memory (ROM) is used as the BIOS. It cannot be reprogrammed and is expensive to produce. It is

programmed at the point of manufacture.

A PROM is manufactured blank and later programmed with a PROM burner.

EPROMs and EEPROMs are types of ROM that can be reprogrammed under certain conditions. They are expensive

to produce.