fpga tutorial 2009 - physics.purdue.edu

Illustrating the FPGA design process using Quartus II design software and the Cyclone II

FPGA Starter Board.

Physics 536 Spring 2009

Digital logic:Equivalent to a large number of discrete logic elementsNOT a microprocessor (although microprocessors can be implemented in an FPGA design)

High density:All the logic is inside a single chipNo need for interconnecting traces on PCB between logic circuits

Reprogrammable:Designs can be changed after the hardware has been manufacturedHigh-level design software optimizes the usage of limited resources

Both companies produce competitive products neither is endorsed. Other companies exist...We use Altera tools to demonstrate the design process.Xilinx has a similar set of tools.Conceptually, the design process is the same.

AlteraEP2C20F484C7N

$56.30 from Digi-Key

Configuration device stores the design that is automatically downloaded when power is applied.

Implement a 4-input XOR function:Output will be high only when exactly one input is high.Use KEY[0..3] as inputs.Show output on green LED.

Boolean algebra:

We could simplify this, but choose not to.

Design entry:Schematic entryHigh level language

Synthesis:Translating design into logic elements

Simulation:Validate design logic

Fitting:Implementing logic using FPGA resources

Double click here

Altera software is installed under C:\Altera\...

Please be patient...

This should be correct...

File New Project Wizard...What is the working directory for this project?

H:\Physics536

What is the name of this project?FirstExample

What is the name of the top-level entity...?FirstExample (default)

Then click Next > ... Click Yes to create the directory.No need to add design files, so click Next > .

Select the device:Family: Cyclone IIDevice: EP2C20F484C7

Then click Finish .

If you can t get something simple to work, don t expect to be able to do anything complicated...A much simpler design:

Input KEY0Output to green LEDG0

KEY[0] LEDG[0]

Input pin Output pinBuffer

File New Block Diagram/Schematic File

Add components

Add wires

Click on navigate to .../primitives/pin/inputClick OK, click to place the pin.

Do the same for the output pin.

Buffers can be used to drive special signals in the FPGA. In this case we don t need anything special so we can select

.../primitives/buffer/wire

Click the Wire tool ( ) and connect the pins to the buffer.

Double-click on the text associated with the pins

Change input pin name to KEY[0] and output pin name to LEDG[0] .

File Save ProjectProcessing Start CompilationSuccess? If not, fix the problem; try again.Look at resource usage:

But wait... how does it know which pins are physically wired to KEY[0] and LEDG[0]?

Total logic elements: 0/18,752 (0%)

Total pins: 2/315 (<1%)Not too surprising...

Pins can be assigned individually:Assignments Pins

Or imported from a file:Assignments Import Assignments

Don t forget to re-compile the design.

C:\Altera\Kits\CycloneII_Starter_Kit-v1.0.0/...

.../Examples/CII_Starter_demonstrations/design_files/CII_Starter_pin_assignments.csv

Plug in and turn on the DC powerPlug in the USB cable.Tools Programmer Start

This file contains the configuration data to be downloaded into the FPGA.

Sort of...Pins are pulled high via 10k resistors.

Low-pass filter to prevent the switches from bouncing .

Invert the KEY[0..3] inputs before assigning them to D0, D1, D2, D3.Use .../primitives/logic/not for inverterImplement the logic:

Use 4-input AND and 4-input OR gates:.../primitives/logic/and4.../primitives/logic/or4

Can you spot the mistake? The compiler certainly can!

We need to specify all possible inputs.File New... Other Files Waveform Vector File

Right-click here.

Right-click under Name Insert Insert Node or Bus...

Left-click on the KEY signal.Left-click on the , then OK

File Save...H:\Physics536\FirstExample\Waveform1.wvf

Processing Simulator ToolSimulation input: H:\Physics536\FirstExample\Waveform1.wvf

Click Start , then Open to examine the output.

Does this look right?

We should expect only 1110, 1101, 1011 and 0111 to give and output of 1...Check the timing report...

Longest tpd (propagation delay) from source pin KEY[1] to destination pin LEDG[0] is 10.24 ns.

Increase period of each input vector from 10ns to 50 ns...

Now this looks like what one would expect.Try downloading the FPGA with this configuration and try it out.

This document was created with Win2PDF available at http://www.daneprairie.com.The unregistered version of Win2PDF is for evaluation or non-commercial use only.

fpga tutorial 2009 - physics.purdue.edu

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