POLITECNICO DI MILANO

Reconfigurable Computing Reconfigurable Computing

Italian MeetingItalian Meeting19 December 2008

Room S01, Politecnico di Milano - Milan (Italy)

With the technical support of the Italian Chapters of:

IEEE Computational

Intelligence Society

Sponsored by:

The Programmable Solutions CompanyRoma

Advanced DSP Group of Atmel Corporation

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AgendaAgenda

09.30 – 9.45 WelcomeD. Sciuto (Politecnico di Milano)

09.45 - 11.30 Session 1: TrendsSession chair: V. Rana (Politecnico di Milano)

11.30 – 11.45 Coffee Break

11.45 – 13.15 Session 2: The hArtes European projectSession chair: V. Rana (Politecnico di Milano)

13.15 – 14.15 Lunch

14.15 – 15.30 Session 3: Applicative scenariosSession chair: F. Cancarè (Politecnico di Milano)

15.30 – 15.45 Coffee Break

15.45 – 17.30 Session 4: The High Level Reconfiguration project descriptionSession chair: F. Redaelli (Politecnico di Milano)

17.30 - 17.45 Concluding session

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Session 1: TrendsSession 1: Trends

Altera FPGA strategy for a reconfigurable approach in industry application

Speaker: A. Montanaro (ALTERA)Slide

A Multi-Core Signal Processor for Heterogeneous Reconfigurable Computing

Speaker: F. Campi (STMicroelectronics)Slide

Janus: FPGA Based System for Scientific ComputingSpeaker: F. Mantovani (Università di Ferrara)Slide

Future ChallengeSpeaker: M Corvo (Mindway )Slide

4

Coffee Break (15Coffee Break (15’’))

Next...

Session 2: The hArtes European project

Session chair: V. Rana (Politecnico di Milano)

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Session 2: The Session 2: The hArteshArtes European projectEuropean project

B2B with minimum TRIMM time. Un obiettivoambizioso, ma realizzabile

Speaker: R. Nutricato (Atmel Roma)

Slide

PandA: a framework for task partitioning of reconfigurable MPSoCs architectures

Speaker: F. Ferrandi (Politecnico di Milano)

Slide

The hardware application platform of the hArtesproject

Speaker: G. Marchiori (Università di Ferrara)

Slide

6

Lunch (60Lunch (60’’))

Next

14.15 – 15.30 Session 3: Applicative scenarios

Session chair: F. Cancarè (Politecnico di Milano)

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Session 3: Applicative scenariosSession 3: Applicative scenarios

Evolvable Hardware: past, present and future

Speaker: F. Cancarè (Politecnico di Milano)

Slide

Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing

Speaker: M. Lanuzza (Università della Calabria)

Slide

Coordinated Management of Hardware and Software Self-adaptivity

Speaker: A. V. Taddeo (ALaRI)

Slide

8

Coffee Break (15Coffee Break (15’’))

Next

Session 4: The High Level Reconfiguration project description

Session chair: F. Redaelli (Politecnico di Milano)

Concluding session

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Session 4: The High Level Session 4: The High Level Reconfiguration project descriptionReconfiguration project description

HLR overviewSpeaker: F. Redaelli (Politecnico di Milano) Slide

Core Identification for Reconfigurable Systems driven by Specification Self-Similarity

Speakers: M. Redaelli (Politecnico di Milano) and R. Cordone (Università degli Studi di Milano)Slide

Task Scheduling Techniques on Dynamically Reconfigurable SystemsSpeakers: R. Cordone (Università degli Studi di Milano) and F. Redaelli (Politecnico di Milano)Slide

Runtime core relocation management for self dynamically reconfigurable architectures

Speakers: M. Morandi (Politecnico di Milano) and M. Novati (Politecnico di Milano) Slide

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See you in 2009!See you in 2009!

Merry Christmas and Merry Christmas and

a happy and successful 2009!a happy and successful 2009!