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© 2008 Altera Corporation—Public
Altera FPGA strategy for a reconfigurable approach in industry application
Reconfigurable Computing Italian Meeting19 December 2008
Achille Montanaro
Altera Account Manager
© 2008 Altera Corporation—Public
2
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
This Decade: Programmable SolutionsThis Decade: Programmable Solutions
70’s 80’s 90’s 00’s
75
100
250
Bil
lio
ns
($
)
125
200
225
150
175
50
25
300
275
Texas Instruments
MotorolaSemiconductor
Intel
LSI Logic
Mentor Graphics®
Synopsys
Sun Microsystems
Broadcom
PMC-Sierra
TSMC
Multi-core
CPUs
DSPs
Logic designTTL integration
ASICmethodology
Fablesscompanies
SOCs, FPGAsmassively
parallel arrays
3
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
Definition “reconfigurable HW in industry applications”
Definition “reconfigurable HW in industry applications”
What is reconfigurable HW architecture in real
industry/telecom applications?
“it is an architecture that doesn’t require on the fly
Timing Analysis”
Why?− Because most of product qualification are extensively done in
Temperature Room Cycle and don’t let HW architecture changes
4
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
Fine-grainedarrays
FPGAsDSPsCPUs
Single cores
Programmable Solutions: 1985-2002Programmable Solutions: 1985-2002
5
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
Fine-grainedmassively
parallelarrayswith
embeddedhard IP blocks
FPGAsDSPsCPUs
Single cores Coarse-grainedmassively
parallelprocessor
arrays
Multi-coresCoarse-grainedCPUs and DSPs
Multi-cores Arrays
Programmable Solutions: 2002-20XXProgrammable Solutions: 2002-20XX
© 2008 Altera Corporation—Public
Future trends
7
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
Single-CPU Technology LimitationsSingle-CPU Technology Limitations
1970 1975 1980 1985 1990 1995 2000 2005 2010
Power (W)
1K
10 K
100 K
1 million
10 million
100 million
1 billion
10 billion
Transistors
CPU Clock (MHz)
Transistor Count
8
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
Parallel Speed-up: A Realistic ViewParallel Speed-up: A Realistic View
1 2 4 8 16 32 64 128 256 512 1024
Number of Processors
1
1024
Speed-up
Tasks with no data dependency
Tasks with high data dependency
9
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
Future Architecture—Micro 2015Future Architecture—Micro 2015
A Glimpse of Evolving Processor ArchitectureHow All This Might Come Together in a Hypothetical Intel Future Architecture Is What We Call “Micro 2015”. This Hypothetical Micro 2015 Processor’s Features Include:
Reliable and reconfigurable circuit blocks with a built-in
management infrastructure.
Parallelism at all levels that will be handled through an
abundant number of software and hardware threads. Chip-
Level Multi-processing (CMP) will provide true parallelism with
multiple low-power IA cores in a reconfigurable architecture
with a built-in microkernel.
Special-purpose, low-power hardware engines for fixed
functions including, but not limited to, real-time signal
processing and graphics.
High-speed interconnects linking cores within groups and among
groups, as well as special-purpose hardware and memory. The
memory interconnect bandwidth will match the performance
requirements of the processor and be in the multiple gigabytes per
second range.
Built-in virtualization and trust mechanisms providing layers of
abstraction to the applications and the OS to meet security,
reliability, and manageability requirements.
Compatibility with existing software while providing teraflops of
supercomputer-like performance and new capabilities for new
applications, workloads, and usage models
This is just one example of many possible architectural
scenarios since Micro 2015 is a composite of many capabilities
that may or may not be incorporated into Intel’s roadmap based
on current and future trends, requirements, and technological
constraints. Nonetheless, we believe it fairly represents the
overall shape of things to come.
Paul Otellini, Intel President & CEO
Keynote Address, IDF
Tens of billions of transistors in a single chip (as predicted by
Moore’s Law) Billions of Transistors in a Single ChipBillions of Transistors in a Single Chip
Parallelism at All LevelsParallelism at All Levels
Special Purpose Low-Power Hardware Engines for Real-Time Signal Processing
Special Purpose Low-Power Hardware Engines for Real-Time Signal Processing
Large High-Speed Global ReconfigurableOn-Chip Memory
Large High-Speed Global ReconfigurableOn-Chip Memory
High-Speed Interconnects Linking Cores Within Groups & Among Groups
High-Speed Interconnects Linking Cores Within Groups & Among Groups
Compatibility With Existing SoftwareCompatibility With Existing Software
Reconfigurable Circuits BlocksReconfigurable Circuits Blocks
www.intel.com/technology/computing/archinnov/platform2015/index.htm
10
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
Let’s Build The Future…Let’s Build The Future…2015 Today!2015 Today!
Reconfigurable Circuit Blocks
Reconfigurable Circuit Blocks
High-Speed Interconnects Linking Cores Within Groups & Among Groups
High-Speed Interconnects Linking Cores Within Groups &
Among Groups
Large High-Speed Global ReconfigurableOn-Chip Memory
Large High-Speed Global ReconfigurableOn-Chip Memory
Special Purpose Low-Power Hardware Engines for Real-Time Signal Processing
Special Purpose Low-Power Hardware Engines for Real-Time Signal Processing
Parallelism at All LevelsParallelism at All Levels
Billions of Transistors in a Single Chip
Billions of Transistors in a Single Chip
Compatibility With Existing Software
Compatibility With Existing Software
Standard HDL Design& Synthesis
Stratix IV EP4SGX230 Stratix IV EP4SGX230 Stratix IV EP4SGX230 Stratix IV EP4SGX230 Available NowAvailable NowAvailable NowAvailable Now
EP4SGX530 coming in few weeksEP4SGX530 coming in few weeksEP4SGX530 coming in few weeksEP4SGX530 coming in few weeks
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© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
Program memoryProgram memory
Functional unitsFunctional units
Data memoryData memory
Multi-Core Systems on FPGAsMulti-Core Systems on FPGAs
� Many programmable coarse-grained processors
− Soft blocks in FPGA fabric
− Each with local memory
− Homogeneous or
− Heterogeneous
� Programmable interconnect
� Software defined
− C Compilation to Microcode
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© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
Modern FPGAs: Massively ParallelModern FPGAs: Massively Parallel
Stratix® IV device
1,100 programmable I/O blocks
1,500 9-kbit memory blocks
1,300 DSP blocks
680,000 logic elements
64 144-k bits memory blocks
48 transceivers
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© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
Key Productivity ChallengesKey Productivity Challenges
Hardware design capture
RTL Synthesis
“Fitting” (Map, Place, Route)
Programming
CPU software development
Ha
rdw
are
de
sig
nS
oft
wa
re d
esig
n
Design idea
RTL, Schematic
Netlist
Post-Fit Netlist
Bitstream
C, C++
Object code
Can my softwareengineers accelerate their
software code?
Can my engineers Construct systems quickly
and easily?
Will my system architectureMeet my power budget?
Will the softwareautomatically optimize power,
and still meet timing?
Are the power estimates reliable?
Power management
Can teams in differentlocations work on the same
project?
Can my engineers reducetheir compile times?
Team productivity
System-leveldesign
Are we using the optimal system to close timing?
Unique Quartus IIUnique Quartus IIUnique Quartus IIUnique Quartus IIproductivity technologies productivity technologies productivity technologies productivity technologies save weeks to months of save weeks to months of save weeks to months of save weeks to months of
engineering effortengineering effortengineering effortengineering effort
Nios® II C2H
PowerPlay
SOPC Builder
TimeQuest
Team-based design and
incremental Compile
The Quartus II Software AdvantageThe Quartus II Software Advantage
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© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
One Tool for All Your Design NeedsOne Tool for All Your Design Needs
High-density,high-performance FPGAs
CPLDs StructuredASICs
Low-cost FPGAs Low-cost Transceiver FPGAs
Low Development Cost. Improved ProductivityLow Development Cost. Improved ProductivityLow Development Cost. Improved ProductivityLow Development Cost. Improved Productivity
15
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
Summary and ConclusionsSummary and Conclusions
� FPGA technology on 40nm allowing an incredible amount of reconfigurable silicon resources
� Universities are strongly encourage to take advantage and exploit innovation thanks this huge parallel technology available with low investment (no ASIC design)
� Reconfiguration must take into account industry constraints for practical applications
− Cost of qualification for Time to Market and Productivity
� Reconfigurable block that take advantage of huge embedded memory are likely to be the most successfull example of reconfiguration in real industry applications