CHAPTER 1

INTRODUCTION

1.1 INTRODUCTION

Wide utilization of memory storage systems and sequential logic in modern

electronics triggers a demand for high-performance and low area implementations of basic

memory components. In these circuits, the output not only depends upon the current values

of the inputs, but also upon preceding input values. These circuits are often called cyclic logic

circuits. These Timing elements (TEs) include latches, flip-flops, registers, and memory

storage cells are one of the most important components in synchronous VLSI designs. Their

performance has a critical effect on cycle time and they often account for a large fraction of

total system power. Therefore, there has been significant interest in the development of fast

and low power TE circuits, and correspondingly in techniques to evaluate their performance.

Previous work in TE characterization [1-5] has failed to consider the effect of circuit loading

on the relative ranking of TE structures. These earlier work used fixed, and usually overly

large, output loads when comparing alternatives. Input drive was either assumed to be large

[3, 5] or was not specified [1, 2, 4, 6, 7]. Bistable circuits exhibit two stable states representing

logic one and logic zero. These include latches and flip flops, which are useful in a number

of applications that require the temporary retention of one or more bits. Some examples are

counters, shift registers, and memories. Bistable circuits can also perform signal shaping

functions, e.g., the Schmitt trigger, which exhibits hysteresis and is useful in this regard. The

two requirements for realization of bistable operation are amplification (gain greater than

unity) and positive feedback. A circuit meeting these requirements can be built using two

cross-coupled inverters, as shown in Fig. 1. There are two stable states for this circuit: state 0 is

characterized by Q = 0 and Q' = 1 and state 1 is characterized by Q = 1 and Q' =0 Either

state is stable and will be maintained as long as the system power is on; therefore, this circuit

can retain 1 bit of information. T or toggle flip flop which is often used for counters can be

realized by connecting the J and K inputs of JK flip flop together. All of the popular flip flop

can easily be modified to incorporate asynchronous set and/or reset inputs. For master-slave

inputs, this normally means adding some extra circuitry to both the master and the slave latch

so that the asynchronous inputs will dominate independent of the clock and other inputs.

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These inputs are often used to initialize the state of digital ICs at the time the power is first

applied. Normally, a set or reset input is required, but seldom both. A T flip flop alternately

sends an output signal to two different outputs when an input signal is applied.

1.2 AIM OF THE PROJECT

The aim of project is by using GDI technique the power consumption, delay, chip area

and connection and parasitic capacitors is decreased. In this project, we are implementing the

new T-flip flop using GDI technique for low power and high speed in order to achieve power

delay product (PDP)

1.3 BASIC T-FLIP FLOP

T flip flop with clock pulse is shown in Fig. 1.1. This particular configuration is the

basis for many CMOS T flip flops, but it does suffer from a similar limitation as the SR flip

flop. The characteristic table for toggle or T flip flop is described in Table I. This is

equivalent with, if T is "0", the state will not change and if T is "1" then flip flop will

change state or toggle.

Figure 1.1: a T flip flop based on cross-coupled NOR gates.

T-FLIP FLOP:

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T Q(t+1)

No change 0 Q(t)

Toggle 1 Q'(t)

TABLE 1: THE CHARACTERISTIC TABLE FOR A TOGGLE OR

1.4 VLSI DESIGN CYCLE:

The design process of producing a package VLSI chip physically follows various steps

which is popularly known as VLSI design cycle. This design cycle is normally represented by a

flow chart shown below. The various steps involved in the design cycle are elaborated below.

Fig1.2. VLSI design flow

(i). System specification: The specifications of the system to be designed are exactly

specified in this step. It considers performance, functionality, and the physical dimensions of the

design. The choice of fabrication technology and design techniques is also considered. The end

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results are specifications for the size, speed, power, and functionality of the VLSI system to be

designed.

(ii) Functional design: In this step, behavioral aspects of the system are considered. The

outcome is usually a timing diagram or other relationships between sub-units. This information is

used to improve the overall design process and to reduce the complexity of the subsequent

phases.

(iii) Logic design: In this step, the functional design is converted into a logical design, using

the Boolean expressions. These expressions are minimized to achieve the smallest logic design

which conforms to the functional design. This logic design of the system is simulated and tested

to verify its correctness.

(iv) Circuit design: This step involves conversion of Boolean expressions into a circuit

representation by taking into consideration the speed and power requirements of the original

design. The electrical behavior of the various components is also considered in this phase. The

circuit design is usually expressed in a detailed circuit diagram.

(v) Physical design: In this step, the circuit representation of each component is converted

into a geometric representation. This representation is a set of geometric patterns which perform

the intended logic function of the corresponding component. Connections between different

components are also expressed as geometric patterns. (This geometric representation of a circuit

is called a layout). The exact details of the layout also depend on design rules, which are

guidelines based on the limitations of the fabrication process and the electrical properties of the

fabrication materials. Physical design is a very complex process; therefore, it is usually broken

down into various sub-steps in order to handle the complexity of the problem.

(vi) Design verification: In this step, the layout is verified to ensure that the layout meets the

system specifications and the fabrication requirements. Design verification consists of design

rule checking (DRC) and circuit extraction. DRC is a process which verifies that all geometric

patterns meet the design rules imposed by the fabrication process. After checking the layout for

design rule violations and removing them, the functionality of the layout is verified by circuit

extraction. This is a reverse engineering process and generates the circuit representation from the

layout. This reverse engineered circuit representation can then be compared to the original circuit

representation to verify the correctness of the layout

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(vii) Fabrication: This step is followed after the design verification. The fabrication process

consists of several steps like, preparation of wafer, deposition, and diffusion of various materials

on the wafer according to the layout description. A typical wafer is 10 cm in diameter and can be

used to produce between 12 and 30 chips. Before the chip is mass produced, a prototype is made

and tested.

(viii) Packaging, testing, and debugging: In this step, the chip is fabricated and diced in

a fabrication facility. Each chip is then packaged and tested to ensure that it meets all the design

specifications and that it functions properly. Chips used in printed circuit boards (PCBs) are

packaged in a dual in-line package (DIP) or pin grid array (PGA). Chips which are to be used in

a multichip module (MCM) are not packaged because MCMs use bare or naked chips.

1.5 PHYSICAL DESIGN CYCLE:The Physical design cycle converts a circuit diagram into a layout. This complex task is

completed in several steps, like partitioning, floor-planning, placement, routing, and lay-out

compaction etc. The details of these steps are given below.

(a) Partitioning: The chip layout is always a complex task and hence it is divided into several

smaller tasks. A chip may contain several million transistors. Layout of the entire circuit cannot

be handled due to the limitation of memory space as well as computation power available.

Therefore, it is normally partitioned by grouping the components into blocks. The actual

partitioning process considers many factors such as size of the blocks, number of blocks, and

number of interconnections between the blocks. The output of partitioning is a set of blocks

along with the interconnections required between blocks. The set of interconnections required is

referred to as a net list. In large circuits the partitioning process is hierarchical and at the

topmost level a chip may have between 5 and 25 blocks. Each module is then partitioned

recursively into smaller blocks.

A disadvantage of the partitioning process is that it may degrade the performance of the final

design. During partitioning, critical components should be assigned to the same partition. If such

an assignment is not possible, then appropriate timing constraints must be generated to keep the

two critical components close together. Usually, several components, forming a critical path,

determine the chip performance. If each component is assigned to a different partition, the

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critical path may be too long. Minimizing the length of critical paths improves system

performance.

After a chip has been partitioned, each of the sub-circuits must be placed on a fixed plane and the

nets between all the partitions must be interconnected. The placement of the sub-circuits is done

by the placement algorithms and the nets are routed by using routing algorithms.

(b) Placement: It is the process of arranging a set of modules on the layout surface. Each

module has fixed shape and fixed terminal locations. A poor placement uses larger area and

hence results in performance degradation.

The placement process determines the exact positions of the blocks on the chip, so as to find a

minimum area arrangement for the blocks that allows completion of interconnections between

the blocks. Placement is typically done in two phases. In the first phase an initial placement is

created. In the second phase the initial placement is evaluated and iterative improvements are

made until the layout has minimum area and conforms to design specifications.

It is important to note that some space between the blocks is intentionally left empty to allow

interconnections between blocks. Placement may lead to un-routable design, i.e., routing may not

be possible in the space provided. Thus, another iteration of placement is necessary. To limit the

number of iterations of the placement algorithm, an estimate of the required routing space is used

during the placement phase. A good routing and circuit performance heavily depend on a good

placement algorithm. This is due to the fact that once the position of each block is fixed, very

little can be done to improve the routing and the overall circuit performance.

There are various types of placements.

System-level placement: Place all the PCBs together such that Area occupied is minimum

and Heat dissipation is within limits.

Board-level placement: All the chips have to be placed on a PCB. Area is fixed all modules

of rectangular shape.

The objective is to, minimize the number of routing layers and Meet system performance

requirements.

Chip-level placement: Normally, floor planning / placement carried out along with pin

assignment. It has limited number of routing layers (2 to 4). Bad placements may be unroutable.

Can be detected only later (during routing). Costly delays in design cycle. Minimization of area.

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Floor planning:Floor-plan design is an important step in physical design of VLSI circuits to plan the positions of

a set of circuit modules on a chip in order to optimize the circuit performance.

In floor-planning, the information of a set of modules, including their areas and interconnection

is considered and the goal is to plan their positions on a chip to minimize the total chip area and

interconnect cost.

In the floor planning phase, the macro cells are positioned on the layout surface in such a way

that no blocks overlap and that there is enough space left to complete the interconnections. The

input for the floor planning is a set of modules, a list of terminals (pins for interconnections) for

each module and a net list, which describes the terminals which have to be connected.

Fig1.3. Physical design process

(c) Routing: The main objective in this step is to complete the interconnections between

blocks according to the specified net list. First, the space not occupied by the blocks (called the

routing space) is partitioned into rectangular regions called channels and switchboxes. The goal

of a router is to complete all circuit connections using the shortest possible wire length and using

only the channels and switchboxes. This is usually done in two phases, referred to as the global

routing and detailed routing phases.

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In global routing, connections are completed between the proper blocks of the circuit

disregarding the exact geometric details of each wire and pin. For each wire, the global router

finds a list of channels which are to be used as a passage way for that wire. In other words,

global routing specifies the ‘‘loose route’’ of a wire through different regions in the routing

space. Global routing is followed by detailed routing, which completes point-to-point

connections between pins on the blocks. Loose routing is converted into exact routing by

specifying geometric information such as width of wires and their layer assignments. Detailed

routing includes channel routing and switchbox routing.

As all problems in routing are computationally hard, the researchers have focused on heuristic

algorithms. As a result, experimental evaluation has become an integral part of all algorithms and

several benchmarks have been standardized. Due to the nature of the routing algorithms,

complete routing of all the connections cannot be guaranteed in many cases

(d) Compaction: The operation of layout area minimization without violating the design rules

and without altering the original functionality of layout is called as compaction. The input of

compaction is layout and output is also layout but by minimizing area.

Compaction is done by three ways:

(i) By reducing space between blocks without violating design space rule.

(ii) By reducing size of each block without violating design size rule.

(iii).By reducing shape of blocks without violating electrical characteristics of blocks.

Therefore compaction is very complex process because this process requires the knowledge of

all design rules. Due to the use of strategies compaction algorithms are divided into one-

dimensional algorithms (either in x-dimension or y-dimension), two dimensional algorithms

(both in x-dimension and y-dimension) and topological algorithm (moving of separate cells

according to routing constraints).

1.6 VLSI –DESIGN STYLES Though the partitioning of a physical design decomposes the physical design into

several conceptually easier steps, still each step is computationally very hard. So, in order to

reduce the complexity of physical design and to get high yield certain restricted models and

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design styles are proposed. They are (i) full-custom design style (ii) standard cell design style

(iii) gate array design style

1.7 SIMULATIONThe objective behind any simulation tool is to create a computer based model for the

design verification and analyzing the behavior of circuits under construction also checking the

current level of abstraction.

Types of Simulation:  Device level simulation, Circuit level simulation, Timing level & Macro level

simulation, Switch level simulation, Gate level simulation, RTL simulation, System level

simulation.

Device level simulation:

This model involves with a semiconductor device like a MOS transistor used to test the

effect of fabrication parameters .Simulator techniques based on finite-element method are used

for this purpose.

Circuit level simulation:

It deals with small groups of transistors modeled in the analog domain .The variables

computed are currents and voltages and the computations are based on numerical methods.

Switch level simulation:

This simulation method, models the MOS transistors as switches, that pass signals .The

values of signals are discrete, but it also includes certain analog features to combine certain

components like resistance and capacitance.

Gate level simulation: In this model a circuit is composed of several logic gates connected by uni-directional

memory less wires. The logic gates themselves are collections of transistors and other circuit

elements which perform a logic function. A logic gate may be a simple inverter or NAND gate or

NOR gate or more complex functional unit like a flip-flop or register.

Register –Transfer Level (RTL) simulation: This model is used synchronous circuits where all registers are controlled by a system

clock signal. The registers store the state of the system, while the combinational logic computes

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the next state and the output based on the current state and the input. Here the important

consideration is the state transitions and the precise timing of intermediate signals in the

computation of the next state is not considered.

System level Simulation:

It deals with the hardware described in terms of primitives that need not correspond with

hardware building blocks. VHDL is the most popular hardware description language used for

system level simulation. When used in the initial stages of a design, it can describe the behavior

of a circuit as a processor as a set of communicating processes.

1.8 OVERVIEW

This project proposes of a low-power high-speed T flip flop Using GDI Technique.

This novel technique proposes a new method for designing logical circuits in standard

technologies of CMOS. Performance comparison with traditional CMOS and various

transistors logic design techniques. The different methods are compared with respect to

layout area, number of devices, delay, and power dissipation.

1.9 OUTLINE

In the chapter 2 there is a brief explanation of GATE DIFFUSION INPUT TECHNIQUE, and its operational analysis.

In the chapter 3, there is a brief explanation about software used for the project i.e. MENTOR GRAPHICS, and tool used is PYXIS.

In chapters 4 & 5th the stimulation results of both CMOS and GDI are shown detailed.

In chapter 6th comparison results and power dissipation of both CMOS and GDI are shown.

1.10 CONCLUSION

In this project we proposed a GDI T flip flop for low-power design was presented. The

proposed circuit has a simple structure, based on two Master-Slave principles, and some gates to

describe T flip flop. It contains 24 transistors. An optimization procedure was developed for GDI

TFF, based on iterative transistor sizing, while targeting a minimal power-delay product.

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Performance comparison with other TFF design techniques was shown, with respect to gate area,

delay and power dissipation.

CHAPTER 2

LOW POWER HIGH SPEED T-FLIP FLOP USING GATE

DIFFUSION INPUT TECHNIQUE

2.1 GATE DIFFUSION INPUT (GDI) The performance of a digital circuit is judged by its speed in producing output when an

input is given to it. The most common technology for designing digital circuits is the CMOS

technology. After the development of CMOS logic, there was increasing need to optimize circuit

in terms of speed. One technique thought of was by using Pass Transistor Technology (PTL)

which makes use of lesser number of gates to realize an operation. The Transmission Gate (TG)

is one of them which are typically a combination of NMOS and PMOS transistors connected in

parallel. The GDI cell represents another form of pass transistor technology which looks similar

to CMOS but differs in the supply provided to the input terminals. The main advantages of PTL

over conventional CMOS design are as follows- 1) lesser number of transistors results in low

power dissipation and lesser delay. 2) Lesser number of transistors so smaller area and lesser

interconnect effects. However, PTL technologies also suffer from two main problems such as

reduced circuit speed at low power operations and greater static power dissipation.

GDI technique that can be used to design fast, low power circuits using only a few transistors.

The GDI cell is similar to a CMOS inverter structure. In a CMOS inverter the source of the

PMOS is connected to VDD and the source of NMOS is grounded. But in a GDI cell this might

not necessarily occur. There are some important differences between the two. The three inputs in

GDI are namely-

1) G- common inputs to the gate of NMOS and PMOS

2) N- input to the source/drain of NMOS

3) P- input to the source/drain of PMOS

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Bulks of both NMOS and PMOS are connected to N or P (respectively), that is it can be

arbitrarily biased unlike in CMOS inverter. Moreover, the most important difference between

CMOS and GDI is that in GDI N, P and G terminals could be given a supply ‘VDD’ or can be

grounded or can be supplied with input signal depending upon the circuit to be designed and

hence effectively minimizing the number of transistors used in case of most logic circuits (eg.

AND, OR, XOR, MUX, etc). As the allotment of supply and ground to PMOS and NMOS is not

fixed in case of GDI, therefore, problem of low voltage swing arises in case of GDI which is a

drawback and hence finds difficulty in case of implementation of analog circuits.

2.2 OPERATIONAL ANALYSIS

The most common problem with PTL technique is its low voltage swing. An extra buffer

circuitry may be used additionally to eliminate the problem of low swing and improve

drivability. The problem of low swing can be understood with the help of a random function

shown in figure and table.

Functionality Of any

Random Function

using GDI A

B Functionality Logic

A B Y

0 0 pMOS Trans Gate Vtp

0 1 CMOS Inverter 1

1 0 nMOS Trans Gate 0

1 1 CMOS Inverter 0

Table 2.1 GDI truth table for inverter

The problem of low swing occurs only when A=0 and B=0 where the voltage level is VTP

instead of 0.This occurs due to the poor high to low transition characteristics of PMOS. In the

rest of the cases it provides full swing.

2.3 GDI CELL USING SHANNON EXPANSION

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Shannon’s Expansion Theorem: The Shannon’s expansion theorem is used iteratively to build any BDD for a given

Boolean function.

Shannon’s expansion theorem states that “Any switching function of n variables can be

expressed as a sum of products of n literals, one for each variable’.

Let us assume that f (x1, x2, ..., xn) is a switching function of n variables. According to Shannon

, one way of expressing this function is

f(x1, x2, ..., xn) = x1f(1, x2, ..., xn) + x1'f(0, x2, ..., xn)

On the right side, the function is the sum of two terms, one of them relevant when x1 is equal to 1

and the other when x1 is equal to 0 . The first term is x1 times what remains of f when x1 is equal

to the value 1 and the second term is x1' times what remains of f when x1 is equal to 0.

Shannon’s expansion theorem in the general case is

f = a0 x1'x2' ... xn' + a1x1'x2' ... xn–1'xn + a2x1'x2' ... xn–1 xn' + ...+ a2n–2 x1x2... xn' + a2n–1 x1x2... xn

Each ai is a constant in which the subscript is the decimal equivalent of the multiplier of

ai viewed as a binary number. Thus, for three variables, a5 (binary 101) is the coefficient of

x1x2'x3.

In a similar way it can be stated as “any switching function of n variables can be expressed as a

product of sums of n literals, one for each variable “.

The concept of Shannon theorem could be applied with ease to design a basic GDI cell. In

Shannon expansion theorem, any function F can be written as: F(x1…xn) = x1H(x2….xn) + (not

x1)G(x2…xn) = x1F(1,x2…xn)+(notx1)F(0,x2….xn) (1) That is a larger function can be broken

down into smaller function as shown above in equation (1). Then, the smaller functions could be

further broken down if possible till the time it is not further reducible. The output function of a

basic GDI cell (where A, B, and C are inputs to G, P, and N, respectively) is given by: Out=AC

+ (notA) B (2) Therefore, comparing equations (1) and (2) it is seen that a standard GDI cell can

be used to implement any logic function based on Shannon expansion theorem as shown below

taking an example. If A=x1, C=F(1,x1….xn), B=F(0,x1…..xn) then Out=F(x1…xn)=x1F(1,x2…

xn) +( not x1) F(0,x2…xn).

2.4 BASIC T FLIP FLOP:T flip flop with clock pulse is shown in Fig. 2.1. This particular configuration is the

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basis for many CMOS T flip flops, but it does suffer from a similar limitation as the SR flip

flop. The characteristic table for toggle or T flip flop is described in Table I. This is

equivalent with, if T is "0", the state will not change and if T is "1" then flip flop will

change state or toggle.

Figure 2.1: a T flip flop based on cross-coupled NOR gates.

TABLE 2.2: THE CHARACTERISTIC TABLE FOR A TOGGLE OR

2.5 BASIC GDI CELL

The GDI method is based on the simple cell shown in Fig.2.2. A basic GDI cell contains

four terminals - G (the common gate input of the nMOS and pMOS transistors), P (the outer

diffusion node of the pMOS transistor), N (the outer diffusion node of the nMOS transistor)

and the D node (the common diffusion of both transistors). P, N and D may be used as either

input or output ports, depending on the circuit structure. Table 2.3 shows how various

configuration changes of the inputs P, N and G in the basic GDI cell correspond to different

Boolean functions at the output D. GDI enables simpler gates, lower transistor count, and

lower power dissipation in many implementations, as compared with standard CMOS and

Pass-transistor Logic (PTL) design techniques .

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T Q(t+1)

No Change 0 Q(t)

Toggle 1 Q'(t)

Figure 2.2: GDI basic cell

N P G D Function'0' B A HB F1B '1' A H + B F2'1' B A A + B ORB '0' A AB ANDC B A HB+AC MUX'0' '1' A H NOT

TABLE 2.3: SOME LOGIC FUNCTIONS THAT CAN BE IMPLENTED WITH A

SINGLE GDI CELL.

2.6 DESIGN OF LOW-POWER, HIGH-SPEED GDI T FLIP FLOP

A novel implementation of a GDI TFF is shown in Fig.2.3. It is based on the Master-

Slave connection of two GDI Latches and some gates. Each latch consists of four basic GDI

cells, resulting in a simple eight-transistor structure and gates consists six transistors in order

that related with latch. The components of the latch circuit can be divided into two main

categories; GDI gate and inverter. GDI gate uses two transistors and controlled by the Clk

signal. Clk signals fed to the gate of transistors and create two alternative states: one state is

when the Clk is low and the signals are propagating through PMOS transistors and create

transient state and other one is when the Clk is high and the prior values are maintained due

to conduction of the outputs. In this state, GDI gates holding state of the latch. Other gates

for main T flip flop are inverter gates. They are responsible for maintaining the

complementary values of the internal signals and the circuit outputs. Note that the size of the

p-channel transistor is wider than that of the n-channel transistor. This width difference is

not needed for functionally correct operation. Rather, it somewhat compensates for the

difference in the motilities of n-channel and p-channel transistors. The effective mobility of

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n-channel transistors is between two and four times that of p-channel transistors. These

inverters has important role for swing restoration and improved driving abilities of the

outputs, it's buffering of the internal signals and create suitable output current for driving of

load.

Figure 2.3: GDI T-flip flop implementation

2.7 SIMULATION SETUPA T flip flop designed in GDI and two kinds of CMOS was simulated in 0.18Km TSMC CMOS

technology. Simulation results shows compare the GDI design with a set of representative flip

flops, commonly used for high performance design. The circuits were simulated using ADS 2008

at 1.8V, 500 MHz and 27 0c, with load capacitance of 100fF. The simulation setup is shown in

Fig.2.5. The device under test was placed between input buffers to account for the current

consumption from the previous stage, and output buffers to emulate real environmental

conditions

The reference circuits are presented in Fig.2.5. The set includes (a) modified CMOS after and (b)

TGB after. These circuits have been sized according to optimization procedure, as presented in

Fig.2.6. shows timing diagram of input clock, square input wave, output of T flip flop (Q) and its

differential output (Q') for proposed T flip flop.

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Average Power: Best results of average power are observed for the dynamic GDI ~ 77 %

(approximately) less than the modified CMOS implementation and 84% less than the TGB

circuit (which is the best CMOS implementation in terms of power). GDI T-flip flop shows

results close to the CMOS circuit, and better than any static CMOS implementation.

1)Maximal Delay: The Dynamic GDI is the fastest circuit, showing up to 44% decrease

compared to modified CMOS techniques, and a 76% improvement compared to the TGB, which

is the fastest technique among CMOS circuits.

2) Power delay product: GDI T flip flop circuit has 87% decrease PDP compared to modified

CMOS technique and 96% less than TGB circuit.

It should be noted that the optimization in all compared circuits is performance-driven

(minimal power-delay product is obtained by sizing), while separate parameters, like average

power and maximal delay are secondary. The Simulation results diagram obtained through can

be seen in Fig. For Average power and PDP used.

The layout of the proposed low-power, high-speed TFF is presented in Fig.

(a) (b)

Figure 2.5: Set of representative flip -flops for comparison: (a) modified CMOS, (b) tgb

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(a) (b)

(c) (d)

Figure 2.6: timing diagram of a) input clock, b) square input wave, c) output of T flip flop (Q) and d)

differential output (Q')

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(a) (b)

Figure 2.7: Simulation results diagram and comparison of modified CMOS,

TGB and GDI for a) Average power and b) PDP used.

CHAPTER 3

TOOLS USED

3.1 Mentor graphics history

In 1981, the idea of computer-aided design for electronics as the foundation of a

company occurred to several groups - those who founded Mentor, Valid Logic Systems,

and Daisy Systems. One of the main distinctions between these groups was that the founding

engineers of Mentor, whose backgrounds were in software development at Tektronix, ruled out

designing and manufacturing proprietary computers to run their software applications. They felt

that hardware was going to become a commodity owned by big computer companies, so instead

they would select an existing computer system as the hardware platform for the Computer Aided

Engineering (CAE) programs they would build.

By February 1981, most of the start-up team had been identified; by March, the three executive

founders, Tom Bruggere, Gerry Langeler and Dave Moffenbeier had left Tektronix, and by May

the business plan was complete. The first round of money, $1 million, came from Sutter Hill,

Greylock, and Venrock Associates. The next round was $2 million from five venture capital

firms and in April 1983 a third round raised $7 million more. Mentor Graphics was one of the

first companies to attract venture capital to Oregon. Apollo Computer workstations were chosen

as the initial hardware platform. Based in Chelmsford, Apollo was less than a year old and had

only announced itself to the public a few weeks prior to when the founders of Mentor Graphics

began their initial meetings.

When Mentor entered the CAE market the company had two technical differentiators: the first

was the software - Mentor, Valid, and Daisy each had software with different strengths and

weaknesses. The second was the hardware - Mentor ran all programs on the Apollo workstation,

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while Daisy and Valid each built their own hardware. By the late 1980s, all EDA companies

abandoned proprietary hardware in favor of workstations manufactured by companies such as

Apollo and Sun Microsystems. After a frenzied development, the IDEA 1000 product was

introduced at the 1982 Design Automation Conference, though in a suite and not on the floor. By

the time founder Bruggere ran for the U.S. Senate in 1996, the company had grown to annual

revenues of $384 million.

Mentor Graphics is a global company with product development taking place in the USA,

Europe, Japan, Pakistan, India and Egypt. In keeping with global trends in software

development, the company has a substantial labor force in lower cost locations such as Pakistan,

India, Poland, Hungary and Egypt. James "Jim" Ready, one of the more colorful people

in embedded systems, left Mentor in 1999 to form the embedded Linux company MontaVista.

Neil Henderson, a pioneer in the royalty-free, source provided market space, joined Mentor

Graphics in 2002 with the acquisition of Accelerated Technology Inc. Stephen Mellor, a leader

in the UML space and co-originator of the Shlaer-Mellordesign methodology, joined Mentor

Graphics in 2004 following the acquisition of Project Technology. As of 2012, Mentor's major

competitors are: Cadence Design Systems, Synopsys and Zuken.

In June 2008, Cadence Design Systems offered to acquire Mentor Graphics in a leveraged

buyout. On 15 August 2008, Cadence withdrew this offer quoting an inability to raise the

necessary capital and the unwillingness of Mentor Graphics' Board and management to discuss

the offer. Mentor acquired Flomerics Group plc for $60 million in cash in October 2008, and in

August 2009, Mentor completed the acquisition of silicon manufacturing testing

company LogicVision for $13 million in an all stock deal.[8] Mentor completed the acquisition of

Valor Computerized Systems in March 2010 in a cash and stock deal valued at $50 million.

On 22 February 2011, Carl Icahn, an activist investor, made an offer to buy the company for

about $1.86 billion in cash in a move to push other suitors to declare themselves.

3.2 Tools Distributed By Mentor Graphics:

Electronic design automation for:

20

Integrated circuit layout full-custom and SDL tools such as IC Station

IC place and route tool: Olympus-SoC

IC Verification tools such as Calibre nmDRC, Calibre nmLVS, Calibre xRC, Calibre

xACT 3D

IC Design for Manufacturing tools such as Calibre LFD, Calibre YieldEnhancer and

Calibre YieldAnalyzer

Schematic editors for electronic schematics such as Design Architect IC or DxDesigner

A Layout tools for printed circuit boards with programs such as PADS, Expedition

Enterprise and Board Station

Component library management tools

FPGA synthesis tools:

Precision synthesis - Advanced RTL & physical synthesis for FPGAs

Simulation tools for analog mixed-signal design:

ModelSim is a hardware simulation and debug environment primarily targeted at smaller

ASIC and FPGA design

QuestaSim is a Simulator with additional Debug capabilities targeted at complex FPGA's

and SoC's. QuestaSim can be used by users who have experience with ModelSim as it

shares most of the common debug features and capabilities. One of the main differences

between QuestaSim and Modelsim (besides performance/capacity) is that QuestaSim is

the simulation engine for the Questa Platform which includes integration of Verification

Management, Formal based technologies, Questa Verification IP, Low Power Simulation

and Accelerated Coverage Closure technologies. QuestaSim natively supports System

Verilog for Test bench, UPF, UCIS, OVM/UVM where ModelSim does not.

Eldo is a SPICE simulator

SystemVision is a virtual lab for mechatronic system design and analysis

ADiT is a Fast-SPICE simulator

Questa ADMS is a mixed-signal verification tool

21

3.3 PYXIS LAYOUTPyxis Layout, part of Mentor's new Pyxis Custom IC Design Platform, provides a fast and

flexible environment for layout entry and editing.

Pyxis Layout supports an extensive set of editing functions for efficient, accurate polygon

editing. This gives the design engineer full control of circuit density and performance, while

improving productivity by as much as 5X. Hierarchy and advanced window management allows

multiple views of the same cell and provides the capability to edit both views. Additionally,

design engineers can create matched analog layouts quickly by editing using a half-cell

methodology.

Pyxis Layout interacts seamlessly with other solutions in the Pyxis Custom IC Design Platform

to create, develop, simulate, verify, optimize and implement even the most challenging full

custom analog and mixed-signal IC designs quickly and accurately—the first time. As a

designer, you enjoy a consistent look and feel in single environment, whether creating

schematics, block diagrams, symbols, or HDL representations. Additionally, Mentor’s foundry

partners provide certified design kits for use with Pyxis Custom IC Design Platform solutions.

Schematic Driven Layout

Schematic-driven layout (SDL) is a design methodology that enables design engineers to

create "correct by construction" layouts. These layouts are based on information from a

schematic or a net list source. By using the designs connectivity, Pyxis SDL enables automated

creation of layout data, while maintaining the relationship between layout and schematic,

reducing design cycle time and assuring layout is free of LVS violations.

Any mix of polygons, device generators (either custom, built-in or from a foundry supplied

Process Design Kit), and cell data are supported in the layout environment. Available as an add-

on option to Pyxis Layout, Pyxis SDL enables this functionality, reducing design cycle time and

assuring correct-by-construction layout.

22

Concurrent Editing

Pyxis Concurrent, an add-on option for Pyxis Layout, allows multiple designers to

simultaneously make edits to the same cell. With Pyxis Concurrent, multiple designers can join a

layout session in shared mode. Once in the session, the designers create fences to define their

work area. They can create one or more fences and can make edits to any shape or path that is

wholly enclosed within their fenced area. These shapes are local to the session and are not stored

with the design.

3.4 BENEFITS AND OPTIONS

KEY BENEFITS

Improves layout design throughput up to 50X compared to manual layout methods.

Multiple tools support increasing level of layout automation.

Reduces design rule checking (DRC) debugging cycles, leading to shortened time-to-market.

Creates DRC/LVS–correct complex layout with a simple command to improve reliability of final

product.

Options

Pyxis Concurrent – Adds concurrent editing functionality to Pyxis Layout

Pyxis TFT-LCD – Adds functionality required for flat panel design to Pyxis Layout

Pyxis Plot – Enables plotting to HP Plotter from Pyxis Layout verification requirements.

Mentor Graphics Analog/Mixed-Signal IC Design Flow

23

Fig.3.1 IC-Design Flow

Fig.3.2 Pyxis Tool Set

24

3.5 ASIC CAD tools available in ECE

Modeling and Simulation Questa

ADMS = Questa+Modelsim+Eldo+ADiT(Mentor Graphics)

Verilog-XL, NC_Verilog, Spectre(Cadence)

Design Synthesis (digital) Leonardo Spectrum(Mentor Graphics)

Design Compiler (Synopsys), RTL Compiler (Cadence)

Design for Test and Automatic Test Pattern GenerationTessentDFT Advisor,

Fastscan, SoCScan(Mentor Graphics)

Schematic Capture & Design IntegrationDesign Architect-IC (Mentor Graphics)

Design Framework II (DFII) -Composer (Cadence)

Physical LayoutIC Station (Mentor Graphics)

SOC Encounter, Virtuoso (Cadence)

Design VerificationCalibreDRC, LVS, PEX (Mentor Graphics)

Diva, Assura(Cadence)

3.6 Mentor Graphics ASIC Design Kit (ADK)

Technology files & standard cell librariesAMI: ami12, ami05 (1.2, 0.5 μm)

TSMC: tsmc035, tsmc025, tsmc018 (0.35, 0.25**, 0.18 μm) **also have VT Cadence lib

Current MOSIS Instructional: IBM 180nm CMOS (7RF), ON Semi 0.5um CMOS

Current MOSIS Unfunded Research: IBM 130nm CMOS (8RF), 130nm SiGEBiCMOS(8HP)

IC flow & DFT tool support files:Simulation models VHDL/Verilog/Mixed-Signal

models(ModelsimSE/Questa ADMS)

25

Analog (SPICE) models(Eldo, ADiT)

*Post-layout timing (Mach TA) * obsolete: Mach TA replaced by ADiT

*Digital schematic (QuicksimII, QuicksimPro)* obsolete: HDL or Eldo now used

Standard cell synthesis libraries (LeonardoSpectrum)

Design for test & ATPG libraries (DFT Advisor, Fastscan)

Schematic capture (Design Architect-IC)

IC physical design (standard cell & custom) Standard cell models, symbols, layouts (IC Station)

Design rule check, layout vsschematic, parameter extraction (Calibre)

3.7 CALIBRE RVE

Results Viewing Environment

26

Fig 3.3 Calibre RVE’s robust viewing and debugging capabilities

ACCELERATING TIME TO TAPE-OUT

While the Calibre platform’s best-in-class engines provide physical and circuit

verification results in record time, you still need to fix the identified layout issues before you can

tape out.

Calibre RVE provides fast, flexible, and easy-to-use graphical debugging capabilities that

minimize your turnaround time and get you to “tapeout-clean” on schedule. Calibre RVE is

integrated into all the popular layout environments, including Mentor Graphics IC Station,

Calibre DESIGNrev, Synopsys IC Compiler, Cadence Encounter, Cadence Virtuoso, Springsoft

Laker, Seiko, Tanner, and Agilent ADS. Whatever design environment you use, Calibre RVE

provides the debugging technology you need for fast, accurate error resolution.

27

While the Calibre platform’s best-in-class engines provide physical and circuit verification results in

record time, you still need to fix the identified layout issues before you can tape out. Calibre RVE

provides fast, flexible, and easy-to-use graphical debugging capabilities that minimize your turnaround

time and get you to “tapeout-clean” on schedule. Calibre RVE is integrated into all the popular layout

environments, including Mentor Graphics IC Station, Calibre DESIGNrev, Synopsys IC Compiler,

Cadence Encounter, Cadence Virtuoso, Springsoft Laker, Seiko, Tanner, and Agilent ADS. Whatever

design environment you use, Calibre RVE provides the debugging technology you need for fast,

accurate error resolution.

While the Calibre platform’s best-in-class engines provide physical and circuit

verification results in record time, you still need to fix the identified layout issues before you can

tape out. Calibre RVE provides fast, flexible, and easy-to-use graphical debugging capabilities

that minimize your turnaround time and get you to “tapeout-clean” on schedule. Calibre RVE is

integrated into all the popular layout environments, including Mentor Graphics IC Station,

Calibre DESIGNrev, Synopsys IC Compiler, Cadence Encounter, Cadence Virtuoso, Springsoft

Laker, Seiko, Tanner, and Agilent ADS. Whatever design environment you use, Calibre RVE

provides the debugging technology you need for fast, accurate error resolution.

While the Calibre platform’s best-in-class engines provide physical and circuit

verification results in record time, you still need to fix the identified layout issues before you can

tape out. Calibre RVE provides fast, flexible, and easy-to-use graphical debugging capabilities

that minimize your turnaround time and get you to “tapeout-clean” on schedule. Calibre RVE is

integrated into all the popular layout environments, including Mentor Graphics IC Station,

Calibre DESIGNrev, Synopsys IC Compiler, Cadence Encounter, Cadence Virtuoso, Springsoft

Laker, Seiko, Tanner, and Agilent ADS. Whatever design environment you use, Calibre RVE

provides the debugging technology you need for fast, accurate error resolution.

PHYSICAL VERIFICATION

However complex the rule deck, Calibre RVE can handle it. Even with millions of error

results, Calibre RVE provides fast navigation through the layout, allowing you to focus on

analyzing and fixing the errors. The tabbed viewing format enables you to easily organize data

28

by tiling the display windows side by side. And, because Calibre RVE is designed with a low-

memory footprint, you can run it on the same machine you use for your design environment.

Waived errors can be a source of needless work and lost time. Calibre RVE provides a flexible

waiver flow to persistently mark, annotate, and review error results that will be waived by the

foundry. Calibre RVE also provides integrated support for the Calibre Auto-Waiver flow and

automatically removes waivers from the results, reducing your turnaround time even further.

CALIBRE RVE:

• Filters error results by cell, check, property, waived, and fixed status so you can quickly

select only the results you want to review.

• Highlights DRC results in the context in which they occur, providing greater flexibility

in error visualization,location and analysis.

• Marks and comments waived errors for subsequent DRC runs.

• Provides statistical summaries of error properties across checks and cells.

• Enables designers to merge generated polygons (such as metal fill) into the original

layout database.

Circuit Verification

Calibre RVE has kept pace with the expanding requirements of circuit verification with a

wide range of capabilities, including: layout vs. schematic (LVS), schematic vs. schematic

(SVS), electrical rule checking (ERC), programmable electrical rule checking (PERC), soft

checks, point-to-point resistance checking, and current density checking. By providing both

source and layout schematics, Calibre RVE can easily and quickly cross-highlight between the

schematics, the design layout, and the Calibre LVS results report

Calibre RVE circuit verification capabilities include:

29

• Fast and intuitive schematic visualization and hierarchical SPICE browser to navigate and

highlight nets and devices. Highlights appear in layout and schematic windows, along with the

Calibre RVE layout and source schematics.

• Fix suggestions that provide an English description of the error (e.g., “Layout net 5 and 10 are

shorted”) to simplify and speed up the debugging process.

• Advanced Short Isolation function that can be run hierarchically and by layer to quickly isolate

the root cause of a texted short.

When the short isolation algorithm is unable to pinpoint the short, the Calibre RVE interface

enables the user to interactively isolate the issue without re-running the batch tool.

Fig 3.4 cross-probing capabilities

3.8 DRC

Design Rule Checking or Check(s) (DRC) is the area of Electronic Design

Automation that determines whether the physical layout of a particular chip layout satisfies a

30

series of recommended parameters called Design Rules. Design rule checking is a major step

during Physical verification signoff on the design, which also involves LVS (Layout versus

schematic) Check, XOR Checks, ERC (Electrical Rule Check) and Antenna Checks. For

advanced processes some fabs also insist upon the use of more restricted rules to improve yield.

Fig 3.5 Basic DRC checks - width, spacing, and enclosure

Design Rules are a series of parameters provided by semiconductor manufacturers that enable the

designer to verify the correctness of a mask set. Design rules are specific to a particular semiconductor

manufacturing process. A design rule set specifies certain geometric and connectivity restrictions to

ensure sufficient margins to account for variability in semiconductor manufacturing processes, so as to

ensure that most of the parts work correctly.

DESIGN RULE CHECKING SOFTWARE

The main objective of design rule checking (DRC) is to achieve a high overall yield and

reliability for the design. If design rules are violated the design may not be functional. To meet this goal

of improving die yields, DRC has evolved from simple measurement and Boolean checks, to more

involved rules that modify existing features, insert new features, and check the entire design for process

limitations such as layer density. A completed layout consists not only of the geometric representation of

the design, but also data that provides support for the manufacture of the design. While design rule checks

do not validate that the design will operate correctly, they are constructed to verify that the structure

meets the process constraints for a given design type and process technology.

SOME EXAMPLE OF DRC'S IN IC DESIGN INCLUDE:

31

Active to active spacing

Well to well spacing

Minimum channel length of the transistor

Minimum metal width

Metal to metal spacing

Metal fill density (for processes using CMP)

Poly density

ESD and I/O rules

Antenna effect

Commercial DRC Software

Major products in the DRC area of EDA include:

Advanced Design System Design Rule Checker by Agilent's EEsof EDA division

Calibre by Mentor Graphics

Diva, Dracula, Assura and PVS by Cadence Design Systems

Hercules and IC Validator by Synopsys

Quartz by Magma Design Automation

3.9 LVS

Calibre nmLVS, the market-leading layout vs. schematic physical verification tool, is tightly

linked with both Calibre nmDRC and Calibre xRC to deliver production-proven device

extraction for both physical verification and parasitic extraction. Calibre nmLVS performs a vital

32

function as a member of a complete IC verification tool suite by providing device and

connectivity comparisons between the IC layout and the schematic. Calibre's hierarchical

processing engine runs Calibre nmLVS, supplying data for modifying the IC design to achieve

superior functionality and reliability.

ACCURATE CIRCUIT VERIFICATION

Calibre nmLVS enables accurate circuit verification because it is able to measure actual

device geometries on a full-chip for a complete accounting of physical parameters. These precise

device parameters supply the information for back-annotation to the source schematic and the

comprehensive data for running simulations. In addition to working with Calibre xRC, Calibre

nmLVS can also be used with third party parasitic extraction tools.

AUTOMATE ADVANCED, CUSTOMER-SPECIFIC ERCS

Calibre nmLVS can now be enhanced with Calibre PERC (Programmable Electrical

Rule Checker). With Calibre PERC, you can automate advanced, customer-specific ERCs to

eliminate lengthy and error-prone manual checking. PERC recognizes grouped devices that are

connected as you describe and measures geometrical data associated with the circuit topology.

AUTOMATE ADVANCED, CUSTOMER-SPECIFIC ERCS

Calibre nmLVS can now be enhanced with Calibre PERC (Programmable Electrical

Rule Checker). With Calibre PERC, you can automate advanced, customer-specific ERCs to

eliminate lengthy and error-prone manual checking. PERC recognizes grouped devices that are

connected as you describe and measures geometrical data associated with the circuit topology.

3.10 RED HAT ENTERPRISE LINUX

Red Hat Enterprise Linux (RHEL) is a Linux distribution developed by Red Hat and

targeted toward the commercial market. Red Hat Enterprise Linux is released in server versions

for x86, x86-64, Itanium, PowerPC and IBM System z, and desktop versions for x86 and x86-64.

All of the Red Hat's official support and training, together with the Red Hat Certification

33

Program, focuses on the Red Hat Enterprise Linux platform. Red Hat Enterprise Linux is often

abbreviated to RHEL, although this is not an official designation.

The first version of Red Hat Enterprise Linux to bear the name originally came onto the market

as "Red Hat Linux Advanced Server". In 2003 Red Hat rebranded Red Hat Linux Advanced

Server to "Red Hat Enterprise Linux AS", and added two more variants, Red Hat Enterprise

Linux ES and Red Hat Enterprise Linux WS.

Red Hat uses strict trademark rules to restrict free re-distribution of their officially supported

versions of Red Hat Enterprise Linux, but still freely provides its source code. Third-party

derivatives can be built and redistributed by stripping away non-free components like Red Hat's

trademarks, including community-supported distributions like CentOS and Scientific Linux, and

commercial forks like Oracle Linux, which aim to offer 100% binary compatibility with Red Hat

Enterprise Linux.

3.11 VARIANTSThere are also "Academic" editions of the Desktop and Server variants. They are offered

to schools and students, are less expensive, and are provided with Red Hat technical support as

an optional extra. Web support based on number of customer contacts can be purchased

separately.

It is often assumed the branding ES, AS, and WS stand for "Entry-level Server", "Advanced

Server" and "Work Station", respectively. The reason for this is that the ES product is indeed the

company's base enterprise server product, while AS is the more advanced product. However,

nowhere on its site or in its literature does Red Hat say what AS, ES and WS stand for. In Red

Hat Enterprise Linux 5 there are new editions that substitute former Red Hat Enterprise Linux

AS/ES/WS/Desktop:

Red Hat Enterprise Linux Advanced Platform (former AS)

Red Hat Enterprise Linux (former ES) (limited to 2 CPUs)

Red Hat Enterprise Linux Desktop with Workstation and Multi-OS option

Red Hat Enterprise Linux Desktop with Workstation option (former WS)

Red Hat Enterprise Linux Desktop with Multi-OS option

Red Hat Enterprise Linux Desktop (former Desktop)

34

Red Hat had also announced its Red Hat Global Desktop Linux edition "for emerging markets".

RHEL 4, 3, and prior releases had four variants:

Red Hat Enterprise Linux AS for mission-critical/enterprise computer systems.

Red Hat Enterprise Linux ES for supported network servers

Red Hat Enterprise Linux WS for technical power user enterprise desktops for high-

performance computing

Red Hat Desktop for multiple deployments of single-user desktops for enterprises

CHAPTER 4

IMPLEMENTATION OF T-FLIP FLOP USING CMOS

35

Fig 4.1 Transistor level of CMOS T-flip flop

Fig 4.2 CMOS T-flip flop cell symbol

36

Fig 4.3 CMOS T-flip flop new schematic cell

Fig 4.4 CMOS T-flip flop waveforms

37

Fig 4.5 CMOS T-flip flop layout

38

4.1 DRC REPORT FOR CMOS T-FLIP FLOP===================================================================================== CALIBRE::DRC-H SUMMARY REPORT===Execution Date/Time: Tue Feb 24 19:59:41 2015Calibre Version: v2012.4_25.21 Tue Dec 11 17:18:50 PST 2012Rule File Pathname: /mgc_tree/tnssprproject/cmostff/lib/cell/newlay.cal/_DRC_Rule File Title: Layout System: GDSLayout Path(s): newlay.calibre.dbLayout Primary Cell: newlayCurrent Directory: /mgc_tree/tnssprproject/cmostff/lib/cell/newlay.calUser Name: rootMaximum Results/RuleCheck: 1000Maximum Result Vertices: 4096DRC Results Database: newlay.drc.results (ASCII)Layout Depth: ALLText Depth: PRIMARYSummary Report File: newlay.drc.summary (REPLACE)Geometry Flagging: ACUTE = YES SKEW = YES ANGLED = NO OFFGRID = YES NONSIMPLE POLYGON = YES NONSIMPLE PATH = NOExcluded Cells: CheckText Mapping: ALL TEXTLayers: MEMORY-BASEDKeep Empty Checks: YES--- RULECHECK RESULTS STATISTICS (BY CELL)---CELL newlay ............ TOTAL Result Count = 1 (1) RULECHECK PO.R.2 ... TOTAL Result Count = 1 (1)------------------------------------------------------------------------------------- SUMMARY---TOTAL CPU Time: 0TOTAL REAL Time: 0TOTAL Original Layer Geometries: 1692 (1692)TOTAL DRC RuleChecks Executed: 386TOTAL DRC Results Generated: 1 (1)

39

4.2 LVS REPORT FOR CMOS T-FLIP FLOP

################################################## ## ## ## C A L I B R E S Y S T E M ## ## ## ## L V S R E P O R T ## ## ## ##################################################

REPORT FILE NAME: lvs.reportLAYOUT NAME: /mgc_tree/tnssprproject/cmostff/lib/cell/newlay.cal/lay.net ('newlay')SOURCE NAME: /mgc_tree/tnssprproject/cmostff/lib/cell/newlay.cal/newlay.calibre.src.net ('cell')RULE FILE: /mgc_tree/tnssprproject/cmostff/lib/cell/newlay.cal/_LVS_CREATION TIME: Tue Feb 24 20:00:24 2015CURRENT DIRECTORY: /mgc_tree/tnssprproject/cmostff/lib/cell/newlay.calUSER NAME: rootCALIBRE VERSION: v2012.4_25.21 Tue Dec 11 17:18:50 PST 2012

OVERALL COMPARISON RESULTS

# ################### _ _ # # # * * # # # CORRECT # | # # # # \___/ # ###################

************************************************************************************************************** CELL SUMMARY**************************************************************************************************************

Result Layout Source ----------- ----------- -------------- CORRECT newlay cell

40

************************************************************************************************************** LVS PARAMETERS**************************************************************************************************************

o LVS Setup:

// LVS COMPONENT TYPE PROPERTY // LVS COMPONENT SUBTYPE PROPERTY // LVS PIN NAME PROPERTY LVS POWER NAME "VD33" "AVDDB" "DVDD" "VDDG" "AVDDG" "AHVDD" "AVDDBG" "AHVDDB" "VDD5V" "DHVDD" "TAVDDPST" "TAVD33PST" "VDWELL" "AHVDDG" "AVDWELL" "AVDDR" "VDDSA" "TAVDD" "VDDPST" "TAVD33" "AHVDDR" "HVDDWELL" "AHVDDWELL" "VDD" "AVDD" LVS GROUND NAME "DVSS" "VSSG" "AVSSG" "AHVSS" "AVSSBG" "AHVSSB" "DHVSS" "TAVSSPST" "AHVSSG" "AVSSR" "VS33" "TAVSS" "VSSPST" "VSSUB" "AVSSUB" "AHVSSR" "GND" "AGND" "HVSSUB" "VSS" "AHVSSUB" "AVSS" "AVSSB" LVS CELL SUPPLY NO LVS RECOGNIZE GATES ALL LVS IGNORE PORTS NO LVS CHECK PORT NAMES YES LVS IGNORE TRIVIAL NAMED PORTS NO LVS BUILTIN DEVICE PIN SWAP YES LVS ALL CAPACITOR PINS SWAPPABLE YES LVS DISCARD PINS BY DEVICE NO LVS SOFT SUBSTRATE PINS NO LVS INJECT LOGIC YES LVS EXPAND UNBALANCED CELLS YES LVS FLATTEN INSIDE CELL NO LVS EXPAND SEED PROMOTIONS NO LVS PRESERVE PARAMETERIZED CELLS NO LVS GLOBALS ARE PORTS YES LVS REVERSE WL NO LVS SPICE PREFER PINS YES LVS SPICE SLASH IS SPACE YES LVS SPICE ALLOW FLOATING PINS YES // LVS SPICE ALLOW INLINE PARAMETERS LVS SPICE ALLOW UNQUOTED STRINGS NO LVS SPICE CONDITIONAL LDD NO LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO LVS SPICE IMPLIED MOS AREA NO // LVS SPICE MULTIPLIER NAME LVS SPICE OVERRIDE GLOBALS NO LVS SPICE REDEFINE PARAM NO LVS SPICE REPLICATE DEVICES NO

41

LVS SPICE SCALE X PARAMETERS NO LVS SPICE STRICT WL NO // LVS SPICE OPTION LVS STRICT SUBTYPES NO LVS EXACT SUBTYPES NO LAYOUT CASE NO SOURCE CASE NO LVS COMPARE CASE NO

LVS DOWNCASE DEVICE NO LVS REPORT MAXIMUM 50 LVS PROPERTY RESOLUTION MAXIMUM 65536 // LVS SIGNATURE MAXIMUM // LVS FILTER UNUSED OPTION // LVS REPORT OPTION LVS REPORT UNITS YES // LVS NON USER NAME PORT // LVS NON USER NAME NET // LVS NON USER NAME INSTANCE

// Reduction

LVS REDUCE SERIES MOS NO LVS REDUCE PARALLEL MOS YES LVS REDUCE SEMI SERIES MOS NO LVS REDUCE SPLIT GATES NO LVS REDUCE PARALLEL BIPOLAR YES LVS REDUCE SERIES CAPACITORS YES LVS REDUCE PARALLEL CAPACITORS YES LVS REDUCE SERIES RESISTORS YES LVS REDUCE PARALLEL RESISTORS YES LVS REDUCE PARALLEL DIODES YES LVS REDUCTION PRIORITY PARALLEL LVS SHORT EQUIVALENT NODES NO

// Trace Property

TRACE PROPERTY r(rm1) r r 0.2 TRACE PROPERTY r(rm2) r r 0.2 TRACE PROPERTY r(rm3) r r 0.2 TRACE PROPERTY r(rm4) r r 0.2 TRACE PROPERTY r(rm5) r r 0.2 TRACE PROPERTY r(rm6) r r 0.2 TRACE PROPERTY r(rm7) r r 0.2 TRACE PROPERTY r(rm8) r r 0.2 TRACE PROPERTY mimcap_g13 a a 0 TRACE PROPERTY mimcap_g13 m m 0 TRACE PROPERTY r(rndiffs) w w 0 TRACE PROPERTY r(rndiffs) l l 0 TRACE PROPERTY r(rpdiffs) w w 0 TRACE PROPERTY r(rpdiffs) l l 0 TRACE PROPERTY r(rndiffwo) w w 0

42

TRACE PROPERTY r(rndiffwo) l l 0 TRACE PROPERTY r(rpdiffwo) w w 0 TRACE PROPERTY r(rpdiffwo) l l 0 TRACE PROPERTY r(rnwod) w w 0 TRACE PROPERTY r(rnwod) l l 0 TRACE PROPERTY r(rnwsti) w w 0 TRACE PROPERTY r(rnwsti) l l 0 TRACE PROPERTY r(rnpolylo) w w 0 TRACE PROPERTY r(rnpolylo) l l 0 TRACE PROPERTY r(rppolylo) w w 0 TRACE PROPERTY r(rppolylo) l l 0 TRACE PROPERTY r(rnpolyhi) w w 0 TRACE PROPERTY r(rnpolyhi) l l 0 TRACE PROPERTY r(rppolyhi) w w 0 TRACE PROPERTY r(rppolyhi) l l 0 TRACE PROPERTY mn(nmos) l l 0

TRACE PROPERTY mn(nmos) w w 0 TRACE PROPERTY mn(nmos_na) l l 0 TRACE PROPERTY mn(nmos_na) w w 0 TRACE PROPERTY mn(nmos_lvt) l l 0 TRACE PROPERTY mn(nmos_lvt) w w 0 TRACE PROPERTY mn(nmos_hvt) l l 0 TRACE PROPERTY mn(nmos_hvt) w w 0 TRACE PROPERTY mn(nmos_33) l l 0 TRACE PROPERTY mn(nmos_33) w w 0 TRACE PROPERTY mn(nmos_na33) l l 0 TRACE PROPERTY mn(nmos_na33) w w 0 TRACE PROPERTY mp(pmos) l l 0 TRACE PROPERTY mp(pmos) w w 0 TRACE PROPERTY mp(pmos_lvt) l l 0 TRACE PROPERTY mp(pmos_lvt) w w 0 TRACE PROPERTY mp(pmos_hvt) l l 0 TRACE PROPERTY mp(pmos_hvt) w w 0 TRACE PROPERTY mp(pmos_33) l l 0 TRACE PROPERTY mp(pmos_33) w w 0 TRACE PROPERTY d(ndiode) a a 0.5 TRACE PROPERTY d(ndiode_33) a a 0.5 TRACE PROPERTY d(pdiode) a a 0.5 TRACE PROPERTY d(pdiode_33) a a 0.5 TRACE PROPERTY d(nwdiode) a a 0.5 TRACE PROPERTY c(nmosvar) lr lr 0 TRACE PROPERTY c(nmosvar) wr wr 0 TRACE PROPERTY mp(pmos_rf25) rl rl 0 TRACE PROPERTY mp(pmos_rf25) nr nr 0 TRACE PROPERTY mp(pmos_rf) rl rl 0 TRACE PROPERTY mp(pmos_rf) nr nr 0 TRACE PROPERTY mn(nmos_rf) nr nr 0 TRACE PROPERTY mn(nmos_rf25) nr nr 0 TRACE PROPERTY c(moscap_rf) nr nr 0 TRACE PROPERTY c(moscap_rf25) nr nr 0 TRACE PROPERTY c(mimcap) lt lt 0 TRACE PROPERTY c(xjvar) nr nr 0

43

TRACE PROPERTY spiral_inductor_lvs nr nr 0

CELL COMPARISON RESULTS ( TOP LEVEL )

# ################### _ _ # # # * * # # # CORRECT # | # # # # \___/ # ###################

LAYOUT CELL NAME: newlaySOURCE CELL NAME: cell

--------------------------------------------------------------------------------------------------------------

INITIAL NUMBERS OF OBJECTS

--------------------------

Layout Source Component Type ------ ------ -------------- Ports: 6 6

Nets: 27 27

Instances: 23 23 MN (4 pins) 23 23 MP (4 pins) ------ ------ Total Inst: 46 46

NUMBERS OF OBJECTS AFTER TRANSFORMATION---------------------------------------

Layout Source Component Type ------ ------ -------------- Ports: 6 6

Nets: 17 17

Instances: 2 2 MP (4 pins) 2 2 SPMN_2_1 (5 pins) 5 5 _invv (4 pins) 2 2 _nand2v (5 pins)

44

4 4 _nor2v (5 pins) 2 2 _smp2v (4 pins) ------ ------ Total Inst: 17 17

************************************************************************************************************** INFORMATION AND WARNINGS**************************************************************************************************************

Matched Matched Unmatched Unmatched Component Layout Source Layout Source Type ------- ------- --------- --------- --------- Ports: 6 6 0 0

Nets: 17 17 0 0

Instances: 2 2 0 0 MP(PMOS) 2 2 0 0 SPMN_2_1 5 5 0 0 _invv 2 2 0 0 _nand2v 4 4 0 0 _nor2v 2 2 0 0 _smp2v

------- ------- --------- ---------

Total Inst: 17 17 0 0

o Initial Correspondence Points:

Ports: VDD GROUND Q QBAR CLK T

************************************************************************************************************** SUMMARY**************************************************************************************************************

Total CPU Time: 0 secTotal Elapsed Time: 0 sec

45

4.3 PEX NETLIST FOR CMOS T-FLIP FLOP* File: newlay.pex.netlist* Created: Tue Feb 24 20:02:25 2015* Program "Calibre xRC"* Version "v2012.4_25.21"* .global VDD VSS .include "newlay.pex.netlist.pex".subckt newlay GROUND Q QBAR CLK T* * T T* CLK CLK* QBAR QBAR* Q Q* GROUND GROUND* VDD VDDM0 N_3_M0_d N_CLK_M0_g N_2_M0_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M1 N_2_M1_d N_Q_M1_g N_GROUND_M1_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M2 N_6_M2_d N_QBAR_M2_g N_5_M2_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M3 N_3_M3_d N_T_M3_g N_2_M3_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M4 N_5_M4_d N_CLK_M4_g N_GROUND_M4_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M5 N_6_M5_d N_T_M5_g N_5_M5_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M6 N_7_M6_d N_6_M6_g N_GROUND_M6_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M7 N_8_M7_d N_7_M7_g N_GROUND_M7_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M8 N_8_M8_d N_13_M8_g N_GROUND_M8_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M9 N_9_M9_d N_CLK_M9_g N_GROUND_M9_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M10 N_10_M10_d N_3_M10_g N_GROUND_M10_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M11 N_12_M11_d N_8_M11_g N_11_M11_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M12 N_11_M12_d N_9_M12_g N_GROUND_M12_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M13 N_13_M13_d N_8_M13_g N_GROUND_M13_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M14 N_14_M14_d N_12_M14_g N_GROUND_M14_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M15 N_13_M15_d N_10_M15_g N_GROUND_M15_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M16 N_Q_M16_d N_14_M16_g N_GROUND_M16_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06

M17 N_Q_M17_d N_QBAR_M17_g N_GROUND_M17_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M18 N_17_M18_d N_9_M18_g N_16_M18_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M19 N_16_M19_d N_13_M19_g N_GROUND_M19_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M20 N_18_M20_d N_17_M20_g N_GROUND_M20_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M21 N_QBAR_M21_d N_Q_M21_g N_GROUND_M21_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M22 N_QBAR_M22_d N_18_M22_g N_GROUND_M22_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M23 N_3_M23_d N_T_M23_g N_20_M23_s N_VDD_M23_b PMOS L=1.3e-07 W=2e-06

46

M24 N_20_M24_d N_CLK_M24_g N_VDD_M24_s N_VDD_M23_b PMOS L=1.3e-07 W=2e-06M25 N_3_M25_d N_Q_M25_g N_VDD_M25_s N_VDD_M23_b PMOS L=1.3e-07 W=2e-06M26 N_21_M26_d N_QBAR_M26_g N_VDD_M26_s N_VDD_M23_b PMOS L=1.3e-07 W=2e-06M27 N_6_M27_d N_T_M27_g N_21_M27_s N_VDD_M23_b PMOS L=1.3e-07 W=2e-06M28 N_6_M28_d N_CLK_M28_g N_VDD_M28_s N_VDD_M23_b PMOS L=1.3e-07 W=2e-06M29 N_7_M29_d N_6_M29_g N_VDD_M29_s N_VDD_M23_b PMOS L=1.3e-07 W=2e-06M30 N_22_M30_d N_7_M30_g N_VDD_M30_s N_VDD_M23_b PMOS L=1.3e-07 W=2e-06M31 N_8_M31_d N_13_M31_g N_22_M31_s N_VDD_M23_b PMOS L=1.3e-07 W=2e-06M32 N_10_M32_d N_3_M32_g N_VDD_M32_s N_VDD_M32_b PMOS L=1.3e-07 W=2e-06M33 N_9_M33_d N_CLK_M33_g N_VDD_M33_s N_VDD_M32_b PMOS L=1.3e-07 W=2e-06M34 N_12_M34_d N_8_M34_g N_VDD_M34_s N_VDD_M23_b PMOS L=1.3e-07 W=2e-06M35 N_12_M35_d N_9_M35_g N_VDD_M35_s N_VDD_M23_b PMOS L=1.3e-07 W=2e-06M36 N_23_M36_d N_8_M36_g N_VDD_M36_s N_VDD_M32_b PMOS L=1.3e-07 W=2e-06M37 N_13_M37_d N_10_M37_g N_23_M37_s N_VDD_M37_b PMOS L=1.3e-07 W=2e-06M38 N_14_M38_d N_12_M38_g N_VDD_M38_s N_VDD_M23_b PMOS L=1.3e-07 W=2e-06M39 N_24_M39_d N_14_M39_g N_VDD_M39_s N_VDD_M23_b PMOS L=1.3e-07 W=2e-06M40 N_Q_M40_d N_QBAR_M40_g N_24_M40_s N_VDD_M40_b PMOS L=1.3e-07 W=2e-06M41 N_17_M41_d N_9_M41_g N_VDD_M41_s N_VDD_M41_b PMOS L=1.3e-07 W=2e-06M42 N_17_M42_d N_13_M42_g N_VDD_M42_s N_VDD_M41_b PMOS L=1.3e-07 W=2e-06M43 N_18_M43_d N_17_M43_g N_VDD_M43_s N_VDD_M41_b PMOS L=1.3e-07 W=2e-06M44 N_QBAR_M44_d N_18_M44_g N_25_M44_s N_VDD_M41_b PMOS L=1.3e-07 W=2e-06M45 N_25_M45_d N_Q_M45_g N_VDD_M45_s N_VDD_M41_b PMOS L=1.3e-07 W=2e-06*.include "newlay.pex.netlist.NEWLAY.pxi"*.ends….

47

4.4 EXTRACTION REPORT FOR CMOS T-FLIP FLOP

############################################################# ## ## ## C A L I B R E S Y S T E M ## ## ## ## C I R C U I T E X T R A C T I O N R E P O R T ## ## ## #############################################################

REPORT FILE NAME: lvs.report.extLAYOUT NAME: newlay.calibre.gds ('newlay')

CREATION TIME: Tue Feb 24 20:00:23 2015CURRENT DIRECTORY: /mgc_tree/tnssprproject/cmostff/lib/cell/newlay.calUSER NAME: rootCALIBRE VERSION: v2012.4_25.21 Tue Dec 11 17:18:50 PST 2012

WARNING: Invalid PATHCHK request "GROUND && ! POWER": no GROUND nets present, operation aborted.

WARNING: Invalid PATHCHK request "POWER && ! GROUND": no GROUND nets present, operation aborted.

WARNING: Invalid PATHCHK request "! POWER && ! GROUND": no GROUND nets present, operation aborted.

48

4.5 PARASITICS FOR CMOS T-FLIP FLOP

Fig: 4.6 CMOS T-flip flop parasitic

4.6 POWER DISSIPATION FOR CMOS T-FLIP FLOP:

// Invocation args: -check -upper -ground_nodes:GROUND -eldo -o $CMOSTFF/newlib/newcell/default/netlist.spi -log /mgc_tree/tnssprproject/cmostff/newlib/newcell/default/netlist_transcript -quiet $CMOSTFF/newlib/newcell/default

// **** Reading <$CMOSTFF/newlib/newcell/default> for ELDO netlist ****

// Checking 2 sheet(s) for out of date references to symbols and interfaces...// Done.// Parsing file '/mgc_tree/pyxis/v10.2_rhelx86linux/pyxis_home/mgc_icstd_lib/global.ncf' succeeded.// Parsing file '/mgc_tree/design_data/new_pdk/PDK/generic13/symbols/pmos/@ncf.dir/pmos.ncf' succeeded.

49

// Parsing file '/mgc_tree/design_data/new_pdk/PDK/generic13/symbols/nmos/@ncf.dir/nmos.ncf' succeeded.// NOTE: There is no part interface for the top level schematic. The external nets in the schematic// are being scanned to create the pin names for the top level subckt.

Processing [$CMOSTFF/newlib/newcell] [newcell/newcell] [newschematic] (NCF entry line: 17 file: $NCF_GLOBAL)Processing [$CMOSTFF/lib/cell] [[#2]/cell] [schematic] (NCF entry line: 17 file: $NCF_GLOBAL)Primitive [$GENERIC13/symbols/nmos] [nmos/nmos] [ELDOSPICE=M] (NCF entry line: 19 file: $GENERIC13/symbols/nmos/@ncf.dir/nmos.ncf)Primitive [$GENERIC13/symbols/pmos] [pmos/pmos] [ELDOSPICE=M] (NCF entry line: 19 file: $GENERIC13/symbols/pmos/@ncf.dir/pmos.ncf)Primitive [$MGC_IC_SOURCES_LIB/pulse_v_source] [pulse_v_source/pulse_v_source] [SPICE=V] (NCF entry line: 754 file: $NCF_GLOBAL)Primitive [$MGC_IC_SOURCES_LIB/voltage_source] [voltage_source/voltage_source] [SPICE=V] (NCF entry line: 519 file: $NCF_GLOBAL)

**** Writing <$CMOSTFF/newlib/newcell/default> netlist for ELDO ****

Number of cells: 6Number of primitive instances: 49

Done...

Running eldo on localhost.localdomainwith Eldo libraries :/mgc_tree/AMS/aol/lib/libeldoudm_64.so/mgc_tree/AMS/aol/lib/libeldomos1_64.so/mgc_tree/AMS/aol/lib/libeldoekv_64.so/mgc_tree/AMS/aol/lib/libeldomosp9_64.so/mgc_tree/AMS/aol/lib/libeldocsem_64.so/mgc_tree/AMS/aol/lib/libeldomos2_64.so/mgc_tree/AMS/aol/lib/libeldomos3_64.so/mgc_tree/AMS/aol/lib/libeldobip_64.so/mgc_tree/AMS/aol/lib/libeldodio_64.so

/mgc_tree/AMS/aol/lib/libeldojfet_64.so/mgc_tree/AMS/aol/lib/libeldosoi_64.so/mgc_tree/AMS/aol/lib/libeldomos4_64.so/mgc_tree/AMS/aol/lib/libeldoasitft_64.so/mgc_tree/AMS/aol/lib/libeldohisim_64.so/mgc_tree/AMS/aol/lib/libeldospmod_64.so/mgc_tree/AMS/aol/lib/libeldopsp_64.so/mgc_tree/AMS/aol/lib/libeldomosvar_64.so/mgc_tree/AMS/aol/lib/libeldolegtft_64.so/mgc_tree/AMS/aol/lib/libeldomoto_64.so/mgc_tree/AMS/aol/lib/libeldost_64.so

50

/mgc_tree/AMS/aol/lib/libeldobnr_64.so/mgc_tree/AMS/aol/lib/libeldorockw_64.so/mgc_tree/AMS/aol/lib/libeldopubhicum_64.so/mgc_tree/AMS/aol/lib/libeldotftsh_64.so/mgc_tree/AMS/aol/lib/libeldobta_64.so/mgc_tree/AMS/aol/lib/libeldofas_64.so/mgc_tree/AMS/aol/lib/libeldofascm_64.so/mgc_tree/AMS/aol/lib/libeldosdsim_64.so/mgc_tree/AMS/aol/lib/libeldowire_64.so/mgc_tree/AMS/aol/lib/libogr_64.so loaded.

Copyright 1988 Mentor Graphics CorporationAll Rights Reserved

THIS WORK CONTAINS TRADE SECRET AND PROPRIETARYINFORMATION WHICH ARE THE PROPERTY OF MENTORGRAPHICS CORPORATION OR ITS LICENSORS AND ISSUBJECT TO LICENSE TERMS.

***** SYSTEM INFORMATION ...

*** User : unknown@localhost.localdomain*** OS : Red Hat Enterprise Linux Server release 5.9 (Tikanga) [VCO = aol]*** CPU : Pentium(R) Dual-Core CPU E5500 @ 2.80GHz Number of physical processors : 1 Hyper-Threading Technology : disabled Number of cpu cores : 2 Number of logical processors : 2*** Freq : 1200.000MHz*** Cache : 2048 KB*** MEM : 973644 kB*** Date : Thu Feb 26 17:28:06 2015

***** PRE-PROCESSING ...

***** ANALYSIS ....

***** 0 error(s).

***** 0 warning(s).

***** GENERATION ...

51

***** 0 error(s). ***** 0 warning(s).

INFORMATION ABOUT COMPILATION...

Memory space allocated (MB): 25749 elements26 nodes3 input signals

***> Parsing CPU TIME 0h 0mn 0s 050ms <***

Eldo VERSION : ELDO 14.1 (64 bits) Fri Jul 4 10:16:17 GMT 2014

*** DATE: 26-Feb-2015 17:28:08

*** TITLE: * Component: $CMOSTFF/newlib/newcell Viewpoint: default

TEMPERATURE : 27.000000 degrees C

Performing DC analysis...

--> Partitioning circuit...

***> DC CPU TIME 0s 010ms <***

DC:10 iterations FOR DC analysisCLK 0.0000 Q 10.1685N QBAR 5.0000 T 0.0000 VDD 5.0000 X_CELL1.N$101 2.8931U X_CELL1.N$103 1.4466U X_CELL1.N$12 5.0000 X_CELL1.N$120 5.0000 X_CELL1.N$130 5.0000 X_CELL1.N$132 4.3652 X_CELL1.N$136 723.1012N X_CELL1.N$141 4.9038 X_CELL1.N$147 5.0000 X_CELL1.N$153 5.0000 X_CELL1.N$23 723.1012N X_CELL1.N$45 5.0000 X_CELL1.N$55 4.3652 X_CELL1.N$57 5.0000 X_CELL1.N$59 130.8306M X_CELL1.N$63 5.0000

52

X_CELL1.N$65 723.0446N X_CELL1.N$69 5.0000 X_CELL1.N$78 435.6477N X_CELL1.N$89 693.3957M X_CELL1.N$91 5.0000

TOTAL POWER DISSIPATION: 471.8403N WATTS

Eldo NEWTON: VNTOL=1.000000e-06 RELTOL=1.000000e-03

Connecting to JWDB server, please wait...connected to wdb server : -jwdbhost localhost.localdomain -jwdbport 53567

Compute from 0.000000 Nano to 600.000000 Nano................................................Simulation progress : 10% (t = 61.4319 N)Elapsed CPU time : 0h 0mn 0s 30 ( 0h 0mn 0s 30)CPU Usage : 40% ( 40%)

................................................Simulation progress : 20% (t = 121.0000 N)Elapsed CPU time : 0h 0mn 0s 10 ( 0h 0mn 0s 40)CPU Usage : 76% ( 45%)................................................Simulation progress : 30% (t = 182.2978 N)Elapsed CPU time : 0h 0mn 0s 10 ( 0h 0mn 0s 60)CPU Usage : 52% ( 56%)................................................Simulation progress : 40% (t = 242.5731 N)Elapsed CPU time : 0h 0mn 0s 20 ( 0h 0mn 0s 80)CPU Usage : 100% ( 66%)................................................Simulation progress : 50% (t = 300.0000 N)Elapsed CPU time : 0h 0mn 0s 10 ( 0h 0mn 0s 90)CPU Usage : 71% ( 66%)................................................Simulation progress : 60% (t = 361.4319 N)Elapsed CPU time : 0h 0mn 0s 20 ( 0h 0mn 0s 110)CPU Usage : 86% ( 69%)................................................Simulation progress : 70% (t = 421.0000 N)Elapsed CPU time : 0h 0mn 0s 10 ( 0h 0mn 0s 120)CPU Usage : 76% ( 70%)................................................Simulation progress : 80% (t = 482.2978 N)Elapsed CPU time : 0h 0mn 0s 20 ( 0h 0mn 0s 140)CPU Usage : 100% ( 76%)................................................Simulation progress : 90% (t = 542.5731 N)Elapsed CPU time : 0h 0mn 0s 0 ( 0h 0mn 0s 140)CPU Usage : 0% ( 74%)

53

................................................Simulation progress : 100% (t = 600.0000 N)Elapsed CPU time : 0h 0mn 0s 10 ( 0h 0mn 0s 150)CPU Usage : 100% ( 76%)

***>Current simulation completed

SIMULATION INFORMATION memory size allocated in Mbytes 259.9Latency: 0.000000%average number of newton iterations: 2.393822nb of components: 49nb of nodes: 118nb of MOS or BIP calls: 7508Number of steps computed: 259

***>CPU TIME 0s 150ms <***

***>GLOBAL CPU TIME 0s 260ms <***

***>GLOBAL ELAPSED TIME 6s <***

54

CHAPTER 5

IMPLEMENTATION OF T FLIP FLOP USING GDI

Fig: 5.1 Transistor level of GDI T-flip flop

Fig: 5.2 GDI T-flip flop cell symbol

55

Fig: 5.3 GDI T-flip flop schematic cell

Fig: 5.4 GDI T-flip flop waveform

56

Fig: 5.5 GDI T-flip flop layout

57

5.1 DRC REPORT FOR GDI T- FLIP FLOP

===================================================================================== CALIBRE::DRC-H SUMMARY REPORT===Execution Date/Time: Thu Feb 19 19:26:57 2015Calibre Version: v2012.4_25.21 Tue Dec 11 17:18:50 PST 2012Rule File Pathname: /mgc_tree/rajkiran/tff/L1/C1/l3.cal/_DRC_Rule File Title: Layout System: GDSLayout Path(s): l3.calibre.dbLayout Primary Cell: l3Current Directory: /mgc_tree/rajkiran/tff/L1/C1/l3.calUser Name: rootMaximum Results/RuleCheck: 1000Maximum Result Vertices: 4096DRC Results Database: l3.drc.results (ASCII)Layout Depth: ALLText Depth: PRIMARYSummary Report File: l3.drc.summary (REPLACE)Geometry Flagging: ACUTE = YES SKEW = YES ANGLED = NO OFFGRID = YES NONSIMPLE POLYGON = YES NONSIMPLE PATH = NOExcluded Cells: CheckText Mapping: ALL TEXTLayers: MEMORY-BASEDKeep Empty Checks: YES------------------------------------------------------------------------------------- RULECHECK RESULTS STATISTICS (BY CELL)---CELL l3 ................ TOTAL Result Count = 1 (1) RULECHECK PO.R.2 ... TOTAL Result Count = 1 (1)------------------------------------------------------------------------------------- SUMMARY---TOTAL CPU Time: 0TOTAL REAL Time: 0TOTAL Original Layer Geometries: 792 (792)TOTAL DRC RuleChecks Executed: 386TOTAL DRC Results Generated: 1 (1)

58

5.2 LVS REPORT FOR GDI T-FLIP FLOP

################################################## ## ## ## C A L I B R E S Y S T E M ## ## ## ## L V S R E P O R T ## ## ## ##################################################

REPORT FILE NAME: lvs.reportLAYOUT NAME: /mgc_tree/rajkiran/tff/L1/C1/l3.cal/lay.net ('l3')SOURCE NAME: /mgc_tree/rajkiran/tff/L1/C1/l3.cal/l3.calibre.src.net ('C1')RULE FILE: /mgc_tree/rajkiran/tff/L1/C1/l3.cal/_LVS_CREATION TIME: Thu Feb 19 19:26:06 2015CURRENT DIRECTORY: /mgc_tree/rajkiran/tff/L1/C1/l3.calUSER NAME: rootCALIBRE VERSION: v2012.4_25.21 Tue Dec 11 17:18:50 PST 2012

OVERALL COMPARISON RESULTS

# ################### _ _ # # # * * # # # CORRECT # | # # # # \___/ # ###################

************************************************************************************************************** CELL SUMMARY**************************************************************************************************************

Result Layout Source ----------- ----------- -------------- CORRECT l3 C1

59

************************************************************************************************************** LVS PARAMETERS**************************************************************************************************************

o LVS Setup:

// LVS COMPONENT TYPE PROPERTY // LVS COMPONENT SUBTYPE PROPERTY // LVS PIN NAME PROPERTY LVS POWER NAME "VD33" "AVDDB" "DVDD" "VDDG" "AVDDG" "AHVDD" "AVDDBG" "AHVDDB" "VDD5V" "DHVDD" "TAVDDPST" "TAVD33PST" "VDWELL" "AHVDDG" "AVDWELL" "AVDDR" "VDDSA" "TAVDD" "VDDPST" "TAVD33" "AHVDDR" "HVDDWELL" "AHVDDWELL" "VDD" "AVDD" LVS GROUND NAME "DVSS" "VSSG" "AVSSG" "AHVSS" "AVSSUB" "AHVSSR" "GND" "AGND" "HVSSUB" "VSS" "AHVSSUB" "AVSS" "AVSSB" LVS CELL SUPPLY NO LVS RECOGNIZE GATES ALL LVS IGNORE PORTS NO LVS CHECK PORT NAMES YES LVS IGNORE TRIVIAL NAMED PORTS NO LVS BUILTIN DEVICE PIN SWAP YES LVS ALL CAPACITOR PINS SWAPPABLE YES LVS DISCARD PINS BY DEVICE NO LVS SOFT SUBSTRATE PINS NO LVS INJECT LOGIC YES LVS EXPAND UNBALANCED CELLS YES LVS FLATTEN INSIDE CELL NO LVS EXPAND SEED PROMOTIONS NO LVS PRESERVE PARAMETERIZED CELLS NO LVS GLOBALS ARE PORTS YES LVS REVERSE WL NO LVS SPICE PREFER PINS YES LVS SPICE SLASH IS SPACE YES LVS SPICE ALLOW FLOATING PINS YES // LVS SPICE ALLOW INLINE PARAMETERS LVS SPICE ALLOW UNQUOTED STRINGS NO LVS SPICE CONDITIONAL LDD NO LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO LVS SPICE IMPLIED MOS AREA NO // LVS SPICE MULTIPLIER NAME LVS SPICE OVERRIDE GLOBALS NO LVS SPICE REDEFINE PARAM NO LVS SPICE REPLICATE DEVICES NO LVS SPICE SCALE X PARAMETERS NO LVS SPICE STRICT WL NO // LVS SPICE OPTION LVS STRICT SUBTYPES NO LVS EXACT SUBTYPES NO

60

LAYOUT CASE NO SOURCE CASE NO LVS COMPARE CASE NO LVS DOWNCASE DEVICE NO LVS REPORT MAXIMUM 50 LVS PROPERTY RESOLUTION MAXIMUM 65536 // LVS SIGNATURE MAXIMUM LVS REPORT UNITS YES // LVS NON USER NAME PORT // LVS NON USER NAME NET // LVS NON USER NAME INSTANCE

// Reduction

LVS REDUCE SERIES MOS NO LVS REDUCE PARALLEL MOS YES LVS REDUCE SEMI SERIES MOS NO LVS REDUCE SPLIT GATES NO LVS REDUCE PARALLEL BIPOLAR YES LVS REDUCE SERIES CAPACITORS YES LVS REDUCE PARALLEL CAPACITORS YES LVS REDUCE SERIES RESISTORS YES LVS REDUCE PARALLEL RESISTORS YES LVS REDUCE PARALLEL DIODES YES LVS REDUCTION PRIORITY PARALLEL LVS SHORT EQUIVALENT NODES NO

// Trace Property

TRACE PROPERTY r(rm1) r r 0.2 TRACE PROPERTY r(rm2) r r 0.2 TRACE PROPERTY r(rm3) r r 0.2 TRACE PROPERTY r(rm4) r r 0.2 TRACE PROPERTY r(rm5) r r 0.2 TRACE PROPERTY r(rm6) r r 0.2 TRACE PROPERTY r(rm7) r r 0.2 TRACE PROPERTY r(rm8) r r 0.2 TRACE PROPERTY mimcap_g13 a a 0 TRACE PROPERTY mimcap_g13 m m 0 TRACE PROPERTY r(rndiffs) w w 0 TRACE PROPERTY r(rndiffs) l l 0 TRACE PROPERTY r(rpdiffs) w w 0 TRACE PROPERTY r(rpdiffs) l l 0 TRACE PROPERTY r(rndiffwo) w w 0 TRACE PROPERTY r(rndiffwo) l l 0 TRACE PROPERTY r(rpdiffwo) w w 0 TRACE PROPERTY r(rpdiffwo) l l 0 TRACE PROPERTY r(rnwod) w w 0 TRACE PROPERTY r(rnwod) l l 0 TRACE PROPERTY r(rnwsti) w w 0 TRACE PROPERTY r(rnwsti) l l 0 TRACE PROPERTY r(rnpolylo) w w 0

61

TRACE PROPERTY r(rnpolylo) l l 0 TRACE PROPERTY r(rppolylo) w w 0 TRACE PROPERTY r(rppolylo) l l 0 TRACE PROPERTY r(rnpolyhi) w w 0 TRACE PROPERTY r(rnpolyhi) l l 0 TRACE PROPERTY r(rppolyhi) w w 0 TRACE PROPERTY r(rppolyhi) l l 0 TRACE PROPERTY mn(nmos) l l 0 TRACE PROPERTY mn(nmos) w w 0 TRACE PROPERTY mn(nmos_na) l l 0 TRACE PROPERTY mn(nmos_na) w w 0 TRACE PROPERTY mn(nmos_lvt) l l 0 TRACE PROPERTY mn(nmos_lvt) w w 0 TRACE PROPERTY mn(nmos_hvt) l l 0 TRACE PROPERTY mn(nmos_hvt) w w 0 TRACE PROPERTY mn(nmos_33) l l 0 TRACE PROPERTY mn(nmos_33) w w 0 TRACE PROPERTY mn(nmos_na33) l l 0 TRACE PROPERTY mn(nmos_na33) w w 0 TRACE PROPERTY mp(pmos) l l 0 TRACE PROPERTY mp(pmos) w w 0 TRACE PROPERTY mp(pmos_lvt) l l 0 TRACE PROPERTY mp(pmos_lvt) w w 0 TRACE PROPERTY mp(pmos_hvt) l l 0 TRACE PROPERTY mp(pmos_hvt) w w 0 TRACE PROPERTY mp(pmos_33) l l 0 TRACE PROPERTY mp(pmos_33) w w 0 TRACE PROPERTY d(ndiode) a a 0.5 TRACE PROPERTY d(ndiode_33) a a 0.5 TRACE PROPERTY d(pdiode) a a 0.5 TRACE PROPERTY d(pdiode_33) a a 0.5 TRACE PROPERTY d(nwdiode) a a 0.5 TRACE PROPERTY c(nmosvar) lr lr 0 TRACE PROPERTY c(nmosvar) wr wr 0 TRACE PROPERTY mp(pmos_rf25) rl rl 0 TRACE PROPERTY mp(pmos_rf25) nr nr 0 TRACE PROPERTY mp(pmos_rf) rl rl 0 TRACE PROPERTY mp(pmos_rf) nr nr 0 TRACE PROPERTY mn(nmos_rf) nr nr 0 TRACE PROPERTY mn(nmos_rf25) nr nr 0 TRACE PROPERTY c(moscap_rf) nr nr 0 TRACE PROPERTY c(moscap_rf25) nr nr 0 TRACE PROPERTY c(mimcap) lt lt 0 TRACE PROPERTY c(xjvar) nr nr 0 TRACE PROPERTY spiral_inductor_lvs nr nr 0

CELL COMPARISON RESULTS ( TOP LEVEL )

62

# ################### _ _ # # # * * # # # CORRECT # | # # # # \___/ # ###################

LAYOUT CELL NAME: l3SOURCE CELL NAME: C1

--------------------------------------------------------------------------------------------------------------

INITIAL NUMBERS OF OBJECTS--------------------------

Layout Source Component Type ------ ------ -------------- Ports: 6 6

Nets: 15 15

Instances: 11 11 MN (4 pins) 11 11 MP (4 pins) ------ ------ Total Inst: 22 22

NUMBERS OF OBJECTS AFTER TRANSFORMATION---------------------------------------

Layout Source Component Type ------ ------ -------------- Ports: 6 6

Nets: 15 15

Instances: 5 5 _invb (6 pins) 6 6 _invv (4 pins) ------ ------ Total Inst: 11 11

INFORMATION AND WARNINGS**************************************************************************************************************

Matched Matched Unmatched Unmatched Component Layout Source Layout Source Type ------- ------- --------- --------- --------- Ports: 6 6 0 0

63

Nets: 15 15 0 0

Instances: 5 5 0 0 _invb 6 6 0 0 _invv ------- ------- --------- --------- Total Inst: 11 11 0 0

o Initial Correspondence Points:

Ports: VDD GROUND QBAR Q T CLK

SUMMARY**************************************************************************************************************

Total CPU Time: 0 secTotal Elapsed Time: 0 sec

64

5.3 PEX NETLIST FOR GDI T-FLIP FLOP* File: l3.pex.netlist* Created: Thu Feb 19 19:42:16 2015* Program "Calibre xRC"* Version "v2012.4_25.21"* .global VDD VSS .include "l3.pex.netlist.pex".subckt l3 GROUND QBAR Q T CLK* * CLK CLK* T T* Q Q* QBAR QBAR* GROUND GROUND* VDD VDDM0 N_3_M0_d N_Q_M0_g N_GROUND_M0_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M1 N_4_M1_d N_T_M1_g N_3_M1_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M2 N_5_M2_d N_4_M2_g N_GROUND_M2_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M3 N_6_M3_d N_9_M3_g N_GROUND_M3_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M4 N_7_M4_d N_CLK_M4_g N_6_M4_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M5 N_9_M5_d N_CLK_M5_g N_8_M5_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M6 N_8_M6_d N_7_M6_g N_GROUND_M6_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M7 N_11_M7_d N_CLK_M7_g N_QBAR_M7_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M8 N_QBAR_M8_d N_13_M8_g N_GROUND_M8_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M9 N_Q_M9_d N_11_M9_g N_GROUND_M9_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M10 N_13_M10_d N_CLK_M10_g N_Q_M10_s N_GROUND_M0_b NMOS L=1.3e-07 W=2e-06M11 N_3_M11_d N_Q_M11_g N_VDD_M11_s N_VDD_M11_b PMOS L=1.3e-07 W=2e-06M12 N_4_M12_d N_T_M12_g N_Q_M12_s N_VDD_M11_b PMOS L=1.3e-07 W=2e-06M13 N_5_M13_d N_4_M13_g N_VDD_M13_s N_VDD_M11_b PMOS L=1.3e-07 W=2e-06M14 N_6_M14_d N_9_M14_g N_VDD_M14_s N_VDD_M14_b PMOS L=1.3e-07 W=2e-06M15 N_7_M15_d N_CLK_M15_g N_5_M15_s N_VDD_M11_b PMOS L=1.3e-07 W=2e-06M16 N_9_M16_d N_CLK_M16_g N_4_M16_s N_VDD_M11_b PMOS L=1.3e-07 W=2e-06M17 N_8_M17_d N_7_M17_g N_VDD_M17_s N_VDD_M11_b PMOS L=1.3e-07 W=2e-06M18 N_11_M18_d N_CLK_M18_g N_6_M18_s N_VDD_M11_b PMOS L=1.3e-07 W=2e-06M19 N_QBAR_M19_d N_13_M19_g N_VDD_M19_s N_VDD_M11_b PMOS L=1.3e-07 W=2e-06M20 N_Q_M20_d N_11_M20_g N_VDD_M20_s N_VDD_M11_b PMOS L=1.3e-07 W=2e-06M21 N_13_M21_d N_CLK_M21_g N_8_M21_s N_VDD_M21_b PMOS L=1.3e-07 W=2e-06*.include "l3.pex.netlist.L3.pxi"*.ends**

65

5.4 POWER DISSIPATION FOR GDI T-FLIP FLOP// Invocation args: -check -upper -ground_nodes:GROUND -eldo -o $T_FF/newlib/newcell/default/netlist.spi -log /mgc_tree/tnsspramod/t-ff/newlib/newcell/default/netlist_transcript -quiet $T_FF/newlib/newcell/default

// **** Reading <$T_FF/newlib/newcell/default> for ELDO netlist ****

// Checking 2 sheet(s) for out of date references to symbols and interfaces...// Done.// Parsing file '/mgc_tree/pyxis/v10.2_rhelx86linux/pyxis_home/mgc_icstd_lib/global.ncf' succeeded.// Parsing file '/mgc_tree/new_pdk/PDK/generic13/symbols/pmos/@ncf.dir/pmos.ncf' succeeded.// Parsing file '/mgc_tree/new_pdk/PDK/generic13/symbols/nmos/@ncf.dir/nmos.ncf' succeeded.// NOTE: There is no part interface for the top level schematic. The external nets in the schematic// are being scanned to create the pin names for the top level subckt.Processing [$T_FF/newlib/newcell] [newcell/newcell] [newschematic] (NCF entry line: 17 file: $NCF_GLOBAL)Processing [$T_FF/lib/cell] [cell/cell] [schematic] (NCF entry line: 17 file: $NCF_GLOBAL)Primitive [$GENERIC13/symbols/nmos] [nmos/nmos] [ELDOSPICE=M] (NCF entry line: 19 file: $GENERIC13/symbols/nmos/@ncf.dir/nmos.ncf)Primitive [$GENERIC13/symbols/pmos] [pmos/pmos] [ELDOSPICE=M] (NCF entry line: 19 file: $GENERIC13/symbols/pmos/@ncf.dir/pmos.ncf)Primitive [$MGC_IC_SOURCES_LIB/pulse_v_source] [pulse_v_source/pulse_v_source] [SPICE=V] (NCF entry line: 754 file: $NCF_GLOBAL)Primitive [$MGC_IC_SOURCES_LIB/voltage_source] [voltage_source/voltage_source] [SPICE=V] (NCF entry line: 519 file: $NCF_GLOBAL)

**** Writing <$T_FF/newlib/newcell/default> netlist for ELDO ****

Number of cells: 6Number of primitive instances: 25

Done...

Running eldo on localhost.localdomainwith Eldo libraries :/mgc_tree/AMS/aol/lib/libeldoudm_64.so/mgc_tree/AMS/aol/lib/libeldomos1_64.so/mgc_tree/AMS/aol/lib/libeldoekv_64.so/mgc_tree/AMS/aol/lib/libeldomosp9_64.so

66

/mgc_tree/AMS/aol/lib/libeldocsem_64.so/mgc_tree/AMS/aol/lib/libeldomos2_64.so/mgc_tree/AMS/aol/lib/libeldomos3_64.so/mgc_tree/AMS/aol/lib/libeldobip_64.so/mgc_tree/AMS/aol/lib/libeldodio_64.so/mgc_tree/AMS/aol/lib/libeldojfet_64.so/mgc_tree/AMS/aol/lib/libeldosoi_64.so/mgc_tree/AMS/aol/lib/libeldomos4_64.so/mgc_tree/AMS/aol/lib/libeldoasitft_64.so/mgc_tree/AMS/aol/lib/libeldohisim_64.so/mgc_tree/AMS/aol/lib/libeldospmod_64.so/mgc_tree/AMS/aol/lib/libeldopsp_64.so/mgc_tree/AMS/aol/lib/libeldomosvar_64.so/mgc_tree/AMS/aol/lib/libeldolegtft_64.so/mgc_tree/AMS/aol/lib/libeldomoto_64.so/mgc_tree/AMS/aol/lib/libeldost_64.so/mgc_tree/AMS/aol/lib/libeldobnr_64.so/mgc_tree/AMS/aol/lib/libeldorockw_64.so/mgc_tree/AMS/aol/lib/libeldopubhicum_64.so/mgc_tree/AMS/aol/lib/libeldotftsh_64.so/mgc_tree/AMS/aol/lib/libeldobta_64.so/mgc_tree/AMS/aol/lib/libeldofas_64.so/mgc_tree/AMS/aol/lib/libeldofascm_64.so/mgc_tree/AMS/aol/lib/libeldosdsim_64.so/mgc_tree/AMS/aol/lib/libeldowire_64.so/mgc_tree/AMS/aol/lib/libogr_64.so loaded.

Copyright 1988 Mentor Graphics CorporationAll Rights Reserved

THIS WORK CONTAINS TRADE SECRET AND PROPRIETARYINFORMATION WHICH ARE THE PROPERTY OF MENTORGRAPHICS CORPORATION OR ITS LICENSORS AND ISSUBJECT TO LICENSE TERMS.

***** SYSTEM INFORMATION ...

*** User : unknown@localhost.localdomain*** OS : Red Hat Enterprise Linux Server release 5.9 (Tikanga) [VCO = aol]*** CPU : Pentium(R) Dual-Core CPU E5500 @ 2.80GHz Number of physical processors : 1 Hyper-Threading Technology : disabled Number of cpu cores : 2 Number of logical processors : 2*** Freq : 2800.000MHz*** Cache : 2048 KB*** MEM : 990028 kB*** Date : Thu Mar 19 19:16:18 2015

67

***** PRE-PROCESSING ...

***** ANALYSIS ....

***** 0 error(s). ***** 0 warning(s).

***** GENERATION ...

Warning 1615: In file "./newcell_default.cir" line 11:+ COMMAND ".TRAN": TPRINT can not be <= 0.0.+ It is set to TSTOP/20.0 = 3.000e-08 s.

***** 0 error(s). ***** 1 warning(s).

INFORMATION ABOUT COMPILATION...

Memory space allocated (MB): 25725 elements15 nodes3 input signals

***> Parsing CPU TIME 0h 0mn 0s 040ms <***

Eldo VERSION : ELDO 14.1 (64 bits) Fri Jul 4 10:16:17 GMT 2014

*** DATE: 19-Mar-2015 19:16:19

*** TITLE: * Component: $T_FF/newlib/newcell Viewpoint: default

TEMPERATURE : 27.000000 degrees C

Performing DC analysis...

--> Partitioning circuit...

***> DC CPU TIME 0s 040ms <***

DC:67 iterations FOR DC analysisCLK 0.0000 Q 723.1440N QBAR 4.9039 T 0.0000 VDD 5.0000 X_CELL1.N$113 584.4738M X_CELL1.N$117 4.8665

68

X_CELL1.N$169 4.8790 X_CELL1.N$185 21.5194U X_CELL1.N$186 5.0000 X_CELL1.N$28 4.8790 X_CELL1.N$34 566.6852M X_CELL1.N$46 5.0000 X_CELL1.N$53 529.6748M X_CELL1.N$59 1.9396M

TOTAL POWER DISSIPATION: 5.3039N WATTS

Eldo NEWTON: VNTOL=1.000000e-06 RELTOL=1.000000e-03

Connecting to JWDB server, please wait...connected to wdb server : -jwdbhost localhost.localdomain -jwdbport 60460

Compute from 0.000000 Nano to 600.000000 Nano

................................................Simulation progress : 10% (t = 61.2305 N)Elapsed CPU time : 0h 0mn 0s 0 ( 0h 0mn 0s 0)CPU Usage : 0% ( 0%)................................................Simulation progress : 20% (t = 121.0000 N)Elapsed CPU time : 0h 0mn 0s 10 ( 0h 0mn 0s 10)CPU Usage : 100% ( 83%)................................................Simulation progress : 30% (t = 182.2305 N)Elapsed CPU time : 0h 0mn 0s 0 ( 0h 0mn 0s 10)CPU Usage : 0% ( 55%)................................................Simulation progress : 40% (t = 242.4408 N)Elapsed CPU time : 0h 0mn 0s 10 ( 0h 0mn 0s 20)CPU Usage : 100% ( 90%)................................................Simulation progress : 50% (t = 300.0000 N)Elapsed CPU time : 0h 0mn 0s 0 ( 0h 0mn 0s 20)CPU Usage : 0% ( 76%)................................................Simulation progress : 60% (t = 361.2305 N)Elapsed CPU time : 0h 0mn 0s 10 ( 0h 0mn 0s 30)CPU Usage : 100% ( 96%)................................................Simulation progress : 70% (t = 421.0000 N)Elapsed CPU time : 0h 0mn 0s 0 ( 0h 0mn 0s 30)CPU Usage : 0% ( 83%)................................................Simulation progress : 80% (t = 482.2305 N)Elapsed CPU time : 0h 0mn 0s 10 ( 0h 0mn 0s 40)CPU Usage : 100% ( 97%)................................................

69

Simulation progress : 90% (t = 542.4408 N)Elapsed CPU time : 0h 0mn 0s 0 ( 0h 0mn 0s 40)CPU Usage : 0% ( 88%)................................................Simulation progress : 100% (t = 600.0000 N)Elapsed CPU time : 0h 0mn 0s 0 ( 0h 0mn 0s 40)CPU Usage : 0% ( 81%)

***>Current simulation completed

SIMULATION INFORMATION memory size allocated in Mbytes 259.8Latency: 0.000000%average number of newton iterations: 2.334630nb of components: 25nb of nodes: 59nb of MOS or BIP calls: 16871Number of steps computed: 257

***>CPU TIME 0s 040ms <***

***>MESSAGE SUMMARY: 1 warning

***>GLOBAL CPU TIME 0s 180ms <***

***>GLOBAL ELAPSED TIME 2s <***

======================================================================================

70

CHAPTER 6

COMPARISION RESULTS

6.1 COMPARISON RESULTS OF CMOS USING T-FLIP FLOP:

CELL COMPARISON RESULTS ( TOP LEVEL )

# ################### _ _ # # # * * # # # CORRECT # | # # # # \___/ # ###################

LAYOUT CELL NAME: newlaySOURCE CELL NAME: cell

--------------------------------------------------------------------------------------------------------------

INITIAL NUMBERS OF OBJECTS--------------------------

Layout Source Component Type------ ------ --------------Ports: 6 6

Nets: 27 27

Instances: 23 23 MN (4 pins) 23 23 MP (4 pins)

------ ------Total Inst: 46 46

NUMBERS OF OBJECTS AFTER TRANSFORMATION---------------------------------------

Layout Source Component Type------ ------ --------------Ports: 6 6

Nets: 17 17

Instances: 2 2 MP (4 pins) 2 2 SPMN_2_1 (5 pins)

71

5 5 _invv (4 pins)2 2 _nand2v (5 pins)4 4 _nor2v (5 pins)

2 2 _smp2v (4 pins)------ ------Total Inst: 17 17

**************************************************************************************************************INFORMATION AND WARNINGS**************************************************************************************************************

Matched Matched Unmatched Unmatched ComponentLayout Source Layout Source Type------- ------- --------- --------- ---------Ports: 6 6 0 0

Nets: 17 17 0 0

Instances: 2 2 0 0 MP(PMOS)2 2 0 0 SPMN_2_1

5 5 0 0 _invv2 2 0 0 _nand2v4 4 0 0 _nor2v2 2 0 0 _smp2v------- ------- --------- ---------Total Inst: 17 17 0 0

o Initial Correspondence Points:

Ports: VDD GROUND Q QBAR CLK T

72

6.2 COMPARISON RESULTS OF GDI USING T-FLIP FLOP

CELL COMPARISON RESULTS ( TOP LEVEL )

# ################### _ _ # # # * * # # # CORRECT # | # # # # \___/ # ###################

LAYOUT CELL NAME: l3SOURCE CELL NAME: C1

--------------------------------------------------------------------------------------------------------------

INITIAL NUMBERS OF OBJECTS--------------------------

Layout Source Component Type ------ ------ -------------- Ports: 6 6

Nets: 15 15

Instances: 11 11 MN (4 pins) 11 11 MP (4 pins) ------ ------ Total Inst: 22 22

NUMBERS OF OBJECTS AFTER TRANSFORMATION---------------------------------------

Layout Source Component Type ------ ------ -------------- Ports: 6 6

Nets: 15 15

Instances: 5 5 _invb (6 pins) 6 6 _invv (4 pins) ------ ------ Total Inst: 11 11

73

************************************************************************************************************** INFORMATION AND WARNINGS**************************************************************************************************************

Matched Matched Unmatched Unmatched Component Layout Source Layout Source Type ------- ------- --------- --------- --------- Ports: 6 6 0 0

Nets: 15 15 0 0

Instances: 5 5 0 0 _invb 6 6 0 0 _invv ------- ------- --------- --------- Total Inst: 11 11 0 0

o Initial Correspondence Points:

Ports: VDD GROUND QBAR Q T CLK

74

CHAPTER 7

CONCLUSION AND FUTURE SCOPE

CONCLUSION

A novel methodology for asynchronous circuits, based on two-transistor GDI cells, was

presented. In this project we proposed a GDI T flip flop for low-power design was presented.

The proposed circuit has a simple structure, based on two Master-Slave principles, and some

gates to describe T flip flop. It contains 24 transistors. An optimization procedure was developed

for GDI TFF, based on iterative transistor sizing, while targeting a minimal power-delay product.

Performance comparison with other TFF design techniques was shown, with respect to gate area,

delay and power dissipation.

FUTURE SCOPE

Gate diffusion input (GDI) technique is used for designing the logic gates, also the power consumption, delay, chip area and connection and parasitic capacitors are decreased

75

CHAPTER 8

BIBILOGRAPHY

1. H. Kawaguchi and T. Sakurai. A reduced clock-swing flipflop (RCSFF) for 63%power

reduction

2. U. Ko and P. Balsara. High performance, energy-efficient D flipflop circuits

3. B. Nikoli´c, V. OklobdSzija, V. Stojanovi´c,W. Jia, J. Chiu, and M. Leung. Improved sense-

amplifier-based flip-flop: Design and measurements.

4. M. Nogawa and Y. Ohtomo. A data-transition look-ahead DFF circuit for statistical reduction

in power consumption.

5. V. Stojanovi´c and V. OklobdSzija. Comparative analysis of master-slave latches and flip-

flops for high-performance and lowpower systems.

6. T. Lang, E. Musoli, and J. Cortadella. Individual flip-flops with gated clocks for low power

datapaths.

7. V. Zyuban and P. Kogge. Application of STD to latchpower estimation. IEEE Trans. VLSI

Systems, 7(1):111–115, March 1999.

8. A. Morgenshtein, A. Fish, I.A. Wagner, “Gate-Diffusion Input (GDI) – A Power Efficient

Method for Digital Combinatorial Circuits,”

9. MOSIS, http://www.mosis.org.

10. Ken Martin, "Digital Integrated Circuit Design", Oxford university press, 2000.

76

APPENDIX-A

Below table shows the comparison values between Gate diffusion input (GDI) and

CMOS.

S.NO Name GDI CMOS 1 T-flip flop 5.3039N watts 471.8403N watts

APPENDIX-B

77

78

79