Design of a low power asynchronous SRAM in 45nM CMOS

Asynchronous SRAM in 45nM CMOS NCSU Free PDKPaper ID: CSMEPUN-1011-033

International Conference on Computer Science and Mechanical Engineering

10th November 2013, PunePaper presented by: Nirav Desai, Assistant Professor,

Dept. of ECE, ITM UniverseWork done as a student at the University of

Minnesota, Twin Cities

Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Citie

Introduction

• 6 Transistor SRAM design presented here.• Mainly used in Level 1 cache memories of

microprocessors.• Low power and fast speed of memory access

are design parameters.• Self timed design to provide immunity to

process variations and adaptability to different clock speeds.


SRAM Cell Design


Figure 1: M1, M3 are inverter pull down transistors. M2 and M4 are inverter pull up transistors. M5 and M6 are NMOS access transistors. BL is bit line and WL is word line. Source: Wikipedia

𝐶𝑒𝑙𝑙 𝑅𝑎𝑡𝑖𝑜=

𝑊𝑎𝑐𝑐𝑒𝑠𝑠𝐿𝑎𝑐𝑐𝑒𝑠𝑠

𝑊𝑝𝑢𝑙𝑙𝑑𝑜𝑤𝑛𝐿𝑝𝑢𝑙𝑙𝑑𝑜𝑤𝑛

>1.28 (𝑅𝑒𝑎𝑑𝑆𝑡𝑎𝑏𝑖𝑙𝑖𝑡𝑦 𝐸𝑞𝑢𝑎𝑡𝑖𝑜𝑛 ) ..(1)

1. Read Operation Stability

𝑃𝑢𝑙𝑙𝑢𝑝 𝑅𝑎𝑡𝑖𝑜=

𝑊𝑝𝑢𝑙𝑙𝑢𝑝𝐿𝑝𝑢𝑙𝑙𝑢𝑝𝑊𝑎𝑐𝑐𝑒𝑠𝑠𝐿𝑎𝑐𝑐𝑒𝑠𝑠

<1.6𝑉 (𝑊𝑟𝑖𝑡𝑒𝑂𝑝𝑒𝑟𝑎𝑡𝑖𝑜𝑛𝑆𝑡𝑎𝑏𝑖𝑙𝑖𝑡𝑦 ) . .

2. Write Operation Stability

3. Minimum Cell Area

Design equations for 6T SRAM:

4. Reverse Short Channel Effect

SRAM CELL READ AND WRITE MARGIN FROM BUTTERFLY CURVE • NMOS inverter = 110nM PMOS inverter = 220nM NMOS Access = 90nM• NMOSinv/NMOSaccess = 1.2 PMOSinv/NMOSaccess=2.4 • Cbitline = 0.747fF for 512 cell array ( Interconnect Parasitics from ASU PTM Website )


SRAM CELL READ AND WRITE MARGIN FROM BUTTERFLY CURVE • NMOS inverter = 150nM PMOS inverter = 555nM NMOS Access = 180nM• NMOSinv/NMOSaccess = 1.2 PMOSinv/NMOSaccess = 3 Cbitline = 0.747fF• Curve shows SRAM cell is close to write failure. • Bitline Precharge to less than 1.1V could be explored to increase SNM.


Simulation Setup

• M0,M1,M3,M4 form the cross coupled inverter pair• M5,M6 are access transistors• C1, C2 is the bitline capacitance• M7 is the precharge switch for bitline ( bit ) - V3 precharges the bitline to 0.8V• V6 precharges bitbar and writes a 0 to the cell

V(write)

V(ic) V(word)

V(qbar)

V(q)

V(bitbar)V(bit)


Timing Waveforms for Characterization

V(write) – Applied to source of M7 (precharge switch)

V(word) – Wordline Voltage

V(qbar)

V(q)

V(ic) – Enables the precharge switch M7

V(bitbar)

V(bit)

• V(write) precharges Cbit to 0.8V via M7• V(word) disables access transistors M5 and M6 during precharge .• V(qbar) and V(q) are used to generate the butterfly curves.• V(ic) enables M7 during precharge It could be implemented as NOT(V(word)).• V(bitbar) precharges to 0.8V, shows

charge pumping when M7 turns off and follows V(qbar) when wordline is enabled.

• V(bit) follows V(q) after word line is enabled.• V(bit) precharged to Vdd by V6

Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities

PASS TRANSISTOR BASED TREE DESIGN

a0

a0

a1

a1

a1

a1

a2

a2

a2

a2

a2

a2

a2

a2

1:8 Row Decoder Tree

8 M

SB B

UFF

ERS

in

Similar Tree Decoder for 16 LSB Bits


TREE DECODER DESIGN

From row buffer

From column buffer

To Word Line Buffer

24 = 16 LSB Bits for Word Line Address from Column Buffers

23 =

8 M

SB B

its fo

r Wor

d Li

ne A

ddre

ss fr

om R

ow B

uffer

s

Directions of Increasing bit number


PASS TRANSISTOR BASED TREE DESIGN

IN OUT

CK

CK

50

880

L

W

Identical Sizing for NMOS and PMOS to minimize charge injection effects

0200

400600

8001000

12001400

16001800

20008090

100110120130140150160170

Series1; 158.9

118.55

98.889.3

84.86

Delay

Transistor Width (nM)

Del

ay (p

sec)

• Delay drops by ~40ps/2 for every Doubling of transistor widths• Delay drop saturates around 1000nM to 89ps• Used W/L of 880/50 for final tree


TREE DECODER TIMING DIAGRAMS

The following waveforms were applied to the row and column selection inputs of the tree decoder



It takes one cycle for initializing the tree decoder after which we get clean pulses for each row output

LSB pulse is wider than MSB pulse in bottom figure to allow the tree to clear present state before next



The top waveforms shows the matrix point output where the row and column select inputs are highThe output node discharges when the input goes low


SRAM TIMING CIRCUIT

220

110

in

SAE/Write Enable

Wordline Enable

Precharge

Read/Write Input PulsePrecharge Disable Pulse

Word Line Enable PulseRead/Write Output Pulse

Timing Sequence:1. Disconnect Precharge2. Enable Word Line3. SAE / Write Enable4. Wait for read/write

5. Disble SAE/Write Enable6. Disable Wordline7. Reconnect Precharge and discharge all word lines


READ WRITE CIRCUIT ( Design by Bong Jin )

Sense Amplifier Write Driver

Precharge Circuit


READ WRITE CIRCUIT TEST SETUP

Bitline Capacitance estimate from ASU PTM Website

Cbit estimate for 512 rows

NMOS Switches to allow read without disabling write circuit

Single SRAM Cell for simulations


READ / WRITE TIMING WAVEFORMS

Precharge Pulse ( Active Low )

Data Meant to be written to cell

Write Enable Pulse

Read Enable Pulse

Output of Write Buffer

Disable output buffer ( tristate logic )

Bitline

Bitline Bar

Data Output

Data Out Bar


SRAM Cell Layout


2X2 SRAM Array Layout

VDD

GND

GND

WORD 1

WORD 0

B0 B0BAR B1 B1BAR

This unit can be replicated in all directions without any changes. LVS check remainingArray Size = 3.7975umX2.4725um



Left: Top waveform: Bitline and Bitline Bar waveforms for reading a 1 and Right: Layout of passTransistor based tree decoder

Final Waveforms and Decoder Layout

References

• Digital Integrated Circuits Jan Rabaey, Anantha Chandrakasan, Borivoje Nikolic ( SRAM Cell Design, Decoders, Read Write Circuits )• CMOS VLSI Design by Weste and Harris ( Butterfly Curves )• CMOS Circuit Design, Layout and Simulation Baker, Li, Boyce (Decoder Design)• Course slides of Prof. Kia Bazargan ( Precharge Techniques, Decoders, SRAM Cell Design )



References (Contd.)• Design of High Performance Microprocessor Circuits by Anantha Chandrakasan, William

Bowhill, Frank Fox• A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage

and Virtual-Ground Replica SchemeTae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim, University of Minnesota

ISSCC 2007• Digital Integrated Circuits by Jan Rabaey• Large-Scale SRAM Variability Characterization in 45 nm CMOS Zheng Guo, Student Member, IEEE, Andrew Carlson, Member, IEEE, Liang-Teck Pang, Member, IEEE, Kenneth T. Duong, Tsu-Jae King Liu, Fellow, IEEE, Borivoje Nikolic´, Senior Member, IEEE• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 11, NOVEMBER 2009• Dama, J.; Lines, A., "GHz Asynchronous SRAM in 65nm," Asynchronous Circuits and

Systems, 2009. ASYNC '09. 15th IEEE Symposium on , vol., no., pp.85,94, 17-20 May 2009doi: 10.1109/ASYNC.2009.23

Technology

Design of a low power asynchronous SRAM in 45nM CMOS