UNIVERSITI PUTRA MALAYSIA

DESIGN OF 1K ASYNCHRONOUS STATIC RANDOM ACCESS MEMORY USING 0.35 MICRON COMPLEMENTARY METAL OXIDE

SEMICONDUCTOR TECHNOLOGY

YEONG TAK NGING.

FK 2005 54

DESIGN OF 1K ASYNCHRONOUS STATIC RANDOM ACCESS MEMORY USING 0.35 MICRON C0MPLEMENTAR.Y METAL OXIDE

SEMICONDUCTOR TECHNOLOGY

BY

YEONG TAK NGING

Thesis Submitted to the School of Graduate Studies, Universiti Putra Malaysia in Fulfilment of the Requirements for the Degree of Master of Science

April 2005

Abstract of thesis presented to the Senate of Universiti Putra Malaysia in fulfilment of the requirement for the degree of Master of Science

DESIGN OF 1K ASYNCHRONOUS STATIC RANDOM ACCESS MEMORY USING 0.35 MICRON COMPLEMENTARY METAL OXIDE

SEMICONDUCTOR TECHNOLOGY

YEONG TAK NGING

April 2005

Chairman

Faculty

: Roslina Mohd Sidek, PhD

: Engineering

Static Random Access Memory (SRAM) is a high speed semiconductor memory

which is widely used as cache memory in microprocessors and microcontrollers,

telecommunication and networking devices.

The SRAM operations are categorized into two main groups: asynchronous and

synchronous. A synchronous SRAM has external clock input signal to control all

the memory operation synchronously at either positive or negative edge of the

clock signal. While, in asynchronous SRAM, the memory events are not referred

or controlled by the external clock.

In this study, we have proposed an asynchronous SRAM which configured with a

self-holding system in the control unit. The self-holding SRAM control system

can produce appropriate signals internally to operate the SRAM system

automatically, eliminating hold and wait time, and eliminating Sense Enable and

Output Enable signals which usually used in SRAM control system. All input

. . 11

signals are synchronized by the internal control unit. The overall SRAM

operations however do not depend on the rising of falling edge of the global

(external) clock signal, and thus, the design is still categorized under

asynchronous SRAM.

The proposed self-holding control system has been developed for a 1 kilobit

SRAM using MIMOS 0.35 micron 3.3V CMOS technology Due to limited

computer resources such as speed and space, the design had been limited to 1

kilobit memory size. The design covers both schematic and layout designs using

Hspice and Cadence Layout Editor, respectively. Meanwhile analysis covers

Hspice, Timernill and LVS (Layout versus Schematic).

The simulation results have shown the self-holding SRAM control system was

working successfully. The design operation speed was 7.0% faster as compared to

the SRAM system without the self-holding circuit. An operation speed of 66Mhz

with access time of 2.85ns was achieved.

Abstrak tesis yang dikemukakan kepada Senat Universiti Putra Malaysia sebagai memenuhi keperluan untuk ijazah Master Sains

REKABENTUK LITAR TAK SEGERAK 1K STATIC RANDOM ACCESS MEMORY DENGAN MENGGUNAKAN TEKNOLOGI

COMPLEMENTARY METAL OXIDE SEMICONDUCTOR 0.35 MIKRON

Oleh

YEONG TAK NGING

April 2005

Pengerusi

Fakulti

: Roslina Mohd Sidek, PhD

: Kejuruteraan

SRAM atau "Static Random Access Memory" merupakan ingatan semikonduktor

yang berkelajuan tinggi di man ia digunakan secara meluas sebagai ingatan utama

dalam litar pemprosesan mikro, litar pengawalan mikro, telekomunikasi dan

peranti rangkaian.

Operasi SRAM dapat dikategorikan dalam dua kumpulan utama, iaitu litar tak

segerak and litar segerak. SRAM segerak mempunyai kawalan masukan berjam

luaran bagi mengawal kesemua operasi secara segerak samada pada pinggir positif

atau pinggir negatif. Sementara itu, dalam SRAM tak segerak, operasinya tidak

merujuk atau dikawal oleh kawalan berjam luaran.

Dalam kajian ini, kami mencandangkan satu litar SRAM tak segerak dengan litar

pegang-sendiri. Sistem kawalan bagi sistem SRAM tersebut dapat menjana

keluaran yang sepatutnya secara dalaman bagi mengoperasi SRAM secara

automatik, menghapuskan masa pegang dan masa menunggu, serta menghapuskan

iv

masukan "Deria Dibenarkan" dan "Keluaran Dibenarakan". Semua masukan

dlsegerakkan oleh unit kawalan dalaman. Namun, keseluruhan operasi SRAM

tidak bergantung kepada pinggir positif atau pinggir negatif masukan berjam, dan

dengan demikian, ia masih dikenali sebagai SRAM tak segerak.

Sistem kawalan yang dicandangkan dlbina untuk 1 kilobit sistem SRAM dengan

menggunakan teknologi MIMOS 0.35 mikron 3.3V CMOS. Disebabkan oleh

keterhadan kelajuan komputer dan simpanannya, rekabentuk telah hterhadkan

kepada ingatan bersaiz 1 lulobit sahaja. Rekabentuk merangkumi litar dan

bentangan dengan menggunakan Hspice dan Cadence Layout Editor masing-

masing. Sementara itu, analisi merangkumi Hspice, Timemill dan LVS (Bentangan

lawan Litar).

Simulasi telah menunjukkan sistem kawalan pegang-sendirir SRAM tersebut

berjaya berfungsi. Rekabentuk tersebut berfungsi dengan 7.0% lebih laju

berbanding dengan sistem tanpa kawalan pegang-sendiri. Kelajuan operasi adalah

66Mhz dengan masa capaian bernilai 2.85ns.

ACKNOWLEDGEMENTS

First and foremost, I would like to express my utmost gratitude to my project

supervisor, Dr Roslina Sidek, En Rahman Wagiran and En Wan Zuha Wan Hasan

for their invaluable guidance, constructive suggestion and encouragement

throughout the duration of the project.

My sincere gratitude goes to my srarn group in MIMOS Berhad, especially Dr.

Mohd Rais Ahmad, En Hanif, En Faizal and Puan Shelli. They have helped and

guided me to handle the CAD (Computer Aided Design) tools in MIMOS that

were used in the project. Not forgetting my friends Cherk Teing, Kenny and Wai

Leong, whose have given me some guidance in the project. And also thanks to

staff and consultants of the Engineering Faculty and people who have help my

years in University more interesting and meaningful.

Words cannot express my deepest appreciation to my family especially my

parents and my wife for their undying love, patient, and support which have

enabled me to complete the project successfully.

I certify that an Examination Committee met on 1 lth April 2005 to conduct the final examination of Yeong Tak Nging on his Master of Science thesis entitled "Design of 1K Asynchronous Static Random Access Memory Using 0.35 Micron Complementary Metal Oxide Semiconductor Technology" in accordance with Universiti Pertanian Malaysia (Higher Degree) Act 1980 and Universiti Pertanian Malaysia (Higher Degree) Regulations 198 1. The Committee recommends that the candidate be awarded the relevant degree. Members of the Examination Committee are as follows:

Mohamad Khazani Abdullah, PhD Associate Professor Faculty of Engineering Universiti Putra Malaysia (Chairman)

Sudhanshu Shekhar Jamuar, PhD Professor Faculty of Engineering Universiti Putra Malaysia (Internal Examiner)

Abdul Rahman Ramli, PhD Associate Professor Faculty of Engineering Universiti Putra Malaysia (Internal Examiner)

Abu Khari A'ain, PhD Associate Professor Faculty of Electrical Engineering Universiti Teknologi Malaysia (External Examiner)

School of ~raduate Studies Universiti Putra Malaysia

vii

This thesis submitted to the Senate of Universiti Putra Malaysia has been accepted as fulfilment of the requirement for the degree of Master of Science. The members of the Supervisory Committee are as follows :

Roslina Sidek, PhD Lecturer Faculty of Engineering Universiti Putra Malaysia (Chairman)

Rahman Wagiran, MSc. Lecturer Faculty of Engineering Universiti Putra Malaysia (Member)

Wan Zuha Wan Hasan, MSc. Lecturer Faculty of Engineering Universiti Putra Malaysia (Member)

AINI IDERIS, PhD ProfessorIDean School of Graduate Studies Universiti Putra Malaysia

1 1 AUG 2005

. . . V l l l

DECLARATION

I hereby declare that the thesis is based on my original work except for quotations and citations which have been duly acknowledged. I also declare that it has not been previously or concurrently submitted for any other degree at UPM or other institutions.

Date: 03 /Q 7 / x 0OAp

TABLE OF CONTENTS

Page

ABSTRACT ABSTRAK ACKNOWLEDGEMENTS APPROVAL DECLARATION LIST OF TABLES LIST OF FIGURES LIST OF ABBREVIATIONS

CHAPTER

INTRODUCTION 1.1 Semiconductor Memories 1.2 SRAM 1.3 SRAM History 1.4 SRAM Market 1.5 Publication of Asynchronous Circuits 1.6 Types of SRAM 1.7 Synchronous SRAMs 1.8 Asynchronous (Fast) SRAMs 1.9 Asynchronous and Synchronous Issues 1.10 Objectives 1.1 1 Thesis Structure

LITERATURE REVIEW 2.1 Types of Semiconductor Memories 2.2 Low Power SRAM 2.3 Low Power SRAM Design Architecture

2.3.1 Divided Word Line Architecture 2.3.2 Hierachical Word Line Architecture SRAM Memory Cells 2.4.1 6T SRAM Cells

2.4.1.1 Conventional 6T SRAM Cell Architecture

2.4.1.2 Driving Source-Line 6T SRAM Cell Architecture

2.4.2 4T SRAM Cells Row/Column Decoder

. . 11

iv vi vii ix xiii xiv XX

2.6 Multiplexer 2.7 Sense Amplifiers 2.8 Pull-up Circuits 2.9 Control Unit 2.10 Write Drive Circuit 2.11 InputIOutput Buffer 2.12 Literature Review Conclusion

METHODOLOGY 3.1 Design Flow Chart 3.2 SRAM System Block Diagram

3.2.1 Inverter 3.2.2 NANDIAND Gates 3.2.3 NOWOR Gates 3.2.4 SRAM Memory Cell 3.2.5 RowIColumn Decoder 3.2.6 Multiplexer 3.2.7 Sense Amplifier 3.2.8 Pull-up Circuit 3.2.9 Write Circuit 3.2.10 Control Unit 3.2.1 1 Output Buffer Layout Design Capacitance and Resistance (RC) Effects

RESULTS AND DISCUSSION 4.1 Hspice Analysis Results

4.1.1 Inverter and Delay (Inverter Pair) 4.1.2 NAND and AND Gates 4.1.3 NOR and OR Gates 4.1.4 SRAM Cell 4.1.5 Row and Column Decoder 4.1.6 Multiplexer 4.1.7 Sense Amplifier 4.1.8 Pull-up 4.1.9 Write Drive 4.1.10 Control Unit 4.1.1 1 Tristate Output Buffer 4.1.12 lK SRAM Timemill Analysis Layout 4.3.1 Inverter and Inverter Pair (Delay) Layout 4.3.2 NAND and AND Gates Layout 4.3.3 NOR and OR Gates Layout 4.3.4 6T SRAM Cell Layout 4.3.5 Row and Column Decoder Input Buffer

Layout

4.3.6 Row and Column Decoder Layout 4.3.7 Multiplexer Layout 4.3.8 Sense Amplifier Layout 4.3.9 Pull-up Circuit Layout 4.3.10 Write Drive Circuit Layout 4.3.1 1 Control Unit Layout 4.3.12 Tristate Output Buffer 4.3.13 1 Kilobit SRAM System LVS (Layout Versus Schematic) Layout Extraction and Analysis Self-holding System Performance Characterization System Expansion Flexibility

CONCLUSION 5.1 Future Development

APPENDICES A 1K SRAM Hspice Netlist Sample B LVS Verification Output File (1K SRAM) C Extracted Spice Netlist Sample

BIODATA OF THE AUTHOR

xii

LIST OF TABLES

Table

2.1 Memory types comparison [4].

2.2 SRAM cell comparison[l6].

2.3 Summary of the 6T SRAM cell transistors state refer

to node N5 and node N6 condition.

Inverter input and output relation.

3.2 A 2-input NAND gate true table.

3.3 2-input NOR gate true table.

3.4 Addresses decoding (a) Row decoder (b) Column Decoder.

3.5 The CSNB and WENB control of the SRAM system.

3.6 Inputs and outputs condition for the control unit.

3.8 Input and output condition for the tristate output buffer.

Page

17

. . . Xll l

LIST OF FIGURES

Figure

1.1 Typical PC microprocessor memory configuration [6].

Source: ZCE(1ntegrated Circuit Engineering)Corporation.

1.2 SRAM block diagram.

1.3 SRAM technologies development flow chart.

1.4 SRAM market growth from year 1992 to 2002[7].

1.5 Yearly publication count on asynchronous logic[l 11.

1.6 Overview of SRAMs types[6]. Source:ZCE, 1997.

1.7 Synchronous SRAM timing diagram (a)Read cycle

(b)write cycle.

1.8a Waveform comparison between conventional SRAM

and this project target for the read cycle.

1.8b Waveform comparison between conventional SRAM

and this project target for the write cycle.

Page

2.1 Masahiko Yoshimoto's Divided Word Line (DWL) concept[l3]. 20

2.2 Hierarchical Word Line (HWL) SRAM architecture[l5]. 22

2.3 (a) 6T SRAM memory cell configuration, 24

(b) 6T SRAM cell logical representation.

2.4 Writing a '1' into 6T cell.

2.5 Writing a '0' into 6T cell.

2.6 Read a '1' in the SRAM system.

2.7 Cell architecture comparison (a) conventional 6T SRAM

architecture, and (b) driving source-line 6T SRAM

xiv

architecture.

2.8 Load resister cell.

TFT (Thin Film Transistor) SRAM cell.

4T full CMOS SRAM cell.

A 4-bit non-pre-decoding circuit.

A 4-bit pre-decoding circuit.

p-channel pass transistor.

n-channel pass transistor.

CMOS pass transistor.

Single ended current mirror sense amplifier [2].

Double ended current mirror sense amplifier [I].

Conventional Current sense amplifier developed

by Seevinck[26].

2.19 High performance cross coupled current mirror

sense amplifier[24].

2.20 A hybrid current sense amplifier configuration.

2.21 A conventional latch type voltage sense amplifier.

2.22 Latch type voltage sense amplifier introduced by Kobayashi

et al. [29].

2.23 Two MOSFETs pullup circuitries (a)p-channel MOSFETs,

(b)n-channel MOSFETs.

2.24 Three MOSFETs pullup circuitries with bitlines balancing

(a)p-channel MOSFETs, (b)n-channel MOSFETs.

2.25 Control unit signaling.

2.26 Conventional SRAM write circuit [I].

2.27 Power pin protections with input protection pad [36].

2.28 A simplified diode model for the ESD protection circuit.

3.1 Design flow chart.

3.2 The asynchronous self-holding SRAM design block diagram.

3.3 (a) Inverter CMOS structure (b) Inverter transit curve.

3.4 (a) Inverter pair circuit, (b) inverter pair logical diagram.

3.5 (a) A 2-input CMOS NAND gate structure,

(b) 2-input NAND gate logical diagram.

3.6 AND gate formation with a NAND gate and inverter

combination.

3.7 A 5-input AND gate (a) CMOS structure (b) logical diagram.

3.8 2-input NOR gate (a) circuit diagram (b) logical diagram.

3.9 An OR formation.

3.10 A 3-input NOR gate (a) schematic diagram

(b) logical diagram.

3.11 6T SRAM memory cell (a) schematic diagram

(b) logical diagram.

3.12 The row/column decoder with input buffer circuit.

3.13 Pass gate schematic of SRAM Multiplexer.

3.14 Single ended current mirror sense amplifier.

3.15 Pull-up circuitry.

3.16 (a)Write drive circuitry (b)write circuitry

waveforms transition estimation.

xvi

3.17 Self-holding control circuit design for the 1 kilobit SRAM.

3.18 The control unit waveforms transition.

3.19 Output buffer circuitry.

3.20 PMOS transistor (a) Cadence layout (b) cross section

view of the PMOS transistor layout.

3.21 nMOS transistor (a) Cadence layout (b) cross section

view of the nMOS transistor layout.

4.1 Spice netlist definition.

4.2 A pulse wave waveform definition.

4.3 The inverter waveform transition result.

4.4 Inverter pair (delay circuit) delay analysis result.

4.5 2-input NAND gate transient result.

4.6 Illustration shows the root cause of a voltage drops

in Figure 4.5.

4.7 2-input AND gate transient result.

4.8 5-input AND gate transient result.

4.9 3-input NOR gate simulation result.

4.10 2-input OR gate simulation result.

4.1 1 6T SRAM cell write operation simulation result.

4.12 Row and column decoder functionality test result.

4.13 Multiplexer functionality test result.

4.14 Illustration shows the of the single ended

current mirror sense amplifier breakdown.

4.15 A modified single ended current mirror sense amplifier.

xvii

4.16 Modified single ended current mirror sense amplifier

voltage swing sensing capability result.

4.17 Pull-up circuitry verification result.

4.18 Write drive circuitry verification test result.

4.19 Control unit functionality test result.

4.20 Tristate output buffer functionality test result.

4.21 1 kilobit SRAM functionality test result.

4.22 (a)Average power consumption

(b) Average current consumption of the

1 kilobit SRAM analysis.

4.23 Inverter layout.

4.24 An inverter pair or delay circuit layout.

4.25 A 2-input NAND gate layout.

4.26 A 2-input AND gate layout.

4.27 A 5-input AND gate layout.

4.28 3-input NOR gate layout.

4.29 A 2-input OR gate layout.

4.30 6T SRAM memory cell layout.

4.31 Duplication and extension of single 6T SRAM memory

cell methodology.

4.32 Row and column decoder address input buffer layout.

4.33 Row and column decoder layout.

4.34 Single bit multiplexer cell layout.

4.35 A single ended current mirror sense amplifier.

xviii

4.36 Single bit pull-up circuitry layout.

4.37 Write drive circuitry layout.

4.38 The control unit circuitry layout.

4.39 Tristate output buffer layout.

4.40 1 Kilobit SRAM system layout.

4.41 1 kilobit SRAM layout functionality analysis result.

4.42 1 lulobit SRAM layout functionality test with

"chip disabled" after the write cycle.

4.43 (a)Average power dissipation

(b)Average current consumption analysis of the 1

kilobit SRAM layout.

4.44 The 1 kilobit asynchronous SRAM ac characteristic

for read cycle (a) without self-holding system,

(b) with self-holding system.

The 1 kilobit asynchronous SRAM ac characteristic for

write cycle (a) without self-holding system, (b) with

self-holding system.

4.46 The 1 kilobit asynchronous self-holding SRAM system

block diagram.

4.47 The 2 kilobit SRAM from the 1 kilobit SRAM expansion

configuration.

4.48 A 64kilobit asynchronous SRAM system structure which

utilizes the asynchronous self-holding SRAM system

modules.

xix

LIST OF ABBREVIATIONS

pBGA

CAD

CMOS

NMOS

CSP

DDR

DRAM

DRC

EEPROM

ERC

ESD

FBGA

FeRAM

I/O

IC

LVS

LW

MRAM

NMOS

PB

ROM

SRAM

STSOP

TFT

TSOP

pBGA

W L

ZBT

Micro Ball Grid Array

Computer Aided Design

Complementary Metal Oxide Semiconductor

n-channel depletion Metal Oxide Semiconducto

Chip Scale Package

Double Data Rate

Dynamic Random Access Memory

Design Rules Checker

Electrical Erasable Read Only Memory

Electrical Rules Checker

Electro Static Discharge

Fine-pitch Ball Grid Array

Ferroelectric Random Access Memory

InputIOutput

Integrated Circuit

Layout Versus Schematic

Late Write

Magnetoresistive Random Access Memory

n-type Metal Oxide Silicon

Pipelined Burst

Read Only Memory

Static Random Access Memory

Shrink Thin Sarnll Outline Package

Thin Film Transistor

Thin Small Outline Package

Micro Ball Grid Array

WidthILength

Zero Bus Turn-around

CHAPTER 1

INTRODUCTION

1.1 Semiconductor Memories

Semiconductor memories have a wide market and commercial values.

Semiconductor memories are divided into two families; volatile and non-volatile.

Volatile memories are able to retain the data in the device as long as the power is

supplied. For non-volatile memories, the data can retain in the device after the

cutoff of the power supply. As an example, Read Only Memory (ROM) is a non-

volatile memory while Random Access Memory (RAM) is a volatile memory.

Recently, combination of volatile and non-volatile memories has been highly

applied especially in critical operation such as networking and workstation.

Various types of semiconductor memories have been introduced in almost all kind

of electrical products ranging from home products to networking and

communication products. Dynamic Random Access Memory (DRAM), Static

Random Access Memory (SRAM), Electrical Erasable Read Only Memory

(EEPROM), Double Data Rate DRAM (DDRRAM), Dual Channel DDRRAM,

Rambus, Magnetic Random Access Memory (MRAM), Flash memory, Ferro-

Electric Random Access Memory, Mirror Bit Random Access Memory, and so

on.

Due to the high demand of semiconductor memories for consumers,

semiconductor technologies continue to scale down to achieve higher density and

higher performance.

1.2 SRAM

Static Random Access Memory (SRAM) is a very fast and low power memory. It

consists of latch type cells where refresh circuitry is not required. Refresh

circuitry is needed in DRAMS (Dynamic Random Access Memory) to retain the

stored data. The refresh system in DRAM requires complex design and

engineering sophistication [I]. For SRAM, data are stored in the memory cells as

long as voltage is supplied to the devices.

Today, SRAMs are used as main memory in small systems with high performance

like L l cache (register), and L2 cache (SRAM) memory in microprocessors [4].

Figure 1.1 shows a typical personal computer (PC) microprocessor memory

configuration.

Microprocessor

SRAM

Figure 1.1 : Typical PC microprocessor memory configuration[6]. Source: ZCE(1ntegrated Circuit Engineering)Corporation

DRAM

Due to the low power consumption, SRAMs have become more and more popular

in low power applications. The advantages of CMOS SRAMs are as following:

Low supply voltage and low power dissipation compared to

DRAMS, due to its small standby current. For mobile devices,

battery will have longer lifetime.

High noise immunity and high noise margin

Simple control logic and easy to use because there is no refreshing

circuitry and no address multiplexing.

Fast access time.

However, SRAMs have higher cost per bit compared to other technologies [4]. It

is also difficult to use internal voltage down converters VDc in low power SRAM.

Figure 1.2 shows a general asynchronous SRAM system block diagram.

Control Circuits

Figure 1.2 : SRAM block diagram.

To perform the read operation, the address bits are placed on the address bus and

corresponding row and column of the memory cell or cell in the array will be

activated. Then, Chip Select (CSNB) is enabled, followed by Output Enable

(OEB). As shown in Figure 1.8a, the data bits are then ready on the data bus.

Meanwhile, to perform the write operation, the corresponding row and column of

the memory cell will be activated as the read operation. As shown in Figure 1.8b,

the Write Enable (WENB) is enabled and followed by data to be written which is

fetched from DataIn.

1.3 SRAM History

SRAMs have been developed in three technological paths; bipolar, CMOS and

NMOS [I]. Figure 1.3 shows the SRAM technologies development flow chart.

Refer to Figure 1.3, each technology has its own characteristics and market

demands, which depends on system requirements. Early CMOS SRAMs are in

low speed, consume large chip area, and suffered latch-up problem. The first

SRAM was developed by using the bipolar technology. The bipolar SRAM has

suffered high power consumption and high power dissipation. After the invention

of NMOS technology, most of the SRAMs were fabricated using NMOS

technology due to its lower power consumption and dissipation. However,

research and development have done to enhance the CMOS performance. After

the development of polysilicon and aluminium for the CMOS technology, NMOS

SRAM technology was replaced. The new CMOS technology has the capacity to

implement larger and higher density of CMOS memory cell compared to the

4