Data Converters for Solving Hard ProblemsAdvanced Techniques of Higher Performance Signal Processing

2

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3

Today’s Agenda

Data converters in the signal chain

Basics of data conversion

Dynamic signal processing

Driving ADCs

Input structures

DACs for high speed and high resolution

4

Analog to Electronic Signal Processing

SENSOR(INPUT)

DIGITALPROCESSOR

AMP CONVERTER

ACTUATOR(OUTPUT)

AMP CONVERTER

5

Analog to Electronic Signal Processing

SENSOR(INPUT)

DIGITALPROCESSOR

AMP ADC

ACTUATOR(OUTPUT)

AMP DAC

6

Analog and Digital DomainsWhy Convert to Digital?

Analog signals are continuous and provide the entire signal

Digital signals capture only a portion of the signal

Why digitize? Improved signal analysis potential More robust storage More accurate transmission

Why not digitize? Cost Complexity Processing time available.

Development objective of sampled data systems is to minimize effect of the sampling process

7

Basic ADC with External Reference

VDD

VSS

GROUND(MAY BE INTERNALLY CONNECTED TO VSS)

ANALOGINPUT

VREF

DIGITALOUTPUT

SAMPLING CLOCK

CONTROL SIGNALS(EOC, DATA READY, ETC.)

ADC

VDIO

8

Sampled Data System: Sampling and Quantization

LPFORBPF

N-BITADC

DSPN-BITDAC

LPFORBPF

fa

fs fs

t

AMPLITUDEQUANTIZATION DISCRETE

TIME SAMPLING

fa

1fs

ts=

9

Unipolar Binary Code, 4-Bit Converter

+15+14+13+12+11+10

+9+8+7+6+5+4+3+2+1

0

BASE 10NUMBER SCALE +10 V FS BINARY

1111111011011100101110101001100001110110010101000011001000010000

9.3758.7508.1257.5006.8756.2505.6255.0004.3753.7503.1252.5001.8751.2500.6250.000

+FS – 1 LSB = 15/16 FS+7/8 FS

+13/16 FS+3/4 FS

+11/16 FS+5/16 FS+9/16 FS+1/2 FS

+7/16 FS+3/8 FS

+5/16 FS+1/4 FS

+3/16 FS+1/8 FS

1 LSB = +1/16 FS0

+15+14+13+12+11+10

+9+8+7+6+5+4+3+2+1

0

BASE 10NUMBER SCALE +10 V FS BINARY

1111111011011100101110101001100001110110010101000011001000010000

9.3758.7508.1257.5006.8756.2505.6255.0004.3753.7503.1252.5001.8751.2500.6250.000

+FS – 1 LSB = 15/16 FS+7/8 FS

+13/16 FS+3/4 FS

+11/16 FS+5/16 FS+9/16 FS+1/2 FS

+7/16 FS+3/8 FS

+5/16 FS+1/4 FS

+3/16 FS+1/8 FS

1 LSB = +1/16 FS0

10

Bipolar Codes, 4-bit Converter

+4.375+3.750+3.125+2.500+1.875+1.250+0.625

0.000–0.625–1.250–1.875–2.500–3.125–3.750–4.375–5.000

1 1 1 11 1 1 01 1 0 11 1 0 01 0 1 11 0 1 01 0 0 11 0 0 00 1 1 10 1 1 00 1 0 10 1 0 00 0 1 10 0 1 00 0 0 10 0 0 0

0 1 1 10 1 1 00 1 0 10 1 0 00 0 1 10 0 1 00 0 0 1

*0 0 0 01 1 1 01 1 0 11 1 0 01 0 1 11 0 1 01 0 0 11 0 0 0

+FS – 1LSB = +7/8 FS+3/4 FS+5/8 FS+1/2 FS+3/8 FS+1/4 FS+1/8 FS

0– 1/8 FS– 1/4 FS– 3/8 FS–1/2 FS–5/8 FS–3/4 FS

– FS + 1LSB = –7/8 FS– FS

±5V FSSCALE

0 1 1 10 1 1 00 1 0 10 1 0 00 0 1 10 0 1 00 0 0 10 0 0 01 1 1 11 1 1 01 1 0 11 1 0 01 0 1 11 0 1 01 0 0 11 0 0 0

0 1 1 10 1 1 00 1 0 10 1 0 00 0 1 10 0 1 00 0 0 1

*1 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

OFFSETBINARY

TWOSCOMP.

ONESCOMP.

SIGNMAG.

0+ 0 0 0 00– 1 1 1 1

0 0 0 01 0 0 0

ONESCOMP.

SIGNMAG.

CODES NOT NORMALLY USEDIN COMPUTATIONS (SEE TEXT)

+7+6+5+4+3+2+1

0–1–2–3–4–5–6–7–8

BASE 10NUMBER

*

11

The Size of a Least Significant Bit (LSB)

VOLTAGE(10V FS)

2.5 V

625 mV

156 mV

39.1 mV

9.77 mV (10 mV)

2.44 mV

610 mV

153 mV

38 mV

9.54 mV (10 mV)

2.38 mV

596 nV*

ppm FS

250,000

62,500

15,625

3,906

977

244

61

15

4

1

0.24

0.06

% FS

25

6.25

1.56

0.39

0.098

0.024

0.0061

0.0015

0.0004

0.0001

0.000024

0.000006

dB FS

-12

-24

-36

-48

-60

-72

-84

-96

-108

-120

-132

-144

RESOLUTIONN

2-bit

4-bit

6-bit

8-bit

10-bit

12-bit

14-bit

16-bit

18-bit

20-bit

22-bit

24-bit

2N

4

16

64

256

1,024

4,096

16,384

65,536

262,144

1,048,576

4,194,304

16,777,216

*600nV is the Johnson Noise in a 10kHz BW of a 2.2kW Resistor @ 25°C

12

Practical Resolution Needs for Data Converters

Instrumentation measurements Sensor resolution/accuracy of 0.5% = 1/200 8 bits equivalent to 1/256 -- digitizing will lose information 10x sensor resolution = 1/2000 -- 12 bits is 1/4096 Allows discrimination of small changes Can also be driven by display requirements

Dynamic signal measurements Audio systems need better than 0.1% distortion at 5% of full scale Equivalent to 1/20,000 -- 16 bits is 1/65,536

13

Transfer Functions for Ideal 3-Bit DAC and ADC

DIGITAL INPUT

ANALOGOUTPUT

FS

000 001 010 011 100 101 110 111 ANALOG INPUT

DIGITALOUTPUT

FS

000

001

010

011

100

101

110

111

QUANTIZATIONUNCERTAINTY

QUANTIZATIONUNCERTAINTY

DAC ADC

14

Primary Errors in Data Converters(DC Parametrics)

Instrumentation and measurement Described in LSBs (least-significant-bit), % of FS, ppm of FS Offset error – the input level needed to change the first code Gain/full-scale error – the input level need to change the last code Nonlinearity – deviation of codes from the line from zero to FS Differential nonlinearity – code-to-code deviation from 1 LSB Transition noise – ADC uncertainty in code center point

15

Primary Errors in Data Converters (AC Parametrics) Dynamic systems

SINAD (Signal-to-Noise-and-Distortion Ratio):

The ratio of the rms signal amplitude to the mean value of the root-sum-squares (RSS) of all other spectral components, including harmonics, but excluding DC.

ENOB (Effective Number of Bits):

SNR (Signal-to-Noise Ratio), or Signal-to-Noise Ratio without Harmonics:

The ratio of the rms signal amplitude to the mean value of the root-sum-squares (RSS) of all other spectral components, excluding the first 5 harmonics and DC

SFDR (Spurious-Free-Dynamic-Range) Signal dynamic range in the bandwidth of interest containing no frequency noise spurs

ENOB = SINAD – 1.76dB

6.02dB

16

Quantifying Data Converter Dynamic Performance

Harmonic Distortion

Worst Harmonic

Total Harmonic Distortion (THD)

Total Harmonic Distortion Plus Noise (THD + N)

Signal-to-Noise-and-Distortion Ratio (SINAD, or S/N +D)

Effective Number of Bits (ENOB)

Signal-to-Noise Ratio (SNR)

Analog Bandwidth (Full-Power, Small-Signal)

Spurious Free Dynamic Range (SFDR)

Two-Tone Intermodulation Distortion

Multi-tone Intermodulation Distortion

Noise Power Ratio (NPR)

Adjacent Channel Leakage Ratio (ACLR)

Noise Figure

Settling Time, Overvoltage Recovery Time

17

The Comparator: A 1-Bit ADC

DIFFERENTIALANALOG INPUT

LOGICOUTPUT

LATCHENABLE

DIFFERENTIAL ANALOG INPUT

COMPARATOR OUTPUT

"0"

"1"

0

VHYSTERESIS

+

–

18

Quantization and Quantization Noise

001

010

011

100

101

110

111

1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS

NORMALIZED ANALOG INPUT

DIG

ITA

L O

UT

PU

T

Quantization noise error: RMS value is LSB/3.464

Quantizationerror function

19

Combined Effects of Code Transition Noiseand DNL

ADC INPUT ADC INPUT ADC INPUT

CODE TRANSITION NOISE DNL TRANSITION NOISEAND DNL

ADCOUTPUT

CODE

20

Ideal ADC Sampling3 Different Frequencies, Sampled the Same

21

Ideal ADC SamplingOnce Sampled, Information Is Lost

22

Nyquist's Criteria

A signal with a maximum bandwidth of fa must be sampled at a rate fs > 2fa or information about the signal will be lost because of aliasing.

Aliasing occurs whenever fs < 2fa

A signal which has frequency components between fa and fb must be sampled at a rate fs > 2 (fb – fa) in order to prevent alias components from overlapping the signal frequencies.

The concept of aliasing is widely used in communications applications such as direct IF-to-digital conversion.

23

Analog Signal fa Sampled @ fs Has Images (Aliases) At |±Kfs ±fa|, K = 1, 2 ...

0.5fs

0.5fs

fs

fs

1.5fs

1.5fs

2fs

2fs

ZONE 1 ZONE 2 ZONE 3 ZONE 4

fa I I I

I III

I

fa

24

Oversampling Relaxes Requirements on Baseband Antialiasing Filter

BA

DR

fs

fa fs – faKfs – f

afa

fs

2

KfsKfs

2STOPBAND ATTENUATION = DR

TRANSITION BAND: fa to fs – fa

CORNER FREQUENCY: fa

STOPBAND ATTENUATION = DR

TRANSITION BAND: fa to Kfs – fa

CORNER FREQUENCY: fa

Advantages of Differential Analog Input Interfaces for Data Converters

Differential inputs give twice the signal swing vs. single-ended (especially important for low voltage single-supply operation)

Differential inputs help suppress even order distortion products

Many IF/RF components such as SAW filters and mixers are differential

Differential inputs suppress common-mode ADC switching noise including LO feed-through from mixer and filter stages

Differential ADC designs allow better internal component matching and tracking than single-ended. Less need for trimming

Helps minimize the effects of noise on the ground.

If you drive them single-ended, you will have degradation in distortion and noise performance

However, many signal sources are single-ended, so the differential amplifier is useful as a single-ended to differential converter

2.25

ADA4941 Driving AD7690 18-Bit PulSAR® ADC in +5V Application

2.26

After filter, noise = 13 µV rms due to amp Signal = 8V p-p differential SNR = 107 dB

+5V

+2.1V

+1.75V

9.53k

10.0k8.45k

0.1µF

0.1µF

11.3k

4.02k

806

ADR444

+5VVREF = +4.096V 0.1µF

REF

+5V

VDD

IN+

IN–

+

+

–

–

CF

VIN = ± 10V

+2.1V +/– 2V

+2.1V – /+ 2V

ADA4941-1

41.2

41.2

3.9nF

3.9nF

AD7690, 400kSPSAD7691, 250kSPS18-BITPulSARADCs

LPF CUTOFF = 1MHz

VCM = +2.1VRR

0.1µF

VREF = +4.096V

INPUT RANGE =8.192V p-p DIFF.

10.2nV/Hz

SNR = 100dBFOR AD7690

ADA4937-1 Driving AD6645in +5V DC-Coupled Application

2.27

AD6645 SPECS:INPUT BW = 270MHz1 LSB = 134µVSNR = 75dB

5nV/Hz 1.57270106 = 103µV rms OUTPUT NOISE =

OUTPUT SNR = 20 log10310–6

0.778= 77.6dB

+

–

AD664514-BIT ADC

AIN–

AIN+

VIN

±1.1V

65.5

200

200

200

226

24.9

24.9

+2.4V

VOCM

ADA4937-1

0.1µF

0.1µF

0.1µF

+1.2V + / – 0.275V

+2.4V – / + 0.55V

+2.4V + / – 0.55V

2.2V p-pDIFFERENTIALINPUT SPAN

+5V

FROM 50SOURCE

fs = 80/105MSPS

VREF

5nV/Hz

+5V

C

Buffered and Unbuffered Differential ADC Inputs Structures

2.28

BUFFERED INPUTS

UNBUFFEREDINPUT

S5

VINB

+

-

A

VINA

CP

CPS1

S2

S3

S4

S6

CH

5pF

CH

5pF

S7ZIN

(A) (B)

(C)

GND

AVDD

VINB

R1 R1

R2 R2

INPUTBUFFER

SHA

VINAINPUT

BUFFERSHA

VREF

VINA

VINB

Input Impedance Model for Buffered and Unbuffered Input ADCs

2.29

R C

ADC

ZIN

BUFFERED INPUT

R and C are constant over frequency Typically:

R: 1 k – 2 kC: 1.5 pF – 3 pF

UNBUFFERED INPUT

R and C vary with both frequency and mode (track/hold)

Use Track mode R and C at the input frequency of interest

2.30

Unbuffered CMOS ADC (AD9236 12-Bit, 80 MSPS)Series Input Impedance in Track Mode and Hold Mode

REAL Z, HOLD

REAL Z, TRACK

IMAG Z, TRACK

IMAG Z, HOLD

ANALOG INPUT FREQUENCY (MHz)

SE

RIE

S R

EA

L I

MP

ED

AN

CE

(O

HM

S)

SE

RIE

S I

MA

GIN

AR

Y I

MP

ED

AN

CE

(p

F)

200

180

160

140

120

100

80

60

40

20

0

20

18

16

14

12

10

8

6

4

2

00 100 200 300 400 500 600 700 800 900 1000

RSZIN

CS

Basic Principles of Resonant Matching

2.31

(2 f )2 CS

RSZIN

CS

RPZIN

CP

LS/2

LS/2LP

LS = 1

(2 f )2 CPLP =

1

SERIES RESONANT @ f (70MHz) PARALLEL RESONANT @ f (70MHz)

ZIN = RS + j0 @ f ZIN = RP + j0 @ f

ADC ADC

Make XLS = XCS Make XLP = XCP

f

|ZIN|RP

|ZIN|

RSf

4k @ 70MHzFor AD9236

69 @ 70MHzFor AD9236

(69)

(4.3pF) (4k) (4.3pF)

(1.2µH) (1.2µH)

Before and After Adding Matching Analog Antialiasing Filter Network

2.32

SFDR Improved by 13.4 dB, SNR improved by 10.7 dB Note: Measured at maximum gain of 35 dB (gain code 255, high gain mode) using

76.8 MHz sampling clock

SAMPLING RATE = 76.8MSPSINPUT = 70MHzNOISE FLOOR = –84.3dBFSTHD = –63.9dBcSFDR = 68.0dBcSNR = 42.1dBFS

SAMPLING RATE = 76.8MSPSINPUT = 70MHzNOISE FLOOR = –84.3dBFSTHD = –63.9dBcSFDR = 68.0dBcSNR = 42.1dBFS

WITHOUT NETWORK

SAMPLING RATE = 76.8MSPSINPUT = 70MHzNOISE FLOOR = –95dBFSTHD = –76.8dBcSFDR = 81.4dBcSNR = 52.8dBFS

WITH NETWORK

33

Effective Aperture Delay TimeMeasured with Respect to ADC Input

SAMPLINGCLOCK

ANALOG INPUTSINEWAVE

ZERO CROSSING

+FS

–FS

0V

+te–te

te

' '

'

34

Effects of Aperture Jitterand Sampling Clock Jitter

ANALOGINPUT

TRACK

HOLD

D

dvdt

v dvdt

tRMS

= APERTURE JITTER

vRMS

NOMINALHELDOUTPUT

= t

= SLOPE = APERTURE JITTER ERRORD

D

D

35

Theoretical SNR and ENOB Due to Jittervs. Full-Scale Sinewave Analog Input Frequency

SNR(dB) ENOB

100

80

60

40

20

16

14

12

10

8

6

4

1 3 10 30 100

tj = 1ns

tj = 100ps

tj = 10ps

tj = 1ps

tj = 0.1ps

120

18

FULL-SCALE SINEWAVE ANALOG INPUT FREQUENCY (MHz)

SNR = 20log101

2pftj

tj = 50fs

Oscillator Requirements vs. Resolution and Analog Input Frequency

tj(ps)

37

Clock and Timing IC JitterS

igna

l to

Noi

se R

atio

(S

NR

) in

dB

Frequency of Fullscale Analog Input to ADC in MHz

ADCLK9XX Buffers

45.0

50.0

55.0

60.0

65.0

70.0

75.0

80.0

85.0

90.0

100 1000

50 fs

100 fs

200 fs

400 fs

800 fs

AIN = 200 MHz300MHz

400MHz

500MHz

AD951X distribution section only

AD951X using on-chip PLL and external VCO

AD9540 or AD995X DDS with external filter & AD9515

ADF4001, ADF4360 PLL synthesizers/VCOs

4.38

SNR Plot for the AD9445 Evaluation Boardwith Proper Decoupling

4.39

AD9445 Pinout Diagram

4.40

SNR Plot for an AD9445 Evaluation Board with Caps Removed from the Analog Supply

4.41

SNR Plot for an AD9445 Evaluation Board with Caps Removed from the Digital Supply

42

ADIsimADC

43

ADIsimADC

44

VisualAnalog™

45

SPI Controller

46

High Accuracy Sources

Resolution to 1 ppm One microvolt out of 1 volt

Everything matters External amplifiers – low offset, drift, noise Voltage reference – 1 ppm drift Layout and design

Applications MRI – magnetic resonance imaging

Precise gradient in magnetic field Test equipment

47

High Accuracy 18-Bit ±10 V Source

48

ADC References

Input level compared to reference ADC accuracy is relative to that reference

Internal reference Simplicity and lower cost Reference tuned to ADC performance Specifications all-inclusive

External reference Can be chosen for higher absolute accuracy Allows common reference in multiple-ADC system Common reference for sensor driver and ADC

Power supply as reference Lowest cost in most cases Noise is biggest issue Tolerance and drift may degrade accuracy

49

Voltage Reference Comparison

50

ADC References

51

Analog to Electronic Signal Processing

SENSOR(INPUT)

DIGITALPROCESSOR

AMP ADC

ACTUATOR(OUTPUT)

AMP DAC

52

DAC Signal Construction

t

SAMPLEDSIGNAL

t

RECONSTRUCTEDSIGNAL

1

fc

IDEAL TRANSITION TRANSITION WITHDOUBLET GLITCH

TRANSITION WITHUNIPOLAR (SKEW) GLITCH

t t t

53

DAC sin x/x Roll Off(Amplitude Normalized)

0.5fc fc 1.5fc 2fc 2.5fc 3fc

A = sin

ffc

ffc

1

f

A

t

–3.92dB

RECONSTRUCTEDSIGNAL

0

1

fc

IMAGESIMAGES

IMAGES

FS – FOUT FS + FOUT 2FS – FOUT 2FS + FOUT

54

LPF Required to Reject Image Frequency

Analog Filter Requirements for fo = 10 MHZ:

fc = 30 MSPS, and fc = 60 MSPS

55

fCLOCK = 30MSPS

dB

IMAGE

10 20 30 40 50 60 70 80

fo

ANALOG LPF

10 20 30 40 50 60 70 80

IMAGE

ANALOGLPF

FREQUENCY (MHz)

IMAGEIMAGEIMAGE

IMAGE

fo

fCLOCK = 60MSPS

dB

A

B

56

DAC Images (continued)

As the DAC output (FOUT) approaches Nyquist frequency, the images come closer together, making it extremely difficult to filter the image from the signal.

0 50 100 150 200 2500

101

102

X X X

FREQUENCY

PO

WE

R

In the above example, FOUT = 0.45 3 Fs

57

Interpolation

Maximum Output Frequency of Standard DAC is FCLOCK 2 (Nyquist Rate).

In an Interpolating D/A Converter, Digital Interpolation Filters and a PLL Clock Multiplier Are Used to Multiply the Input Data Rate to the DAC by a Factor of x Times the Clock Rate.

Produces an Image at x Times FSIGNAL, Smoothing the Sine Function and Simplifying the Filter Requirements and Digital Interface.

fSIGNAL fCLOCK = 2 x fSIGNALfSIGNAL fCLOCK = 8 x fSIGNAL

AD9775 TxDAC® 14-Bit CMOS DAC Core

58

CLOCK

14-BITLATCH

51-BITLATCH

31

CURRENT

SWITCHES

15

CURRENT

5 BINARYCURRENTSWITCHES

BITS 1-5

DECODE

5-TO-31

BITS 6-9

DECODE

4-TO-15

5 5

15154

31 315

14

CURRENT

OUTPUT

FS =2mA-20mA

SWITCHES

I = 512 LSB

I = 32 LSB

I = 1 LSB

5

NOTE: Differential Outputs Not Shown

Oversampling Interpolating TxDAC®

Simplified Block Diagram

59

fo

K•fcfc

LATCH LATCH DAC

LPF

DIGITALINTERPOLATION

FILTER

PLL

N N N N

TYPICAL APPLICATION: fc = 160MSPSfo = 50MHz

K = 2Image Frequency = 320– 50 = 270MHz

60

AD9772: 2X Interpolation vs. Nyquist DAC

Nyquist DAC AD9772 DAC

1st IMAGE 1st NEW IMAGE

IMAGES FILTERED BY DIGITAL 2X

INTERPOLATION

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What We Covered

Data converters in the signal chain

Basics of data conversion

Dynamic signal processing

Driving ADCs

Input structures

DACs for high speed and high resolution

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Design Resources Covered in This Session

Design tools & resources:

Ask technical questions and exchange ideas online in our EngineerZone® Support Community Choose a technology area from the homepage:

ez.analog.com Access the Design Conference community here:

www.analog.com/DC13community

Name Description URL

ADIsimADC Shows dynamic performance of ADCs in real applications

Voltage Reference Selection Wizard

Visual Analog

SPI Controller

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Visit the 16-Bit 250 kSPS 8-Channel, Isolated Data Acquisition System in the Exhibition Room

Circuits from the Lab® CN0254 is a cost effective, highly integrated 16-bit, 250 kSPS, 8-channel data acquisition system that can digitize ±10 V industrial level signals. The circuit also provides 2500 V rms isolation between the measurement circuit and the host controller, and the entire circuit is powered from a single isolated PWM controlled 5 V supply.

This demo board is available for purchase: www.analog.com/DC13-hardware

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16-Bit 250 kSPS 8-Channel Isolated Data Acquisition System—CN0254

65

The Data Conversion Handbook

The Data Conversion Handbook, edited by Walt Kester (Newnes, 2005), is written for design engineers who routinely use data converters and related circuitry. Comprising Data Converter History, Fundamentals of Sampled Data Systems, Data Converter Architectures, Data Converter Process Technology, Testing Data Converters, Interfacing to Data Converters, Data Converter Support Circuits, Data Converter Applications, and Hardware Design Techniques, it may be the ultimate expression of product "augmentation" as it relates to data converters. The last chapter discusses practical issues, including common pitfalls and solutions related to the non-ideal properties of passive components.The Data Conversion Handbook can be purchased from your favorite bookseller.

Individual chapters--or a zip file containing all chapters--of the original Basic Linear Design seminar notes can be downloaded by selecting the appropriate links below

http://www.analog.com/library/analogDialogue/archives/39-06/data_conversion_handbook.html

66

Linear Circuit Design Handbook

Linear Circuit Design Handbook, edited by Hank Zumbahlen (Newnes, 2008), bridges the gap between circuit component theory and practical circuit design. Effective analog circuit design requires a strong understanding of core linear devices and how they affect analog circuit design. This book provides complete coverage of important analog devices and how to use them in designing linear circuits, and serves as a useful learning tool and reference for design engineers involved in analog and mixed-signal design. It features complete coverage of analog circuit components for the practicing engineer; market-validated design information for all major types of linear circuits; practical advice on how to read op amp data sheets and how to choose off-the-shelf op amps; printed circuit board design issues; and over 1000 figures, including working circuit diagrams. Analog Dialogue readers can get a 20% discount when they order this book directly from Newnes. Enter discount code 92222.

Individual chapters--or a zip file containing all chapters--of the original Basic Linear Design seminar notes can be downloaded by selecting the appropriate links below

http://www.analog.com/library/analogDialogue/archives/43-09/linear_circuit_design_handbook.html