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May 4-6, 2015 Granlibakken Conference Center & Lodge, Lake Tahoe, CA http://www.esda.org/iew.htm The 9th International ESD Workshop (IEW) will be held at the Granlibakken Conference Center & Lodge, Lake Tahoe, CA. Granlibakken Conference Center and Lodge, located in beautiful Lake Tahoe, provides the perfect opportunity to meet in a relaxed, invigorating atmosphere and engage in discussions about the latest issues confronting the ESD community. The IEW will include invited seminars, technical sessions, special interest groups (SIGs), discussion groups, and invited speakers. The IEW especially invites submission of late-breaking exciting new research to stimulate 9th Annual International Electrostatic Discharge Workshop IEW Call For Presentations Abstract Submission Deadline Nov. 21, 2014 ® discussion and interaction around new ideas, encouraging new research topics. To maintain the unique IEW experience and provide ample opportunity for informal discussions, the 2015 IEW workshop presentation format for Technical sessions will begin with each author presenting a brief summary to highlight key findings, followed by an interactive poster-based discussion session among authors and attendees. The IEW is closely aligned with the EOS/ESD Symposium for collaborative conference activities. System-Level ESD/EOS Issues On- and off- chip IEC protection clamps, component/system ESD co-design case studies, cable discharge clamps, transient latch-up, design of system-level clamp circuits, system level ESD test issues and scan techniques, ESD-induced soft errors, and EOS field-failure case studies/ histories/solutions. Failure Analysis Techniques Locating failure sites, in particular CDM, imaging techniques, correlating FA identified damage site with ESD stress, distinguishing EOS-like failures from ESD failures, and unusual failure modes. Two special attention focus issues for IEW 2015 include: Power Management EOS/ESD The semiconductor technology development and IC design solutions that address efficient power management in systems have increased the complexity of ESD design challenges, and with expectations of solutions that also reduce cost, save space and work first time. The IEW invites contributions that address some of the ESD/EOS challenges in power management, including high performance IC on- chip power management, PMIC’s, DC/DC & AC/DC power devices, battery management, high voltage technologies and automotive applications. EDA EOS/ESD Tools Best Practices and Experiences With the heightened emphasis on design for reliability, design flows that utilize EDA EOS/ESD verification and simulation tools continue to remain as important as ever, especially for Fabless companies that may lack direct access to manufacturing and process data. Even with Foundry rule decks, understanding how shrinking design margins can impact EOS/ESD and the best practices to consider design compromises is a challenging task. IEW provides a great open forum to share, discuss and learn from the experiences of others, particular for those in the Fabless community. IEW 2015 strongly encourages submission of novel use of EDA tools and methods for IC and system level EOS/ESD verification and simulation. Areas the IEW would also like you to consider as abstract submission topics include: Technology Integration Issues ESD sensitivity with technology transfers, 3D IC ESD design issues, qualification challenges for different fabs, unusual problems of process interaction with ESD, process monitor methods, and technology scaling issues. Novel On-Chip Protection Clamps and Circuit Configurations New clamp devices and clamp configurations, methods to increase the failure threshold of protected devices, high voltage clamps for automotive and power amplifiers, out-of-the-ordinary chip protection concepts, and low-capacitance clamps for RF and SERDES. ESD Test Characterization, Methods, & Issues TLP & vfTLP debug and device characterization methods, correlation between TLP & vfTLP tests with standard qualification tests, HBM and CDM tester artifacts, issues relating test qual levels to real-world exposure, test chip methodology, cable discharge test methods, and test standards issues. Anomalous ESD Issues Random and unrepeatable ESD failures, Case Histories, ESD tester correlation issues, or unique window failures. For submission instructions see page two

2015 IEW call for papers

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The 9th International ESD Workshop (IEW) will be held at the Granlibakken Conference Center & Lodge, Lake Tahoe, CA. Granlibakken Conference Center and Lodge, located in beautiful Lake Tahoe, provides the perfect opportunity to meet in a relaxed, invigorating atmosphere and engage in discussions about the latest issues confronting the ESD community. The IEW will include invited seminars, technical sessions, special interest groups (SIGs), discussion groups, and invited speakers. The IEW especially invites submission of late-breaking exciting new research to stimulate discussion and interaction around new ideas, encouraging new research topics. To maintain the unique IEW experience and provide ample opportunity for informal discussions, the 2015 IEW workshop presentation format for Technical sessions will begin with each author presenting a brief summary to highlight key findings, followed by an interactive poster-based discussion session among authors and attendees. The IEW is closely aligned with the EOS/ESD Symposium for collaborative conference activities. Abstract Submission Deadline Nov. 21, 2014 Two special attention focus issues for IEW 2015 include: (1) Power Management EOS/ESD The semiconductor technology development and IC design solutions that address efficient power management in systems have increased the complexity of ESD design challenges, and with expectations of solutions that also reduce cost, save space and work first time. The IEW invites contributions that address some of the ESD/EOS challenges in power management, including high performance IC on-chip power management, PMIC’s, DC/DC & AC/DC power devices, battery management, high voltage technologies and automotive applications. (2) EDA EOS/ESD Tools Best Practices and Experiences With the heightened emphasis on design for reliability, design flows that utilize EDA EOS/ESD verification and simulation tools continue to remain as important as ever, especially for Fabless companies that may lack direct access to manufacturing and process data. Even with Foundry rule decks, understanding how shrinking design margins can impact EOS/ESD and the best practices to consider design compromises is a challenging task. IEW provides a great open forum to share, discuss and learn from the experiences of others, particular for those in the Fabless community.

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Page 1: 2015 IEW call for papers

May 4-6, 2015 Granlibakken Conference Center & Lodge, Lake Tahoe, CAhttp://www.esda.org/iew.htmThe 9th International ESD Workshop (IEW) will be held at the Granlibakken Conference Center & Lodge, Lake Tahoe, CA. Granlibakken Conference Center and Lodge, located in beautiful Lake Tahoe, provides the perfect opportunity to meet in a relaxed, invigorating atmosphere and engage in discussions about the latest issues confronting the ESD community.The IEW will include invited seminars, technical sessions, special interest groups (SIGs), discussion groups, and invited speakers. The IEW especially invites submission of late-breaking exciting new research to stimulate

9th Annual International Electrostatic Discharge Workshop

IEW Call For Presentations

Abstract Submission Deadline Nov. 21, 2014

®

discussion and interaction around new ideas, encouraging new research topics. To maintain the unique IEW experience and provide ample opportunity for informal discussions, the 2015 IEW workshop presentation format for Technical sessions will begin with each author presenting a brief summary to highlight key findings, followed by an interactive poster-based discussion session among authors and attendees. The IEW is closely aligned with the EOS/ESD Symposium for collaborative conference activities.

System-Level ESD/EOS IssuesOn- and off- chip IEC protection clamps, component/system ESD co-design case studies, cable discharge clamps, transient latch-up, design of system-level clamp circuits, system level ESD test issues and scan techniques, ESD-induced soft errors, and EOS field-failure case studies/histories/solutions.Failure Analysis TechniquesLocating failure sites, in particular CDM, imaging techniques, correlating FA identified damage site with ESD stress, distinguishing EOS-like failures from ESD failures, and unusual failure modes.

Two special attention focus issues for IEW 2015 include:Power Management EOS/ESDThe semiconductor technology development and IC design solutions that address efficient power management in systems have increased the complexity of ESD design challenges, and with expectations of solutions that also reduce cost, save space and work first time. The IEW invites contributions that address some of the ESD/EOS challenges in power management, including high performance IC on-chip power management, PMIC’s, DC/DC & AC/DC power devices, battery management, high voltage technologies and automotive applications.

EDA EOS/ESD Tools Best Practices and ExperiencesWith the heightened emphasis on design for reliability, design flows that utilize EDA EOS/ESD verification and simulation tools continue to remain as important as ever, especially for Fabless companies that may lack direct access to manufacturing and process data. Even with Foundry rule decks, understanding how shrinking design margins can impact EOS/ESD and the best practices to consider design compromises is a challenging task. IEW provides a great open forum to share, discuss and learn from the experiences of others, particular for those in the Fabless community.

IEW 2015 strongly encourages submission of novel use of EDA tools and methods for IC and system level EOS/ESD verification and simulation.

Areas the IEW would also like you to consider as abstract submission topics include: Technology Integration IssuesESD sensitivity with technology transfers, 3D IC ESD design issues, qualification challenges for different fabs, unusual problems of process interaction with ESD, process monitor methods, and technology scaling issues.Novel On-Chip Protection Clamps and Circuit ConfigurationsNew clamp devices and clamp configurations, methods to increase the failure threshold of protected devices, high voltage clamps for automotive and power amplifiers, out-of-the-ordinary chip protection concepts, and low-capacitance clamps for RF and SERDES.

ESD Test Characterization, Methods, & IssuesTLP & vfTLP debug and device characterization methods, correlation between TLP & vfTLP tests with standard qualification tests, HBM and CDM tester artifacts, issues relating test qual levels to real-world exposure, test chip methodology, cable discharge test methods, and test standards issues.Anomalous ESD IssuesRandom and unrepeatable ESD failures, Case Histories, ESD tester correlation issues, or unique window failures.

For submission instructions see page two

Page 2: 2015 IEW call for papers

2015 International Electrostatic Discharge Workshop c/o EOS/ESD Association, Inc.7900 Turin Road, Bldg. 3, Rome, NY 13440

Phone: 315-339-6937, Fax: 315-339-6793 [email protected], www.esda.org8/14/2014

Management Committee: Management Committee Chair: Matthew Hogan, Mentor GraphicsTechnical Program Chair: Ann Concannon, Texas InstrumentsSeminar Chair: Brett Carn, IntelInvited Speaker Chair: Souvick Mitra, IBM CorporationDiscussion Groups/Special Interest Groups Co-Chairs:Michael Khazhinsky, Silicon LaboratoriesScott Ruth, Freescale SemiconductorKeynote Speaker Chair:Robert Gauthier, IBM CorporationAudio/Visual Co-Chairs:Nathan Jack, IntelMichael Stockinger, Freescale Semiconductor Publicity Chair:Bart Keppens, Sofics Marise Bafleur, LAASSteve Voldman, Dr. Steven H. Voldman, LLCAdvisorsDimitri Linten, imecMirko Scholz, imecHarald Gossner, Intel Mobile CommunicationsMarkus Mergens, QPX GmbHTheo Smedes, NXP SemiconductorsWolfgang Stadler, Intel Mobile CommunicationsJames Miller, Freescale SemiconductorIndustry Council Advisor:Charvaka Duvvury ESDA IEW Business Unit Manager:Alan Righter, Analog DevicesESDA HQ Director of Operations:Lisa PimpinellaESDA Education Business Unit Manager:Ginger Hansel, Dangelmayer Associates

Technical Program CommitteeEfraim Aharoni, TowerJazzWarren Anderson, AMDPatrice Besse, FreescaleFabrice Blanc, ARMFabrice Caignet, LAASVictor Cao, Global FoundariesLorenzo Cerati, STMicroelectronicsMichael Chaine, MicronJames Di Sarro, Texas InstrumentsFarzan Farbiz, Texas InstrumentsDimitri Linten,imecTimothy Maloney, IntelMarkus Mergens, QPXJim Miller, FreescaleSouvick Mitra, IBMDionyz Pogany, Vienna Univ. of TechnologyWolfgang Reinprecht, AMSJavier Salcedo, Analog DevicesAkram Salman, Texas InstrumentsTheo Smedes, NXP SemiconductorsHoward Tang, UMCVladislav Vashchenko, Maxim Integrated ProductsJim Vinson, Intersil

9th Annual International Electrostatic Discharge Workshop

Submission InstructionsIn keeping with the informal character of this workshop, please prepare your abstract in the form of a short powerpoint presentation. After the title slide, the second slide of the presentation should describe the objective and significance in a 200 word summary. The presentation should not exceed 5 additional slides; with representative data and figures that will be the foundation for the poster you plan to present at the workshop. Please save your presentation abstract in pdf format and email including title, author affiliation, and e-mail address to [email protected] no later than November 21, 2014. The submission format is a PDF® file (Adobe Acrobat®). Notification of acceptance will occur by December 17, 2014. Final, full presentations for the workshop in MS PowerPoint® format must be received by April 14, 2015. There will be no published proceedings of the workshop. Due to an agreed alignment through the ESD Association, the presentation of your work at the IEW will not preclude a subsequent, but more detailed submission (=> 50% increase of data/graphs), to the EOS/ESD Symposium. For any questions please contact the Technical Program Chair, Ann Concannon ([email protected]). The IEW encourages student submissions by providing a 50% discount in registration fees for a limited number of student presenters. Proof of student status must be submitted along with the abstract for the workshop presentation.

Abstract Submission Deadline Nov. 21, 2014Lodging & FacilitiesGranlibakken is a Norwegian name meaning a hill sheltered by trees. Granlibakken Resort is family-owned, occupying 74 wooded acres in a picturesque mountain valley. Spectacular Lake Tahoe is just minutes away. Granlibakken Resort is at an elevation of 6,350 feet. Friendly but shy bears and other wildlife can be spotted on occasion. Accommodations afford plenty of privacy in a tranquil and relaxing Lake Tahoe hideaway. For pleasure, a full menu of Lake Tahoe’s outdoor recreation and indoor entertainment is available either at the resort or minutes away. The hospitality is European and the lifestyle is Lake Tahoe.Lodging for Sunday, Monday, Tuesday, and Wednesday nights, plus meals starting with Monday Breakfast-Thursday Lunch are included in the registration costs for the workshop. Attendees are allowed to bring guests who will be charged separate fees.Please check our web page at http://www.esda.org/iew.htm for regular updates on the workshop. As it becomes available, we will post information on the full technical program including the seminar topics, the keynote speaker, the technical sessions, as well as the discussion group and special interest group topics. In addition to peer-reviewed presentations, attendees will also have the option to present non-peer-reviewed posters at the workshop. Please also go to the web page for information on workshop registration, as well as the Lake Tahoe area.