Flip Flops

prepared by : Eng. Rania Elsadig

Sudan University of science and Technology

College of Engineering Biomedical Engineering

DepartmentDigital Design II

Third year

Clock Signal

Sequential logic circuits have memory Output is a function of input and present stateSequential circuits are synchronized by a periodic “clock” signal

SR Flip Flop

SR (set-reset) flip-flop based on two nor gates

SR Flip Flop

Edge triggered flip-flop changes only when the clock C changes

Edge Triggered Flip Flop

ExerciseFor a given S and R inputs to SR flip-flop, sketch the output signal Q

Q

t

Exercise

Positive Edge Triggered D Flip Flop

Positive-edge triggered flip-flop changes only on the rising edge of the clock C

Positive Edge Triggered D Flip Flop Cont.

ExerciseThe input D to a positive-edge triggered flip-flop is shownFind the output signal Q

Q

t

Exercise

Positive Edge Triggered JK Flip Flop

D = J Q' + K' Q

Positive Edge Triggered JK Flip Flop Cont.

T ( Toggle) Flip Flop

D = T Q = T Q' + T' Q+

T ( Toggle) Flip Flop Cont.

D flip-flop with asynchronous reset

17

Master-slave D-type flip-flop

D Q

CLK

Input

Master D latch

D Q Output

Slave D latchX

• How to make into negative edge-triggered D-type flip-flop?

Analysis of Clocked Sequential Circuits

State diagrams:• How do we characterize logic circuits?– Combinational circuits: Truth tables – Sequential circuits: State diagrams

• First draw the states– States Unique circuit configurations

• Second draw the transitions between states– Transitions Changes in state caused by inputs

Example1: A Sequential Circuit with D Flip Flops

State Table for the Circuit (ex1)

State Diagram for the Circuit (ex1)

Example2: A Sequential Circuit with D Flip Flops

example3: A Sequential Circuit with JK Flip Flops

State Table & Diagram for the Circuit (ex3)

example4: A Sequential Circuit with T Flip Flops

State Table for the Circuit (ex4)